feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@a

feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I8947660bb96fdf2f178e560b387e4bc93bf68abf

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feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add supp

feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add support to
parse and configure this DTB in BL31. NT_FW_CONFIG contains the platform
information which is needed by BL33.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ib1fb5417c36523eb2ec02aa22845218de68809aa

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refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1

* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure,

refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1

* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure, we hold a copy of EL1, EL2
system registers, per world per PE. This context structure is
enormous and will continue to grow bigger with the addition of
new features incorporating new registers.

* Ideally, EL3 should save and restore the system registers at its next
lower exception level, which is EL2 in majority of the configurations.

* This patch aims at optimising the memory allocation in cases, when
the members from the context structure are unused. So el1 system
register context must be omitted when lower EL is always x-EL2.

* "CTX_INCLUDE_EL2_REGS" is the internal build flag which gets set,
when SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1.
It indicates, the system registers at EL2 are context switched for
the respective build configuration. Here, there is no need to save
and restore EL1 system registers, while x-EL2 is enabled.

Henceforth, this patch addresses this issue, by taking out the EL1
context at all possible places, while EL2 (CTX_INCLUDE_EL2_REGS) is
enabled, there by saving memory.

Change-Id: Ifddc497d3c810e22a15b1c227a731bcc133c2f4a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to wr

chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.

Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory alloca

refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.

Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.

Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
rest

feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.

* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.

* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.

* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".

* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.

Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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chore(rdv3): rename platform RD-Fremont to RD-V3

Arm has decided to rename RD-Fremont to RD-V3 to align with its
existing product lineup, such as RD-V1, RD-V2, etc. This change
replaces all occurenc

chore(rdv3): rename platform RD-Fremont to RD-V3

Arm has decided to rename RD-Fremont to RD-V3 to align with its
existing product lineup, such as RD-V1, RD-V2, etc. This change
replaces all occurences of "Fremont" with "V3" in file names and
contents.

Change-Id: I302103492f962a7ac74854633ad68701b2a7f420
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed

feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ic390517a8810df195a2582793b81afdbff5ffa15

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feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms

Add MHUv3 doorbell channel information to scmi_channel_plat_info_t for
third generation of multichip Neoverse reference design

feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms

Add MHUv3 doorbell channel information to scmi_channel_plat_info_t for
third generation of multichip Neoverse reference design platforms.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ie4ebf47a10f2f6e33c7ecfc8008e30bacc62bf3d

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feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms

Define and use a new scmi_channel_plat_info_t structure specific to
third generation Neoverse platforms in order to use MHUv3 do

feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms

Define and use a new scmi_channel_plat_info_t structure specific to
third generation Neoverse platforms in order to use MHUv3 doorbell
channels. The structure uses the existing mhu_ring_doorbell method for
ring_doorbell implementation.

Signed-off-by: Shriram K <shriram.k@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Icf3be5305df94ba944038a4d4fdf0ccf32168650

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feat(rdfremont): initialize GPT on GPC SMMU block

GPC SMMU does granule protection checks (GPC) for accesses originating
from the system control block and GIC on RD-Fremont platforms. The GPC
check

feat(rdfremont): initialize GPT on GPC SMMU block

GPC SMMU does granule protection checks (GPC) for accesses originating
from the system control block and GIC on RD-Fremont platforms. The GPC
check on this is disabled by the boot firmware. Configure the GPC SMMU
to enable GPC.

The transactions on GPC SMMU should be allowed during boot stages so
don't perform smmuv3_security_init() for this SMMU instance.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I3400c57fe264582a45c6a26f9dae8c669e8a8047

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feat(rdfremont): update Root registers page offset for SMMUv3

SMMUv3 with RME on RD-Fremont platform variants supports Root and Realm
register pages. The page offset for Root and Realm register page

feat(rdfremont): update Root registers page offset for SMMUv3

SMMUv3 with RME on RD-Fremont platform variants supports Root and Realm
register pages. The page offset for Root and Realm register pages is a
platform configurable option. Update the Root registers page offset for
RD-Fremont platform variants.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ib3df7d7b9e54219d49b4d77a1fc5846096f1c78c

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feat(rdfremont): add implementation for GPT setup

Since GPT setup has been delegated to the platform, add an
implementation for plat_bl2_gpt_setup in accordance with the
specification for RD-Fremont

feat(rdfremont): add implementation for GPT setup

Since GPT setup has been delegated to the platform, add an
implementation for plat_bl2_gpt_setup in accordance with the
specification for RD-Fremont variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1ff47249ce304f1c188850282d92c64cae463383

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feat(rdfremont): add support for RD-Fremont-Cfg2

Add board support for RD-Fremont-Cfg2 platform, which is a quad chip
variant of RD-Fremont. Each chip has reduced core count of four CPUs as
compared

feat(rdfremont): add support for RD-Fremont-Cfg2

Add board support for RD-Fremont-Cfg2 platform, which is a quad chip
variant of RD-Fremont. Each chip has reduced core count of four CPUs as
compared to single chip RD-Fremont platform.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9b79f0eef210afecaa15e381414479027617e44a

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feat(rdfremont): add support for RD-Fremont-Cfg1

Add the required source and header files to support RD-Fremont-Cfg1,
which is a variant of RD-Fremont. RD-Fremont-Cfg1 hosts a smaller mesh
and lower

feat(rdfremont): add support for RD-Fremont-Cfg1

Add the required source and header files to support RD-Fremont-Cfg1,
which is a variant of RD-Fremont. RD-Fremont-Cfg1 hosts a smaller mesh
and lower number of cores when compared with RD-Fremont.

Signed-off-by: Shriram K <shriram.k@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I720b0e76174123c8aab64b39e9468b28614607b9

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feat(rdfremont): add support for RD-Fremont

Add the required source and header files to support RD-Fremont.
Additionally, create a makefile for building the platform.

Co-developed-by: Harry Moulton

feat(rdfremont): add support for RD-Fremont

Add the required source and header files to support RD-Fremont.
Additionally, create a makefile for building the platform.

Co-developed-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I03b6913b08d488c86a5f4638ef6cd8b0f5c43a9a

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feat(neoverse-rd): add multichip pas entries

RD-Fremont-Cfg2, the quad-chip variant of RD-Fremont supports 8 DRAM
banks compared to RD-Fremont and RD-Fremont-Cfg1, which only support 2.
Therefore, d

feat(neoverse-rd): add multichip pas entries

RD-Fremont-Cfg2, the quad-chip variant of RD-Fremont supports 8 DRAM
banks compared to RD-Fremont and RD-Fremont-Cfg1, which only support 2.
Therefore, define PAS entry mappings for all the DRAM banks, so that
they could be utilized on the multichip variant.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ief235581c0066a95528235b9821646f864e14d3a

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feat(neoverse-rd): add pas definitions for third gen platforms

Since the GPT setup is now delegated to the platform, each platform
needs to include PAS definitions according to its specifications. T

feat(neoverse-rd): add pas definitions for third gen platforms

Since the GPT setup is now delegated to the platform, each platform
needs to include PAS definitions according to its specifications. This
commit adds PAS definitions specifically tailored for RD-Fremont
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1a23029a74401fb1faa70bb6c2e66093ed08c45a

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feat(neoverse-rd): add DRAM layout for third gen platforms

Given the differences in memory map of the third generation reference
design platforms, it is necessary to move away from the common DRAM
l

feat(neoverse-rd): add DRAM layout for third gen platforms

Given the differences in memory map of the third generation reference
design platforms, it is necessary to move away from the common DRAM
layout present as part of arm_def.h. Therefore, introduce definitions
and necessary carveouts within DRAM to define a new DRAM layout for
these platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I79af066f41259f147febdc3c00447db5be995799

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feat(neoverse-rd): add SRAM layout for third gen platforms

Given the differences in memory map and additional RME requirements for
the V3 CPU based platforms, it is necessary to move away from the c

feat(neoverse-rd): add SRAM layout for third gen platforms

Given the differences in memory map and additional RME requirements for
the V3 CPU based platforms, it is necessary to move away from the common
SRAM layout present as part of arm_def.h. Therefore, introduce
definitions and necessary carveouts within SRAM to define a new SRAM
layout for these platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2d0ef65abde66da7523dd9e09036c7803978570c

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feat(neoverse-rd): add firmware definitions for third gen platforms

Add firmware definitions for the third generation of platforms. The
following files are added -

- nrd_css_fw_def3.h: for CSS firm

feat(neoverse-rd): add firmware definitions for third gen platforms

Add firmware definitions for the third generation of platforms. The
following files are added -

- nrd_css_fw_def3.h: for CSS firmware definitions
- nrd_ros_fw_def3.h : for RoS firmware definitions
- nrd_plat_arm_def3.h: for platform port macros

All the common files for these platforms are housed under nrd3
directory.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I085d609cfe1686d28d1c467fb34d45af47e00eb6

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feat(neoverse-rd): add RoS definitions for third gen platforms

Add RoS definitions for third generation of platforms. Common
definitions for such platforms would be housed in the nrd3 directory
unde

feat(neoverse-rd): add RoS definitions for third gen platforms

Add RoS definitions for third generation of platforms. Common
definitions for such platforms would be housed in the nrd3 directory
under includes.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2062c71676f27b4d17a3069b955565670f62a76c

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feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in th

feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in the
nrd3 directory under includes.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Id271ebdf5dcc1d7b598606c313208ab85662795d

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refactor(neoverse-rd): remove soc_css.mk from common makefile

The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 with

refactor(neoverse-rd): remove soc_css.mk from common makefile

The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 within the
SOC specification. However, as none of the Neoverse reference design
platforms necessitate the initialization of PCIe or NIC400, remove the
soc_css.mk from the common makefile.

Additionally, empty initialization functions for PCIe and NIC400 are
added to satisfy the requirements of the plat/arm common code, which
expects these functions to be present.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935

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refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file

Consolidate and organize platform port definitions within the
nrd_plat_arm_def2.h file. Remove direct references to addresses with
correspond

refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file

Consolidate and organize platform port definitions within the
nrd_plat_arm_def2.h file. Remove direct references to addresses with
corresponding RoS or CSS definitions.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic43cff90d2cf45760b3f808732754cf7c05a814a

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