feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cp

feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cpu objects within a memory that is local to a particular node.
RD-V3-Cfg2 in this case has the per-cpu objects distributed across
different SRAMs present on the system.

introduce platform-specific helper functions to enhance the per_cpu
framework. Adds a helper function to zero init per_cpu sections,
ensuring clean initialization of per-cpu data. Introduces a function
to obtain the base address of per_cpu sections, facilitating efficient
access to per-CPU data structures. Enhances the per_cpu framework's
capability to handle platform-specific requirements.

These additions are crucial for maintaining the integrity and
performance of per-cpu operations.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I550c6b5c59f80fbe2b746a1261cda857f4fb1990

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feat(fvp): allocate L0 GPT at the top of SRAM

This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unu

feat(fvp): allocate L0 GPT at the top of SRAM

This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unused gaps in SRAM.
Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are
defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro.

Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(rdv3): define SPMC manifest base address

ARM_SPMC_MANIFEST_BASE defines the base address of the SPMC manifest
used by BL32. In the non-RESET_TO_BL31 case, it is defined relative to
the top of T

feat(rdv3): define SPMC manifest base address

ARM_SPMC_MANIFEST_BASE defines the base address of the SPMC manifest
used by BL32. In the non-RESET_TO_BL31 case, it is defined relative to
the top of Trusted SRAM. However, for RESET_TO_BL31, the
PLAT_ARM_SPMC_MANIFEST_BASE macro can be used to set it to a different
location which is then used to populate ARM_SPMC_MANIFEST_BASE.

As the RD-V3 platform and its variants have a different SRAM layout
compared to that defined in arm_def.h, define the
PLAT_ARM_SPMC_MANIFEST_BASE macro to an address suitable for this
platform and its variants.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I36e1eb21ab3d1c68bddb52c62198fcdfc40d8993

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feat(rdv3): add carveout for BL32 image

Add and map the carveout for loading Hafnium as BL32 image. Also define
PLAT_ARM_SP_MAX_SIZE as 3 MB for secure partitions.

Signed-off-by: Rohit Mathew <rohi

feat(rdv3): add carveout for BL32 image

Add and map the carveout for loading Hafnium as BL32 image. Also define
PLAT_ARM_SP_MAX_SIZE as 3 MB for secure partitions.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I2845eb6807a127c9f6b92de2dabc9a58d25bd4d4

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feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled

Larger stack size is needed when S-EL2 SPMC is enabled. This is required
because BL31 xlat map framework makes more nested calls w

feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled

Larger stack size is needed when S-EL2 SPMC is enabled. This is required
because BL31 xlat map framework makes more nested calls when this
feature is enabled.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: Ib3f2abf38b576ba96402dab4ba995d8b648b4cc7

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fix(rdv3): fix comment for DRAM1 carveout size

Corrected the comment for the size of NRD_CSS_DRAM1_CARVEOUT_SIZE
(0x0C000000) from 117MB to 192MB

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com

fix(rdv3): fix comment for DRAM1 carveout size

Corrected the comment for the size of NRD_CSS_DRAM1_CARVEOUT_SIZE
(0x0C000000) from 117MB to 192MB

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I289d37f50e70b936f717d4579d73882fac28ee95

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feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@a

feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I8947660bb96fdf2f178e560b387e4bc93bf68abf

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feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add supp

feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add support to
parse and configure this DTB in BL31. NT_FW_CONFIG contains the platform
information which is needed by BL33.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ib1fb5417c36523eb2ec02aa22845218de68809aa

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feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed

feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ic390517a8810df195a2582793b81afdbff5ffa15

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feat(rdfremont): initialize GPT on GPC SMMU block

GPC SMMU does granule protection checks (GPC) for accesses originating
from the system control block and GIC on RD-Fremont platforms. The GPC
check

feat(rdfremont): initialize GPT on GPC SMMU block

GPC SMMU does granule protection checks (GPC) for accesses originating
from the system control block and GIC on RD-Fremont platforms. The GPC
check on this is disabled by the boot firmware. Configure the GPC SMMU
to enable GPC.

The transactions on GPC SMMU should be allowed during boot stages so
don't perform smmuv3_security_init() for this SMMU instance.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I3400c57fe264582a45c6a26f9dae8c669e8a8047

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feat(rdfremont): update Root registers page offset for SMMUv3

SMMUv3 with RME on RD-Fremont platform variants supports Root and Realm
register pages. The page offset for Root and Realm register page

feat(rdfremont): update Root registers page offset for SMMUv3

SMMUv3 with RME on RD-Fremont platform variants supports Root and Realm
register pages. The page offset for Root and Realm register pages is a
platform configurable option. Update the Root registers page offset for
RD-Fremont platform variants.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ib3df7d7b9e54219d49b4d77a1fc5846096f1c78c

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feat(rdfremont): add implementation for GPT setup

Since GPT setup has been delegated to the platform, add an
implementation for plat_bl2_gpt_setup in accordance with the
specification for RD-Fremont

feat(rdfremont): add implementation for GPT setup

Since GPT setup has been delegated to the platform, add an
implementation for plat_bl2_gpt_setup in accordance with the
specification for RD-Fremont variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1ff47249ce304f1c188850282d92c64cae463383

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feat(rdfremont): add support for RD-Fremont-Cfg2

Add board support for RD-Fremont-Cfg2 platform, which is a quad chip
variant of RD-Fremont. Each chip has reduced core count of four CPUs as
compared

feat(rdfremont): add support for RD-Fremont-Cfg2

Add board support for RD-Fremont-Cfg2 platform, which is a quad chip
variant of RD-Fremont. Each chip has reduced core count of four CPUs as
compared to single chip RD-Fremont platform.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9b79f0eef210afecaa15e381414479027617e44a

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feat(rdfremont): add support for RD-Fremont-Cfg1

Add the required source and header files to support RD-Fremont-Cfg1,
which is a variant of RD-Fremont. RD-Fremont-Cfg1 hosts a smaller mesh
and lower

feat(rdfremont): add support for RD-Fremont-Cfg1

Add the required source and header files to support RD-Fremont-Cfg1,
which is a variant of RD-Fremont. RD-Fremont-Cfg1 hosts a smaller mesh
and lower number of cores when compared with RD-Fremont.

Signed-off-by: Shriram K <shriram.k@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I720b0e76174123c8aab64b39e9468b28614607b9

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feat(rdfremont): add support for RD-Fremont

Add the required source and header files to support RD-Fremont.
Additionally, create a makefile for building the platform.

Co-developed-by: Harry Moulton

feat(rdfremont): add support for RD-Fremont

Add the required source and header files to support RD-Fremont.
Additionally, create a makefile for building the platform.

Co-developed-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I03b6913b08d488c86a5f4638ef6cd8b0f5c43a9a

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feat(neoverse-rd): add multichip pas entries

RD-Fremont-Cfg2, the quad-chip variant of RD-Fremont supports 8 DRAM
banks compared to RD-Fremont and RD-Fremont-Cfg1, which only support 2.
Therefore, d

feat(neoverse-rd): add multichip pas entries

RD-Fremont-Cfg2, the quad-chip variant of RD-Fremont supports 8 DRAM
banks compared to RD-Fremont and RD-Fremont-Cfg1, which only support 2.
Therefore, define PAS entry mappings for all the DRAM banks, so that
they could be utilized on the multichip variant.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ief235581c0066a95528235b9821646f864e14d3a

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feat(neoverse-rd): add pas definitions for third gen platforms

Since the GPT setup is now delegated to the platform, each platform
needs to include PAS definitions according to its specifications. T

feat(neoverse-rd): add pas definitions for third gen platforms

Since the GPT setup is now delegated to the platform, each platform
needs to include PAS definitions according to its specifications. This
commit adds PAS definitions specifically tailored for RD-Fremont
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1a23029a74401fb1faa70bb6c2e66093ed08c45a

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feat(neoverse-rd): add DRAM layout for third gen platforms

Given the differences in memory map of the third generation reference
design platforms, it is necessary to move away from the common DRAM
l

feat(neoverse-rd): add DRAM layout for third gen platforms

Given the differences in memory map of the third generation reference
design platforms, it is necessary to move away from the common DRAM
layout present as part of arm_def.h. Therefore, introduce definitions
and necessary carveouts within DRAM to define a new DRAM layout for
these platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I79af066f41259f147febdc3c00447db5be995799

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feat(neoverse-rd): add SRAM layout for third gen platforms

Given the differences in memory map and additional RME requirements for
the V3 CPU based platforms, it is necessary to move away from the c

feat(neoverse-rd): add SRAM layout for third gen platforms

Given the differences in memory map and additional RME requirements for
the V3 CPU based platforms, it is necessary to move away from the common
SRAM layout present as part of arm_def.h. Therefore, introduce
definitions and necessary carveouts within SRAM to define a new SRAM
layout for these platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2d0ef65abde66da7523dd9e09036c7803978570c

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feat(neoverse-rd): add firmware definitions for third gen platforms

Add firmware definitions for the third generation of platforms. The
following files are added -

- nrd_css_fw_def3.h: for CSS firm

feat(neoverse-rd): add firmware definitions for third gen platforms

Add firmware definitions for the third generation of platforms. The
following files are added -

- nrd_css_fw_def3.h: for CSS firmware definitions
- nrd_ros_fw_def3.h : for RoS firmware definitions
- nrd_plat_arm_def3.h: for platform port macros

All the common files for these platforms are housed under nrd3
directory.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I085d609cfe1686d28d1c467fb34d45af47e00eb6

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feat(neoverse-rd): add RoS definitions for third gen platforms

Add RoS definitions for third generation of platforms. Common
definitions for such platforms would be housed in the nrd3 directory
unde

feat(neoverse-rd): add RoS definitions for third gen platforms

Add RoS definitions for third generation of platforms. Common
definitions for such platforms would be housed in the nrd3 directory
under includes.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2062c71676f27b4d17a3069b955565670f62a76c

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feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in th

feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in the
nrd3 directory under includes.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Id271ebdf5dcc1d7b598606c313208ab85662795d

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