Merge "fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest" into integration

refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both n

refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both needing it, two copies of this file are made in Trusted DRAM and
SRAM. The copy in Trusted DRAM is a workaround stemming from memory
constraints in SRAM. We temporarily map the range of memory in Trusted
DRAM into BL31 to allow it to consume the configuration. In principle,
however, BL31 execution should be limited to SRAM, hence reduce the
maximum size of the HW_CONFIG to 16KB in order to accommodate it in
SRAM. This is possible since in practice, the HW_CONFIG on FVP is only
about 11KB.

Change-Id: Idb5dc0637b402562b7177a2b4e2464c4f3f67da7
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717

refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717f4c115cb0babd2c614d6f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(fvp): don't check MPIDRs with the power controller in BL1

The core platform layer requires an implementation for the
`plat_core_pos_by_mpidr` function. This implementation is currently
missing i

fix(fvp): don't check MPIDRs with the power controller in BL1

The core platform layer requires an implementation for the
`plat_core_pos_by_mpidr` function. This implementation is currently
missing in BL1, which causes undefined reference errors when linking
with LTO.

The FVP platform source file providing this implementation is the
`fvp_topology.c` file, so this change adds it to the BL1 sources for the
FVP.

However, the implementation of this function reaches out to the FVP
power controller driver - `fvp_pm.c` - to validate the MPIDR, and this
file has at least two other dependencies:

- `spe.c`
- `arm_gicvX.c`

Pulling these in correctly is no simple job, so I am simply removing the
power controller validation in BL1 builds.

Change-Id: I56ddf1d799f5fe7f5b0fb2b046f7fe8232b07b27
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest

FFA_RXTX_MAP now requires the buffers to be in non-secure memory. This
patch ensures that a region of non-secure memory is available so th

fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest

FFA_RXTX_MAP now requires the buffers to be in non-secure memory. This
patch ensures that a region of non-secure memory is available so that
tftf tests can pass.

Change-Id: I9daf3182e0dcb73d2bf5a5baffb1b4b78c724dcb
Signed-off-by: Karl Meakin <karl.meakin@arm.com>

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feat(rme): pass console info via RMM-EL3 ifc

This patch modifies the boot manifest to add console information to
be passed from EL3 to RMM.

Boot manifest version is bumped to v0.3

Signed-off-by: H

feat(rme): pass console info via RMM-EL3 ifc

This patch modifies the boot manifest to add console information to
be passed from EL3 to RMM.

Boot manifest version is bumped to v0.3

Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Iedc4e640fb7a4450ce5ce966ae76936d1b7b742d

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refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE

fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE (Statistical Profiling Extension) is implemented
and enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is "implemented and enabled".

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I30182c3893416af65b55fca9a913cb4512430434
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(S

fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(Statistical Profiling Extension) is enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is enabled, ENABLE_SPE_FOR_NS=1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Iaeb258c8b0a92e93d70b7dad6ba59d1056aeb135
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level

Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level for region validity
feat(tc): add dummy TRNG support to be able to boot pVMs
feat(tc): get the parent component provided DPE context_handle
feat(tc): share DPE context handle with child component
feat(tc): add DPE context handle node to device tree
feat(tc): add DPE backend to the measured boot framework
feat(auth): add explicit entries for key OIDs
feat(dice): add DPE driver to measured boot
feat(dice): add client API for DICE Protection Environment
feat(dice): add QCBOR library as a dependency of DPE
feat(dice): add typedefs from the Open DICE repo
docs(changelog): add 'dice' scope
refactor(tc): align image identifier string macros
refactor(fvp): align image identifier string macros
refactor(imx8m): align image identifier string macros
refactor(qemu): align image identifier string macros
fix(measured-boot): add missing image identifier string
refactor(measured-boot): move metadata size macros to a common header
refactor(measured-boot): move image identifier strings to a common header

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fix(cpus): workaround for Cortex-X4 erratum 2701112

Cortex-X4 erratum 2701112 is cat B erratum that applies to
revision r0p0 and is fixed in r0p1. This erratum affects
system configurations that do

fix(cpus): workaround for Cortex-X4 erratum 2701112

Cortex-X4 erratum 2701112 is cat B erratum that applies to
revision r0p0 and is fixed in r0p1. This erratum affects
system configurations that do not use an Arm interconnect IP.

The workaround for this erratum is not implemented in EL3.
The erratum can be enabled/disabled on a platform level.
The flag is used when the errata ABI feature is enabled and can
assist the Kernel in the process of mitigation of the erratum.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: I8ede1ee75b0ea1658369a0646d8af91d44a8759b
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(fvp): align image identifier string macros

Macros were renamed, align with new names.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I85d03164f580d9c41b7955482914d20188e559e5

Merge changes from topic "sm/framework_optimize" into integration

* changes:
chore: rearrange the fvp_cpu_errata.mk file
fix(cpus): add erratum 2701951 to Cortex-X3's list
refactor(errata-abi)

Merge changes from topic "sm/framework_optimize" into integration

* changes:
chore: rearrange the fvp_cpu_errata.mk file
fix(cpus): add erratum 2701951 to Cortex-X3's list
refactor(errata-abi): workaround platforms non-arm interconnect
refactor(errata-abi): optimize errata ABI using errata framework

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Merge "fix(el3-spmc): add datastore linker script markers" into integration

chore: rearrange the fvp_cpu_errata.mk file

Change-Id: I3959bdf5852c5714f2238f61493a931b3c857a20
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

fix(cpus): add erratum 2701951 to Cortex-X3's list

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Corte

fix(cpus): add erratum 2701951 to Cortex-X3's list

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(errata-abi): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level

refactor(errata-abi): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP flag. The ABI helps assist the
Kernel in the process of mitigation for the following errata:

Cortex-A715: erratum 2701951
Neoverse V2: erratum 2719103
Cortex-A710: erratum 2701952
Cortex-X2: erratum 2701952
Neoverse N2: erratum 2728475
Neoverse V1: erratum 2701953
Cortex-A78: erratum 2712571
Cortex-A78AE: erratum 2712574
Cortex-A78C: erratum 2712575

Change-Id: Ie86b7212d731a79e2a0c07649e69234e733cd78d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(errata-abi): optimize errata ABI using errata framework

Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structur

refactor(errata-abi): optimize errata ABI using errata framework

Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structures created by the errata framework.

Change-Id: I1a60d3e4f116b6254fb45426f43ff1b21771af89
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(el3-spmc): add datastore linker script markers

Datastore symbol used by EL3 SPMC is not relocated at
boot time when using ENABLE_PIE=1.
Use linker script markers instead of symbol.

Signed-off-b

fix(el3-spmc): add datastore linker script markers

Datastore symbol used by EL3 SPMC is not relocated at
boot time when using ENABLE_PIE=1.
Use linker script markers instead of symbol.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: If22d2fc8deacc74c73d7dc51bb70093935d9fa2b

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feat(smmu): separate out smmuv3_security_init from smmuv3_init

Split the smmuv3_init() to separate smmuv3_security_init() from it in
order to allow skipping the default deny policy on reset for cert

feat(smmu): separate out smmuv3_security_init from smmuv3_init

Split the smmuv3_init() to separate smmuv3_security_init() from it in
order to allow skipping the default deny policy on reset for certain
SMMUv3 implementations.
Additionally, fix a couple of MISRA warnings.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I2127943e709dd1ded34145bd022c930e351bbb4a

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Merge "fix(bl2): make BL2 SRAM footprint flexible" into integration

fix(bl2): make BL2 SRAM footprint flexible

On FVP's the default SRAM size is severly restrictive. However, more
recent models support larger SRAM configurations (> 256 Kb). We
introduced the flag FV

fix(bl2): make BL2 SRAM footprint flexible

On FVP's the default SRAM size is severly restrictive. However, more
recent models support larger SRAM configurations (> 256 Kb). We
introduced the flag FVP_TRUSTED_SRAM_SIZE to allow for TF to handle
different configurations.

BL31 automatically benefits from this optimisation since it starts from
the bottom of shared memory, and runs up to the end of SRAM. Increase
the size of all BL2 builds in proportion to FVP_TRUSTED_SRAM_SIZE so
that BL2 covers around a third of SRAM.

Change-Id: Idf37e8cb86507ea44b97ac8b3b90fffefe13f57a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): remove left-over RSS usage

Remove any residual RSS usage in the FVP platform, complementing the
changes made in commit dea307fd6cca2dad56867e757804224a8654bc38.

Signed-off-by: Manish V B

feat(fvp): remove left-over RSS usage

Remove any residual RSS usage in the FVP platform, complementing the
changes made in commit dea307fd6cca2dad56867e757804224a8654bc38.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9ced272503456361610ec0c7783d270349233926

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Merge changes from topic "od/sme" into integration

* changes:
fix(fvp): permit enabling SME for SPD=spmd
feat(spmd): pass SMCCCv1.3 SVE hint to lower EL

fix(fvp): permit enabling SME for SPD=spmd

Essentially revert [1] to permit specifying SME support along with
SPD=spmd on FVP platform.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmwar

fix(fvp): permit enabling SME for SPD=spmd

Essentially revert [1] to permit specifying SME support along with
SPD=spmd on FVP platform.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20764

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iab15d5a4c966b9f5b265ccde6711765e242abeaa

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