1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 35# progbits limit. We need a way to build all useful configurations while waiting 36# on the fvp to increase its SRAM size. The problem is twofild: 37# 1. the cleanup that introduced these enables cleaned up tf-a a little too 38# well and things that previously (incorrectly) were enabled, no longer are. 39# A bunch of CI configs build subtly incorrectly and this combo makes it 40# necessary to forcefully and unconditionally enable them here. 41# 2. the progbits limit is exceeded only when the tsp is involved. However, 42# there are tsp CI configs that run on very high architecture revisions so 43# disabling everything isn't an option. 44# The fix is to enable everything, as before. When the tsp is included, though, 45# we need to slim the size down. In that case, disable all optional features, 46# that will not be present in CI when the tsp is. 47# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 48# for it. 49# TODO: make all of this unconditional (or only base the condition on 50# ARM_ARCH_* when the makefile supports it). 51ifneq (${DRTM_SUPPORT}, 1) 52ifneq (${SPD}, tspd) 53 ENABLE_FEAT_AMU := 2 54 ENABLE_FEAT_AMUv1p1 := 2 55 ENABLE_FEAT_HCX := 2 56 ENABLE_FEAT_RNG := 2 57 ENABLE_FEAT_TWED := 2 58 ENABLE_FEAT_GCS := 2 59ifeq (${ARCH}, aarch64) 60ifeq (${SPM_MM}, 0) 61ifeq (${CTX_INCLUDE_FPREGS}, 0) 62 ENABLE_SME_FOR_NS := 2 63 ENABLE_SME2_FOR_NS := 2 64endif 65endif 66endif 67endif 68 69# enable unconditionally for all builds 70ifeq (${ARCH}, aarch64) 71 ENABLE_BRBE_FOR_NS := 2 72 ENABLE_TRBE_FOR_NS := 2 73endif 74ENABLE_SYS_REG_TRACE_FOR_NS := 2 75ENABLE_FEAT_CSV2_2 := 2 76ENABLE_FEAT_CSV2_3 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_MTE_PERM := 2 80ENABLE_FEAT_VHE := 2 81CTX_INCLUDE_NEVE_REGS := 2 82ENABLE_FEAT_SEL2 := 2 83ENABLE_TRF_FOR_NS := 2 84ENABLE_FEAT_ECV := 2 85ENABLE_FEAT_FGT := 2 86ENABLE_FEAT_TCR2 := 2 87ENABLE_FEAT_S2PIE := 2 88ENABLE_FEAT_S1PIE := 2 89ENABLE_FEAT_S2POE := 2 90ENABLE_FEAT_S1POE := 2 91endif 92 93# The FVP platform depends on this macro to build with correct GIC driver. 94$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 95 96# Pass FVP_CLUSTER_COUNT to the build system. 97$(eval $(call add_define,FVP_CLUSTER_COUNT)) 98 99# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 100$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 101 102# Pass FVP_MAX_PE_PER_CPU to the build system. 103$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 104 105# Pass FVP_GICR_REGION_PROTECTION to the build system. 106$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 107 108# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 109$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 110 111# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 112# choose the CCI driver , else the CCN driver 113ifeq ($(FVP_CLUSTER_COUNT), 0) 114$(error "Incorrect cluster count specified for FVP port") 115else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 116FVP_INTERCONNECT_DRIVER := FVP_CCI 117else 118FVP_INTERCONNECT_DRIVER := FVP_CCN 119endif 120 121$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 122 123# Choose the GIC sources depending upon the how the FVP will be invoked 124ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 125 126# The GIC model (GIC-600 or GIC-500) will be detected at runtime 127GICV3_SUPPORT_GIC600 := 1 128GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 129 130# Include GICv3 driver files 131include drivers/arm/gic/v3/gicv3.mk 132 133FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 134 plat/common/plat_gicv3.c \ 135 plat/arm/common/arm_gicv3.c 136 137 ifeq ($(filter 1,${RESET_TO_BL2} \ 138 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 139 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 140 endif 141 142else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 143 144# No GICv4 extension 145GIC_ENABLE_V4_EXTN := 0 146$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 147 148# Include GICv2 driver files 149include drivers/arm/gic/v2/gicv2.mk 150 151FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 152 plat/common/plat_gicv2.c \ 153 plat/arm/common/arm_gicv2.c 154 155FVP_DT_PREFIX := fvp-base-gicv2-psci 156else 157$(error "Incorrect GIC driver chosen on FVP port") 158endif 159 160ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 161FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 162else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 163FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 164 plat/arm/common/arm_ccn.c 165else 166$(error "Incorrect CCN driver chosen on FVP port") 167endif 168 169FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 170 plat/arm/board/fvp/fvp_security.c \ 171 plat/arm/common/arm_tzc400.c 172 173 174PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 175 -Iinclude/lib/psa 176 177 178PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 179 180FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 181 182ifeq (${ARCH}, aarch64) 183 184# select a different set of CPU files, depending on whether we compile for 185# hardware assisted coherency cores or not 186ifeq (${HW_ASSISTED_COHERENCY}, 0) 187# Cores used without DSU 188 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 189 lib/cpus/aarch64/cortex_a53.S \ 190 lib/cpus/aarch64/cortex_a57.S \ 191 lib/cpus/aarch64/cortex_a72.S \ 192 lib/cpus/aarch64/cortex_a73.S 193else 194# Cores used with DSU only 195 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 196 # AArch64-only cores 197 # TODO: add all cores to the appropriate lists 198 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 199 lib/cpus/aarch64/cortex_a65ae.S \ 200 lib/cpus/aarch64/cortex_a76.S \ 201 lib/cpus/aarch64/cortex_a76ae.S \ 202 lib/cpus/aarch64/cortex_a77.S \ 203 lib/cpus/aarch64/cortex_a78.S \ 204 lib/cpus/aarch64/cortex_a78_ae.S \ 205 lib/cpus/aarch64/cortex_a78c.S \ 206 lib/cpus/aarch64/cortex_a710.S \ 207 lib/cpus/aarch64/neoverse_n_common.S \ 208 lib/cpus/aarch64/neoverse_n1.S \ 209 lib/cpus/aarch64/neoverse_n2.S \ 210 lib/cpus/aarch64/neoverse_v1.S \ 211 lib/cpus/aarch64/neoverse_e1.S \ 212 lib/cpus/aarch64/cortex_x2.S \ 213 lib/cpus/aarch64/cortex_x4.S \ 214 lib/cpus/aarch64/cortex_gelas.S \ 215 lib/cpus/aarch64/nevis.S \ 216 lib/cpus/aarch64/travis.S 217 endif 218 # AArch64/AArch32 cores 219 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 220 lib/cpus/aarch64/cortex_a75.S 221endif 222 223else 224FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 225 lib/cpus/aarch32/cortex_a57.S \ 226 lib/cpus/aarch32/cortex_a53.S 227endif 228 229BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 230 drivers/arm/sp805/sp805.c \ 231 drivers/delay_timer/delay_timer.c \ 232 drivers/io/io_semihosting.c \ 233 lib/semihosting/semihosting.c \ 234 lib/semihosting/${ARCH}/semihosting_call.S \ 235 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 236 plat/arm/board/fvp/fvp_bl1_setup.c \ 237 plat/arm/board/fvp/fvp_err.c \ 238 plat/arm/board/fvp/fvp_io_storage.c \ 239 ${FVP_CPU_LIBS} \ 240 ${FVP_INTERCONNECT_SOURCES} 241 242ifeq (${USE_SP804_TIMER},1) 243BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 244else 245BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 246endif 247 248 249BL2_SOURCES += drivers/arm/sp805/sp805.c \ 250 drivers/io/io_semihosting.c \ 251 lib/utils/mem_region.c \ 252 lib/semihosting/semihosting.c \ 253 lib/semihosting/${ARCH}/semihosting_call.S \ 254 plat/arm/board/fvp/fvp_bl2_setup.c \ 255 plat/arm/board/fvp/fvp_err.c \ 256 plat/arm/board/fvp/fvp_io_storage.c \ 257 plat/arm/common/arm_nor_psci_mem_protect.c \ 258 ${FVP_SECURITY_SOURCES} 259 260 261ifeq (${COT_DESC_IN_DTB},1) 262BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 263endif 264 265ifeq (${ENABLE_RME},1) 266BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 267 268BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 269 plat/arm/board/fvp/fvp_realm_attest_key.c 270endif 271 272ifeq (${ENABLE_FEAT_RNG_TRAP},1) 273BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 274endif 275 276ifeq (${RESET_TO_BL2},1) 277BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 278 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 279 ${FVP_CPU_LIBS} \ 280 ${FVP_INTERCONNECT_SOURCES} 281endif 282 283ifeq (${USE_SP804_TIMER},1) 284BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 285endif 286 287BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 288 ${FVP_SECURITY_SOURCES} 289 290ifeq (${USE_SP804_TIMER},1) 291BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 292endif 293 294BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 295 drivers/arm/smmu/smmu_v3.c \ 296 drivers/delay_timer/delay_timer.c \ 297 drivers/cfi/v2m/v2m_flash.c \ 298 lib/utils/mem_region.c \ 299 plat/arm/board/fvp/fvp_bl31_setup.c \ 300 plat/arm/board/fvp/fvp_console.c \ 301 plat/arm/board/fvp/fvp_pm.c \ 302 plat/arm/board/fvp/fvp_topology.c \ 303 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 304 plat/arm/common/arm_nor_psci_mem_protect.c \ 305 ${FVP_CPU_LIBS} \ 306 ${FVP_GIC_SOURCES} \ 307 ${FVP_INTERCONNECT_SOURCES} \ 308 ${FVP_SECURITY_SOURCES} 309 310# Support for fconf in BL31 311# Added separately from the above list for better readability 312ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 313BL31_SOURCES += lib/fconf/fconf.c \ 314 lib/fconf/fconf_dyn_cfg_getter.c \ 315 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 316 317BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 318 319ifeq (${SEC_INT_DESC_IN_FCONF},1) 320BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 321endif 322 323endif 324 325ifeq (${USE_SP804_TIMER},1) 326BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 327else 328BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 329endif 330 331# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 332ifdef UNIX_MK 333FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 334FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 335 ${PLAT}_fw_config.dts \ 336 ${PLAT}_tb_fw_config.dts \ 337 ${PLAT}_soc_fw_config.dts \ 338 ${PLAT}_nt_fw_config.dts \ 339 ) 340 341FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 342FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 343FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 344FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 345 346ifeq (${SPD},tspd) 347FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 348FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 349 350# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 351$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 352endif 353 354ifeq (${TRANSFER_LIST}, 1) 355include lib/transfer_list/transfer_list.mk 356endif 357 358ifeq (${SPD},spmd) 359 360ifeq ($(ARM_SPMC_MANIFEST_DTS),) 361ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 362endif 363 364FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 365FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 366 367# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 368$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 369endif 370 371# Add the FW_CONFIG to FIP and specify the same to certtool 372$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 373# Add the TB_FW_CONFIG to FIP and specify the same to certtool 374$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 375# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 376$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 377# Add the NT_FW_CONFIG to FIP and specify the same to certtool 378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 379 380FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 381$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 382 383# Add the HW_CONFIG to FIP and specify the same to certtool 384$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 385endif 386 387# Enable dynamic mitigation support by default 388DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 389 390ifneq (${ENABLE_FEAT_AMU},0) 391BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 392 lib/cpus/aarch64/cpuamu_helpers.S 393 394ifeq (${HW_ASSISTED_COHERENCY}, 1) 395BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 396 lib/cpus/aarch64/neoverse_n1_pubsub.c 397endif 398endif 399 400ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 401 ifeq (${ENABLE_FEAT_RAS},1) 402 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 403 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 404 else 405 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 406 endif 407 else 408 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 409 endif 410endif 411 412ifneq (${ENABLE_STACK_PROTECTOR},0) 413PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 414endif 415 416# Enable the dynamic translation tables library. 417ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 418 ifeq (${ARCH},aarch32) 419 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 420 else # AArch64 421 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 422 endif 423endif 424 425ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 426 ifeq (${ARCH},aarch32) 427 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 428 else # AArch64 429 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 430 ifeq (${SPD},tspd) 431 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 432 endif 433 endif 434endif 435 436ifeq (${USE_DEBUGFS},1) 437 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 438endif 439 440# Add support for platform supplied linker script for BL31 build 441$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 442 443ifneq (${RESET_TO_BL2}, 0) 444 override BL1_SOURCES = 445endif 446 447include plat/arm/board/common/board_common.mk 448include plat/arm/common/arm_common.mk 449 450ifeq (${MEASURED_BOOT},1) 451BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 452 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 453 lib/psa/measured_boot.c 454 455BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 456 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 457 lib/psa/measured_boot.c 458endif 459 460ifeq (${DRTM_SUPPORT}, 1) 461BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 462 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 463 plat/arm/board/fvp/fvp_drtm_err.c \ 464 plat/arm/board/fvp/fvp_drtm_measurement.c \ 465 plat/arm/board/fvp/fvp_drtm_stub.c \ 466 plat/arm/common/arm_dyn_cfg.c \ 467 plat/arm/board/fvp/fvp_err.c 468endif 469 470ifeq (${TRUSTED_BOARD_BOOT}, 1) 471BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 472BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 473 474# FVP being a development platform, enable capability to disable Authentication 475# dynamically if TRUSTED_BOARD_BOOT is set. 476DYN_DISABLE_AUTH := 1 477endif 478 479ifeq (${SPMC_AT_EL3}, 1) 480PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 481endif 482 483PSCI_OS_INIT_MODE := 1 484 485ifeq (${SPD},spmd) 486BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 487endif 488 489# Test specific macros, keep them at bottom of this file 490$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 491ifeq (${PLATFORM_TEST_EA_FFH}, 1) 492 ifeq (${FFH_SUPPORT}, 0) 493 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 494 endif 495 496endif 497 498$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 499ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 500 ifeq (${ENABLE_FEAT_RAS}, 0) 501 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 502 endif 503 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 504 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 505 endif 506endif 507 508$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 509ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 510 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 511 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 512 endif 513 ifeq (${ENABLE_SPMD_LP}, 0) 514 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 515 endif 516 ifeq (${ENABLE_FEAT_RAS}, 0) 517 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 518 endif 519 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 520 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 521 endif 522endif 523 524ifeq (${ERRATA_ABI_SUPPORT}, 1) 525include plat/arm/board/fvp/fvp_cpu_errata.mk 526endif 527 528# Build macro necessary for running SPM tests on FVP platform 529$(eval $(call add_define,PLAT_TEST_SPM)) 530