1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/el3_runtime/context_el2.h> 11 #include <lib/el3_runtime/cpu_data.h> 12 #include <lib/utils_def.h> 13 14 /******************************************************************************* 15 * Constants that allow assembler code to access members of and the 'gp_regs' 16 * structure at their correct offsets. 17 ******************************************************************************/ 18 #define CTX_GPREGS_OFFSET U(0x0) 19 #define CTX_GPREG_X0 U(0x0) 20 #define CTX_GPREG_X1 U(0x8) 21 #define CTX_GPREG_X2 U(0x10) 22 #define CTX_GPREG_X3 U(0x18) 23 #define CTX_GPREG_X4 U(0x20) 24 #define CTX_GPREG_X5 U(0x28) 25 #define CTX_GPREG_X6 U(0x30) 26 #define CTX_GPREG_X7 U(0x38) 27 #define CTX_GPREG_X8 U(0x40) 28 #define CTX_GPREG_X9 U(0x48) 29 #define CTX_GPREG_X10 U(0x50) 30 #define CTX_GPREG_X11 U(0x58) 31 #define CTX_GPREG_X12 U(0x60) 32 #define CTX_GPREG_X13 U(0x68) 33 #define CTX_GPREG_X14 U(0x70) 34 #define CTX_GPREG_X15 U(0x78) 35 #define CTX_GPREG_X16 U(0x80) 36 #define CTX_GPREG_X17 U(0x88) 37 #define CTX_GPREG_X18 U(0x90) 38 #define CTX_GPREG_X19 U(0x98) 39 #define CTX_GPREG_X20 U(0xa0) 40 #define CTX_GPREG_X21 U(0xa8) 41 #define CTX_GPREG_X22 U(0xb0) 42 #define CTX_GPREG_X23 U(0xb8) 43 #define CTX_GPREG_X24 U(0xc0) 44 #define CTX_GPREG_X25 U(0xc8) 45 #define CTX_GPREG_X26 U(0xd0) 46 #define CTX_GPREG_X27 U(0xd8) 47 #define CTX_GPREG_X28 U(0xe0) 48 #define CTX_GPREG_X29 U(0xe8) 49 #define CTX_GPREG_LR U(0xf0) 50 #define CTX_GPREG_SP_EL0 U(0xf8) 51 #define CTX_GPREGS_END U(0x100) 52 53 /******************************************************************************* 54 * Constants that allow assembler code to access members of and the 'el3_state' 55 * structure at their correct offsets. Note that some of the registers are only 56 * 32-bits wide but are stored as 64-bit values for convenience 57 ******************************************************************************/ 58 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 59 #define CTX_SCR_EL3 U(0x0) 60 #define CTX_ESR_EL3 U(0x8) 61 #define CTX_RUNTIME_SP U(0x10) 62 #define CTX_SPSR_EL3 U(0x18) 63 #define CTX_ELR_EL3 U(0x20) 64 #define CTX_PMCR_EL0 U(0x28) 65 #define CTX_IS_IN_EL3 U(0x30) 66 /* Constants required in supporting nested exception in EL3 */ 67 #define CTX_SAVED_ELR_EL3 U(0x38) 68 /* 69 * General purpose flag, to save various EL3 states 70 * FFH mode : Used to identify if handling nested exception 71 * KFH mode : Used as counter value 72 */ 73 #define CTX_NESTED_EA_FLAG U(0x40) 74 #if FFH_SUPPORT 75 #define CTX_SAVED_ESR_EL3 U(0x48) 76 #define CTX_SAVED_SPSR_EL3 U(0x50) 77 #define CTX_SAVED_GPREG_LR U(0x58) 78 #define CTX_EL3STATE_END U(0x60) /* Align to the next 16 byte boundary */ 79 #else 80 #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ 81 #endif /* FFH_SUPPORT */ 82 83 /******************************************************************************* 84 * Constants that allow assembler code to access members of and the 85 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 86 * registers are only 32-bits wide but are stored as 64-bit values for 87 * convenience 88 ******************************************************************************/ 89 #define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 90 #define CTX_SPSR_EL1 U(0x0) 91 #define CTX_ELR_EL1 U(0x8) 92 #define CTX_SCTLR_EL1 U(0x10) 93 #define CTX_TCR_EL1 U(0x18) 94 #define CTX_CPACR_EL1 U(0x20) 95 #define CTX_CSSELR_EL1 U(0x28) 96 #define CTX_SP_EL1 U(0x30) 97 #define CTX_ESR_EL1 U(0x38) 98 #define CTX_TTBR0_EL1 U(0x40) 99 #define CTX_TTBR1_EL1 U(0x48) 100 #define CTX_MAIR_EL1 U(0x50) 101 #define CTX_AMAIR_EL1 U(0x58) 102 #define CTX_ACTLR_EL1 U(0x60) 103 #define CTX_TPIDR_EL1 U(0x68) 104 #define CTX_TPIDR_EL0 U(0x70) 105 #define CTX_TPIDRRO_EL0 U(0x78) 106 #define CTX_PAR_EL1 U(0x80) 107 #define CTX_FAR_EL1 U(0x88) 108 #define CTX_AFSR0_EL1 U(0x90) 109 #define CTX_AFSR1_EL1 U(0x98) 110 #define CTX_CONTEXTIDR_EL1 U(0xa0) 111 #define CTX_VBAR_EL1 U(0xa8) 112 113 /* 114 * If the platform is AArch64-only, there is no need to save and restore these 115 * AArch32 registers. 116 */ 117 #if CTX_INCLUDE_AARCH32_REGS 118 #define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ 119 #define CTX_SPSR_UND U(0xb8) 120 #define CTX_SPSR_IRQ U(0xc0) 121 #define CTX_SPSR_FIQ U(0xc8) 122 #define CTX_DACR32_EL2 U(0xd0) 123 #define CTX_IFSR32_EL2 U(0xd8) 124 #define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ 125 #else 126 #define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ 127 #endif /* CTX_INCLUDE_AARCH32_REGS */ 128 129 /* 130 * If the timer registers aren't saved and restored, we don't have to reserve 131 * space for them in the context 132 */ 133 #if NS_TIMER_SWITCH 134 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0)) 135 #define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8)) 136 #define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10)) 137 #define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18)) 138 #define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20)) 139 #define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */ 140 #else 141 #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END 142 #endif /* NS_TIMER_SWITCH */ 143 144 #if ENABLE_FEAT_MTE2 145 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) 146 #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) 147 #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) 148 #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) 149 150 /* Align to the next 16 byte boundary */ 151 #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) 152 #else 153 #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END 154 #endif /* ENABLE_FEAT_MTE2 */ 155 156 /* 157 * End of system registers. 158 */ 159 #define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END 160 161 /******************************************************************************* 162 * Constants that allow assembler code to access members of and the 'fp_regs' 163 * structure at their correct offsets. 164 ******************************************************************************/ 165 # define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 166 #if CTX_INCLUDE_FPREGS 167 #define CTX_FP_Q0 U(0x0) 168 #define CTX_FP_Q1 U(0x10) 169 #define CTX_FP_Q2 U(0x20) 170 #define CTX_FP_Q3 U(0x30) 171 #define CTX_FP_Q4 U(0x40) 172 #define CTX_FP_Q5 U(0x50) 173 #define CTX_FP_Q6 U(0x60) 174 #define CTX_FP_Q7 U(0x70) 175 #define CTX_FP_Q8 U(0x80) 176 #define CTX_FP_Q9 U(0x90) 177 #define CTX_FP_Q10 U(0xa0) 178 #define CTX_FP_Q11 U(0xb0) 179 #define CTX_FP_Q12 U(0xc0) 180 #define CTX_FP_Q13 U(0xd0) 181 #define CTX_FP_Q14 U(0xe0) 182 #define CTX_FP_Q15 U(0xf0) 183 #define CTX_FP_Q16 U(0x100) 184 #define CTX_FP_Q17 U(0x110) 185 #define CTX_FP_Q18 U(0x120) 186 #define CTX_FP_Q19 U(0x130) 187 #define CTX_FP_Q20 U(0x140) 188 #define CTX_FP_Q21 U(0x150) 189 #define CTX_FP_Q22 U(0x160) 190 #define CTX_FP_Q23 U(0x170) 191 #define CTX_FP_Q24 U(0x180) 192 #define CTX_FP_Q25 U(0x190) 193 #define CTX_FP_Q26 U(0x1a0) 194 #define CTX_FP_Q27 U(0x1b0) 195 #define CTX_FP_Q28 U(0x1c0) 196 #define CTX_FP_Q29 U(0x1d0) 197 #define CTX_FP_Q30 U(0x1e0) 198 #define CTX_FP_Q31 U(0x1f0) 199 #define CTX_FP_FPSR U(0x200) 200 #define CTX_FP_FPCR U(0x208) 201 #if CTX_INCLUDE_AARCH32_REGS 202 #define CTX_FP_FPEXC32_EL2 U(0x210) 203 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ 204 #else 205 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ 206 #endif /* CTX_INCLUDE_AARCH32_REGS */ 207 #else 208 #define CTX_FPREGS_END U(0) 209 #endif /* CTX_INCLUDE_FPREGS */ 210 211 /******************************************************************************* 212 * Registers related to CVE-2018-3639 213 ******************************************************************************/ 214 #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) 215 #define CTX_CVE_2018_3639_DISABLE U(0) 216 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 217 218 /******************************************************************************* 219 * Registers related to ARMv8.3-PAuth. 220 ******************************************************************************/ 221 #define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 222 #if CTX_INCLUDE_PAUTH_REGS 223 #define CTX_PACIAKEY_LO U(0x0) 224 #define CTX_PACIAKEY_HI U(0x8) 225 #define CTX_PACIBKEY_LO U(0x10) 226 #define CTX_PACIBKEY_HI U(0x18) 227 #define CTX_PACDAKEY_LO U(0x20) 228 #define CTX_PACDAKEY_HI U(0x28) 229 #define CTX_PACDBKEY_LO U(0x30) 230 #define CTX_PACDBKEY_HI U(0x38) 231 #define CTX_PACGAKEY_LO U(0x40) 232 #define CTX_PACGAKEY_HI U(0x48) 233 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 234 #else 235 #define CTX_PAUTH_REGS_END U(0) 236 #endif /* CTX_INCLUDE_PAUTH_REGS */ 237 238 /******************************************************************************* 239 * Registers related to ARMv8.2-MPAM. 240 ******************************************************************************/ 241 #define CTX_MPAM_REGS_OFFSET (CTX_PAUTH_REGS_OFFSET + CTX_PAUTH_REGS_END) 242 #if CTX_INCLUDE_MPAM_REGS 243 #define CTX_MPAM2_EL2 U(0x0) 244 #define CTX_MPAMHCR_EL2 U(0x8) 245 #define CTX_MPAMVPM0_EL2 U(0x10) 246 #define CTX_MPAMVPM1_EL2 U(0x18) 247 #define CTX_MPAMVPM2_EL2 U(0x20) 248 #define CTX_MPAMVPM3_EL2 U(0x28) 249 #define CTX_MPAMVPM4_EL2 U(0x30) 250 #define CTX_MPAMVPM5_EL2 U(0x38) 251 #define CTX_MPAMVPM6_EL2 U(0x40) 252 #define CTX_MPAMVPM7_EL2 U(0x48) 253 #define CTX_MPAMVPMV_EL2 U(0x50) 254 #define CTX_MPAM_REGS_END U(0x60) 255 #else 256 #define CTX_MPAM_REGS_END U(0x0) 257 #endif /* CTX_INCLUDE_MPAM_REGS */ 258 259 /******************************************************************************* 260 * Registers initialised in a per-world context. 261 ******************************************************************************/ 262 #define CTX_CPTR_EL3 U(0x0) 263 #define CTX_ZCR_EL3 U(0x8) 264 #define CTX_MPAM3_EL3 U(0x10) 265 #define CTX_PERWORLD_EL3STATE_END U(0x18) 266 267 #ifndef __ASSEMBLER__ 268 269 #include <stdint.h> 270 271 #include <lib/cassert.h> 272 273 /* 274 * Common constants to help define the 'cpu_context' structure and its 275 * members below. 276 */ 277 #define DWORD_SHIFT U(3) 278 #define DEFINE_REG_STRUCT(name, num_regs) \ 279 typedef struct name { \ 280 uint64_t ctx_regs[num_regs]; \ 281 } __aligned(16) name##_t 282 283 /* Constants to determine the size of individual context structures */ 284 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 285 #define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT) 286 287 #if CTX_INCLUDE_FPREGS 288 # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 289 #endif 290 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 291 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 292 #if CTX_INCLUDE_PAUTH_REGS 293 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 294 #endif 295 #if CTX_INCLUDE_MPAM_REGS 296 # define CTX_MPAM_REGS_ALL (CTX_MPAM_REGS_END >> DWORD_SHIFT) 297 #endif 298 299 /* 300 * AArch64 general purpose register context structure. Usually x0-x18, 301 * lr are saved as the compiler is expected to preserve the remaining 302 * callee saved registers if used by the C runtime and the assembler 303 * does not touch the remaining. But in case of world switch during 304 * exception handling, we need to save the callee registers too. 305 */ 306 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 307 308 /* 309 * AArch64 EL1 system register context structure for preserving the 310 * architectural state during world switches. 311 */ 312 DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL); 313 314 /* 315 * AArch64 floating point register context structure for preserving 316 * the floating point state during switches from one security state to 317 * another. 318 */ 319 #if CTX_INCLUDE_FPREGS 320 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 321 #endif 322 323 /* 324 * Miscellaneous registers used by EL3 firmware to maintain its state 325 * across exception entries and exits 326 */ 327 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 328 329 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 330 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 331 332 /* Registers associated to ARMv8.3-PAuth */ 333 #if CTX_INCLUDE_PAUTH_REGS 334 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 335 #endif 336 337 /* Registers associated to ARMv8.2 MPAM */ 338 #if CTX_INCLUDE_MPAM_REGS 339 DEFINE_REG_STRUCT(mpam, CTX_MPAM_REGS_ALL); 340 #endif 341 342 /* 343 * Macros to access members of any of the above structures using their 344 * offsets 345 */ 346 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 347 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 348 = (uint64_t) (val)) 349 350 /* 351 * Top-level context structure which is used by EL3 firmware to preserve 352 * the state of a core at the next lower EL in a given security state and 353 * save enough EL3 meta data to be able to return to that EL and security 354 * state. The context management library will be used to ensure that 355 * SP_EL3 always points to an instance of this structure at exception 356 * entry and exit. 357 */ 358 typedef struct cpu_context { 359 gp_regs_t gpregs_ctx; 360 el3_state_t el3state_ctx; 361 el1_sysregs_t el1_sysregs_ctx; 362 363 #if CTX_INCLUDE_FPREGS 364 fp_regs_t fpregs_ctx; 365 #endif 366 cve_2018_3639_t cve_2018_3639_ctx; 367 368 #if CTX_INCLUDE_PAUTH_REGS 369 pauth_t pauth_ctx; 370 #endif 371 372 #if CTX_INCLUDE_MPAM_REGS 373 mpam_t mpam_ctx; 374 #endif 375 376 #if CTX_INCLUDE_EL2_REGS 377 el2_sysregs_t el2_sysregs_ctx; 378 #endif 379 380 } cpu_context_t; 381 382 /* 383 * Per-World Context. 384 * It stores registers whose values can be shared across CPUs. 385 */ 386 typedef struct per_world_context { 387 uint64_t ctx_cptr_el3; 388 uint64_t ctx_zcr_el3; 389 uint64_t ctx_mpam3_el3; 390 } per_world_context_t; 391 392 extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 393 394 /* Macros to access members of the 'cpu_context_t' structure */ 395 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 396 #if CTX_INCLUDE_FPREGS 397 # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 398 #endif 399 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) 400 #if CTX_INCLUDE_EL2_REGS 401 # define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) 402 #endif 403 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 404 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 405 #if CTX_INCLUDE_PAUTH_REGS 406 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 407 #endif 408 #if CTX_INCLUDE_MPAM_REGS 409 # define get_mpam_ctx(h) (&((cpu_context_t *) h)->mpam_ctx) 410 #endif 411 412 /* 413 * Compile time assertions related to the 'cpu_context' structure to 414 * ensure that the assembler and the compiler view of the offsets of 415 * the structure members is the same. 416 */ 417 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), 418 assert_core_context_gp_offset_mismatch); 419 420 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), 421 assert_core_context_el3state_offset_mismatch); 422 423 CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), 424 assert_core_context_el1_sys_offset_mismatch); 425 426 #if CTX_INCLUDE_FPREGS 427 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), 428 assert_core_context_fp_offset_mismatch); 429 #endif /* CTX_INCLUDE_FPREGS */ 430 431 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), 432 assert_core_context_cve_2018_3639_offset_mismatch); 433 434 #if CTX_INCLUDE_PAUTH_REGS 435 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), 436 assert_core_context_pauth_offset_mismatch); 437 #endif /* CTX_INCLUDE_PAUTH_REGS */ 438 439 #if CTX_INCLUDE_MPAM_REGS 440 CASSERT(CTX_MPAM_REGS_OFFSET == __builtin_offsetof(cpu_context_t, mpam_ctx), 441 assert_core_context_mpam_offset_mismatch); 442 #endif /* CTX_INCLUDE_MPAM_REGS */ 443 444 /* 445 * Helper macro to set the general purpose registers that correspond to 446 * parameters in an aapcs_64 call i.e. x0-x7 447 */ 448 #define set_aapcs_args0(ctx, x0) do { \ 449 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 450 } while (0) 451 #define set_aapcs_args1(ctx, x0, x1) do { \ 452 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 453 set_aapcs_args0(ctx, x0); \ 454 } while (0) 455 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 456 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 457 set_aapcs_args1(ctx, x0, x1); \ 458 } while (0) 459 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 460 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 461 set_aapcs_args2(ctx, x0, x1, x2); \ 462 } while (0) 463 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 464 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 465 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 466 } while (0) 467 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 468 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 469 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 470 } while (0) 471 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 472 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 473 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 474 } while (0) 475 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 476 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 477 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 478 } while (0) 479 480 /******************************************************************************* 481 * Function prototypes 482 ******************************************************************************/ 483 #if CTX_INCLUDE_FPREGS 484 void fpregs_context_save(fp_regs_t *regs); 485 void fpregs_context_restore(fp_regs_t *regs); 486 #endif 487 488 #endif /* __ASSEMBLER__ */ 489 490 #endif /* CONTEXT_H */ 491