feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIF

feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIFEST_SIZE with PAGE_SIZE taken
from PLAT_ARM_HW_CONFIG_SIZE by reducing it as amount of
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

2. increase HAND_OFF transfer list size as much as
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

Change-Id: I56be7783ee4d257e33148f1f623a64bc498f1955
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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Merge changes from topic "bk/pabandon_cleanup" into integration

* changes:
feat(cpus): add pabandon support to the Alto cpu
feat(psci): optimise clock init on a pabandon
feat(psci): check that

Merge changes from topic "bk/pabandon_cleanup" into integration

* changes:
feat(cpus): add pabandon support to the Alto cpu
feat(psci): optimise clock init on a pabandon
feat(psci): check that CPUs handled a pabandon
feat(psci): make pabandon support generic
refactor(psci): unify coherency exit between AArch64 and AArch32
refactor(psci): absorb psci_power_down_wfi() into common code
refactor(platforms): remove usage of psci_power_down_wfi
fix(cm): disable SPE/TRBE correctly

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feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

T

feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

The only exception to this are older secure world dispatchers, which
assume that a CPU_SUSPEND call will be terminal and therefore can
clobber context. This was patched over in common code and hidden behind
a flag. This patch moves this to the dispatchers themselves.

Dispatchers that don't register svc_suspend{_finish} are unaffected.
Those that do must save the NS context before clobbering it and
restoring in only in case of a pabandon. Due to this operation being
non-trivial, this patch makes the assumption that these dispatchers will
only be present on hardware that does not support pabandon and therefore
does not add any contexting for them. In case this assumption ever
changes, asserts are added that should alert us of this change.

Change-Id: I94a907515b782b4d2136c0d274246cfe1d567c0e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(cpufeat): add support for FEAT_FGWTE3" into integration

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MP

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MPAM3_EL3: Not trapped as they are part of the EL3 context.
SCTLR_EL3: Not trapped since it is overwritten during
powerdown sequence(Included when HW_ASSISTED_COHERENCY=1)

TPIDR_EL3: Excluded due to its use in crash reporting(It is included
when CRASH_REPORTING=0)

Reference:
https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/FGWTE3-EL3--Fine-Grained-Write-Traps-EL3

Change-Id: Idcb32aaac7d65a0b0e5c90571af00e01a4e9edb1
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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Merge changes from topic "mb/lfa-core-work" into integration

* changes:
docs(maintainers): add myself as code owner for LFA service
docs(lfa): update porting guide with LFA platform APIs
feat(

Merge changes from topic "mb/lfa-core-work" into integration

* changes:
docs(maintainers): add myself as code owner for LFA service
docs(lfa): update porting guide with LFA platform APIs
feat(lfa): add LFA holding pen logic
feat(lfa): add initial implementation for LFA_ACTIVATE
feat(lfa): add initial implementation for LFA_PRIME
feat(fvp): implement platform API for load and auth image
feat(lfa): implement LFA_CANCEL SMC
feat(fvp): implement platform API for LFA cancel operation
feat(lfa): implement LFA_GET_INVENTORY SMC
feat(fvp): implement platform API for LFA activation pending check
feat(lfa): implement LFA_GET_INFO SMC and integrate LFA build
feat(fvp): initialize LFA component activators in platform layer
feat(rmm): add placeholder activator callbacks for LFA
feat(bl31): add placeholder activator implementation for LFA
feat(lfa): add activation handler interface for component activation
feat(fvp): implement LFA get components API
feat(lfa): create LFA SMC handler template

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feat(fvp): implement LFA get components API

Introduce platform-specific implementation of
`plat_lfa_get_components()` for the Arm FVP platform. This function
returns LFA component metadata, includin

feat(fvp): implement LFA get components API

Introduce platform-specific implementation of
`plat_lfa_get_components()` for the Arm FVP platform. This function
returns LFA component metadata, including component ID, UUID for
each supported firmware image and number of components.

Change-Id: I9e7cbce5865becf3e4babcb770bc5eb3b69a0be8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5

Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5): probe components
feat(gicv5): initialise the IWB
feat(gicv5): initialise the IRS
feat(gicv5): assign interrupt sources to appropriate security states
feat(gicv5): add a barebones GICv5 driver
feat(gicv5): add support for building with gicv5

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docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
curren

docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
current limitations and known constraints.

Introduce build-time checks to ensure incompatible configurations
(e.g., with SPMD or RMMD) fail early with a clear error message.

Initial GICv5 support in FVP is intended to facilitate early Linux
kernel bring-up and to assist with upstream kernel patch development.

Note: This patch is a temporary measure and should be reverted once
proper and complete GICv5 support is upstreamed in TF-A.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2af839aec600040dfde75d74d02eff5a57ecda4e

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feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5

feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5 as the bindings are completely different.

This patch does not include a device tree. This will be added at a later
date.

Change-Id: Ifd0c7b4e0bc2ea1e53a6779ab4c50c4aec39dafb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes If4cd4e71,I0b5158ef into integration

* changes:
docs(fvp): add FVP_HW_CONFIG_ADDR documentation
feat(fvp): add FVP_HW_CONFIG_ADDR make variable

feat(fvp): add FVP_HW_CONFIG_ADDR make variable

Add a new variable that can be optionally set when calling `make`
to allow hw_config (such as DTB) to exist at a specified address.
Prior to this chan

feat(fvp): add FVP_HW_CONFIG_ADDR make variable

Add a new variable that can be optionally set when calling `make`
to allow hw_config (such as DTB) to exist at a specified address.
Prior to this change, the location was hardcoded to 0x82000000, which
could be overwritten if a preceeding image is large enough.
This new variable acts such that if it is unset, the behaviour
is exactly as before this patch, and if it is set, then the value
given is the hw-config's secondary-load-address value in the
fvp_fw_config DT.

Change-Id: I0b5158ef8c089b04078f2e9bb4408f03107591a5
Signed-off-by: emily.boarer@arm.com

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Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY
feat(cpufeat): add support for PMUv3p9

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Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refacto

Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refactor(gic): promote most of the GIC driver to common code
refactor: make arm_gicv2.c and arm_gicv3.c common
refactor(fvp): use more arm generic code for gicv3

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refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos(

refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos() no longer needs to be called
within the driver, helping with performance a bit.

Change-Id: I0b0d1d36d20d67c41c8c9dc14ade11bda6d4a6af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is

refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is difficult as their use is platform specific. So copy them to a
generic place and redirect platforms to them.

The new copies will remain for compatibility for platforms that don't
want to or can't take up upcoming refactors and the old copies can be
drastically refactored to make them more widely applicable.

Change-Id: I056c8710cdda4d8a81b324d392762c29e02cdae1
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(fvp): use more arm generic code for gicv3

The arm generic implementation for the GIC is quite comprehensive and
the fvp's requirements don't diverge too much. Despite that, they
completely

refactor(fvp): use more arm generic code for gicv3

The arm generic implementation for the GIC is quite comprehensive and
the fvp's requirements don't diverge too much. Despite that, they
completely override a lot of code that is effectively reused. Use the
generic implementation instead to make it easier to follow and override
as little code as possible.

Change-Id: I3474aa970d7fbb91d75c0be6a255bc0da734f860
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "sm/rpkm" into integration

* changes:
docs(rmmd): document the EL3-RMM IDE KM Interface
feat(trp): test el3-rmm ide km interface
feat(rmmd): el3-rmm ide key management

Merge changes from topic "sm/rpkm" into integration

* changes:
docs(rmmd): document the EL3-RMM IDE KM Interface
feat(trp): test el3-rmm ide km interface
feat(rmmd): el3-rmm ide key management interface

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feat(rmmd): el3-rmm ide key management interface

Patch introduces the EL3-RMM SMC Interface for Root Port
Key management as per RFC discussed here:
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM

feat(rmmd): el3-rmm ide key management interface

Patch introduces the EL3-RMM SMC Interface for Root Port
Key management as per RFC discussed here:
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface

Three IDE Key management smc calls have been added:
- RMM_IDE_KEY_PROG()
- RMM_IDE_KEY_SET_GO()
- RMM_IDE_KEY_SET_STOP()
- RMM_IDE_KM_PULL_RESPONSE()

Due to the absence of root port support in FVP, we are
currently adding placeholders in this patch for the platform
APIs to return success irrespective of the arguments being passed
by the caller(Realms). The SMCs are guarded by
`RMMD_ENABLE_IDE_KEY_PROG` build flag and is disabled by default.
We expect that once the SMCs are stabilized, this build flag will
not be required anymore.

Change-Id: I9411eb7787dac2a207bd14710d251503bd9626ce
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two pla

fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two places in the build system did not support this, instead were just
checking for a value of "1".

Fix the AArch32 check and build the FVP specific handler routine when
the value is not "0", instead of relying on it to be exactly "1".

Change-Id: I1acd3ed6d2a461d541b9bf57e4aac9c0798ab56b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "jc/tc_fw_handoff" into integration

* changes:
refactor(arm): simplify early platform setup function in BL31
refactor(arm): simplify early platform setup function in BL2

Merge changes from topic "jc/tc_fw_handoff" into integration

* changes:
refactor(arm): simplify early platform setup function in BL31
refactor(arm): simplify early platform setup function in BL2
feat(arm): add support for Transfer List creation

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feat(arm): add support for Transfer List creation

This patch introduces Firmware Handoff support for Arm based
platforms listed under Firmware_Handoff specification.
[https://firmwarehandoff.github.

feat(arm): add support for Transfer List creation

This patch introduces Firmware Handoff support for Arm based
platforms listed under Firmware_Handoff specification.
[https://firmwarehandoff.github.io/firmware_handoff/main/transfer_list.html]

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie3f30ffe38f809db907b663a8dbf1e48944ec690

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Merge "feat(rmmd): add FEAT_MEC support" into integration

feat(rmmd): add FEAT_MEC support

This patch provides architectural support for further use of
Memory Encryption Contexts (MEC) by declaring the necessary
registers, bits, masks, helpers and values a

feat(rmmd): add FEAT_MEC support

This patch provides architectural support for further use of
Memory Encryption Contexts (MEC) by declaring the necessary
registers, bits, masks, helpers and values and modifying the
necessary registers to enable FEAT_MEC.

Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I670dbfcef46e131dcbf3a0b927467ebf6f438fa4

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Merge changes I0396b597,I326f920f,I0437eec8,Ieadf01fc,I4e1d8c24, ... into integration

* changes:
feat(fvp): set defaults for build commandline
docs(arm): enable Linux boot from fip as BL33
fea

Merge changes I0396b597,I326f920f,I0437eec8,Ieadf01fc,I4e1d8c24, ... into integration

* changes:
feat(fvp): set defaults for build commandline
docs(arm): enable Linux boot from fip as BL33
feat(arm): enable Linux boot from fip as BL33
docs(fvp): update fvp build time options
docs(arm): add initrd props to dtb at build time
feat(arm): add initrd props to dtb at build time

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