fix(gpt): unify logging messages

This patch modifies GPT library comments and makes
logging messages consistent with PRIx64 usage and
TF-A format used in other modules.
Minor changes are made to mak

fix(gpt): unify logging messages

This patch modifies GPT library comments and makes
logging messages consistent with PRIx64 usage and
TF-A format used in other modules.
Minor changes are made to make the code compliant
with MISRA C requirements.

Change-Id: Ic40e1b7ac43cd9602819698d00e1ce3a8c7183ce
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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chore(gpt): remove gpt_ prefix

This patch removes 'gpt_' prefix from the
names of static functions for better code
readability.

Change-Id: I0398b55047a73209da598b708240fcba47c779f7
Signed-off-by: A

chore(gpt): remove gpt_ prefix

This patch removes 'gpt_' prefix from the
names of static functions for better code
readability.

Change-Id: I0398b55047a73209da598b708240fcba47c779f7
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only

Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2
fix(cm): hide `cm_init_context_by_index` from BL1
fix(bl1): add missing spinlock dependency

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feat(locks): add bitlock

This patch adds 'bitlock_t' type and bit_lock() and
bit_unlock() to support locking/release functionality
based on individual bit position. These functions use
atomic bit se

feat(locks): add bitlock

This patch adds 'bitlock_t' type and bit_lock() and
bit_unlock() to support locking/release functionality
based on individual bit position. These functions use
atomic bit set and clear instructions which require
FEAT_LSE mandatory from Armv8.1.

Change-Id: I3eb0f29bbccefe6c0f69061aa701187a6364df0c
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge "fix(handoff): correct representation of tag_id" into integration

fix(cm): remove ENABLE_FEAT_MTE usage

commit@c282384dbb45b6185b4aba14efebbad110d18e49
removed ENABLE_FEAT_MTE but missed its usage in
context structure declaration path.

All mte regs that are curre

fix(cm): remove ENABLE_FEAT_MTE usage

commit@c282384dbb45b6185b4aba14efebbad110d18e49
removed ENABLE_FEAT_MTE but missed its usage in
context structure declaration path.

All mte regs that are currently context saved/restored
are needed only when FEAT_MTE2 is enabled, so move to
usage of FEAT_MTE2 and remove FEAT_MTE usage

Change-Id: I6b4417485fa6b7f52a31045562600945e48e81b7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(cm): hide `cm_init_context_by_index` from BL1

BL1 requires the context management library but does not use or
implement `cm_init_context_by_index`. This change ensures that is not
compiled into

fix(cm): hide `cm_init_context_by_index` from BL1

BL1 requires the context management library but does not use or
implement `cm_init_context_by_index`. This change ensures that is not
compiled into BL1, as linking with LTO enabled causes an undefined
reference for this function.

Change-Id: I4a4602843bd75bc4f47b3e0c4c5a6efce1514ef6
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2728106

Cortex-A715 erratum 2728106 is a Cat B(rare) erratum that is present
in revision r0p0, r1p0 and r1p1. It is fixed in r1p2.

The workaround is to

fix(cpus): workaround for Cortex-A715 erratum 2728106

Cortex-A715 erratum 2728106 is a Cat B(rare) erratum that is present
in revision r0p0, r1p0 and r1p1. It is fixed in r1p2.

The workaround is to execute an implementation specific sequence in
the CPU.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Ic825f9942e7eb13893fdbb44a2090b897758cbc4
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge "fix(cc): code coverage optimization fix" into integration

Merge "fix(cm): add more system registers to EL1 context mgmt" into integration

fix(cc): code coverage optimization fix

Resolve issue where optimization is enabled for TF-A using
-Og and compile fail is seen in PSCI module.

Change-Id: Id9afb5c56a6937e7040b20cd01080c190c8276d5

fix(cc): code coverage optimization fix

Resolve issue where optimization is enabled for TF-A using
-Og and compile fail is seen in PSCI module.

Change-Id: Id9afb5c56a6937e7040b20cd01080c190c8276d5
Signed-off-by: Mark Dykes <mark.dykes@arm.com>

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Merge "build: use GCC to link by default" into integration

fix(cm): add more system registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:
MDCCINT_EL1
MDSCR_EL1
DISR_EL1
PIRE0_EL1

fix(cm): add more system registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:
MDCCINT_EL1
MDSCR_EL1
DISR_EL1
PIRE0_EL1
PIR_EL1
POR_EL1
S2POR_EL1
TCR2_EL1

Some of these registers are available as part of core Armv8-A
architecture while others are made available through various
architectural extensions.

Change-Id: I507dccb9053ba177e1b98100fceccd1f32bdfc5c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(handoff): correct representation of tag_id

The tag ID is a 3-byte field used to identify the contents of a TE. In
our library, the internal representation of the tag is a 2 byte field.
We curren

fix(handoff): correct representation of tag_id

The tag ID is a 3-byte field used to identify the contents of a TE. In
our library, the internal representation of the tag is a 2 byte field.
We currently ignore the top byte of this field, marking it res0. This
causes problems when dealing with non-standard TE types, whose range
starts at 0xff_f000. This commit fixes this by using a bit-field with a
24-bit width, and packing `transfer_list_entry`.

Change-Id: Ib3c212f964b64f528ad6f3dd6ab8b4597b877cd9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32

While comments introduced with the original commit claim that
pmuv3_disable_el3()/pmuv3_init_el3() are compatible with PMUv2 and
PMUv1, this

fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32

While comments introduced with the original commit claim that
pmuv3_disable_el3()/pmuv3_init_el3() are compatible with PMUv2 and
PMUv1, this is not true in practice: The function accesses the Secure
Debug Control Register (SDCR), which only available to ARMv8 CPUs.

ARMv8 CPUs executing in AArch32 mode would thus be able to disable
their PMUv3, while ARMv7 CPUs would hang trying to access the SDCR.

Fix this by only doing PMUv3 handling when we know a PMUv3 to be
available. This resolves boot hanging on all STM32MP15 platforms
that use SP_min as BL32 instead of OP-TEE.

Change-Id: I40f7611cf46b89a30243cc55bf55a8d9c9de93c8
Fixes: c73686a11cea ("feat(pmu): introduce pmuv3 lib/extensions folder")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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build: use GCC to link by default

When configuring GNU GCC as the C compiler, we usually use the GNU BFD
linker directly to link by default. However, this complicates things
because we also need to

build: use GCC to link by default

When configuring GNU GCC as the C compiler, we usually use the GNU BFD
linker directly to link by default. However, this complicates things
because we also need to support LTO, which can only be done when linking
is done via the C compiler, and we cannot change the linker later on if
some other part of the build system wants to enable LTO.

This change migrates the default choice of linker to GCC if the C
compiler is GCC, in order to enable this use-case. This should have no
impact on anything outside of the build system, as by default GCC merely
acts as a wrapper around BFD.

Change-Id: I40771be2b0571def67bbfde9e877e7629ec8cdaa
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(cm): save guarded control stack registers

This patch fixes a typo which led to incorrect context save
operations for two FEAT_GCS registers.

Change-Id: I3d3202a6721714bbc8f84c2d775d1b28afffa5df

fix(cm): save guarded control stack registers

This patch fixes a typo which led to incorrect context save
operations for two FEAT_GCS registers.

Change-Id: I3d3202a6721714bbc8f84c2d775d1b28afffa5df
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes from topic "mte_fixes" into integration

* changes:
build(changelog): move mte to mte2
refactor(mte): remove mte, mte_perm

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Sign

chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "fix(cpus): workaround for Cortex-A715 erratum 2413290" into integration

fix(cpus): workaround for Cortex-A715 erratum 2413290

Erratum 2413290 is a Cat B erratum that is present only
in revision r0p1 and is fixed in r1p1.

The initial implementation did not consider that

fix(cpus): workaround for Cortex-A715 erratum 2413290

Erratum 2413290 is a Cat B erratum that is present only
in revision r0p1 and is fixed in r1p1.

The initial implementation did not consider that this
fix is to be applied only when SPE (Statistical Profiling
Extension) is implemented and enabled. This patch applies
the fix by adding a check for ENABLE_SPE_FOR_NS.

Change-Id: I87b2175b89d6fb168c77e6ab233c90ca056791a1
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE

fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE (Statistical Profiling Extension) is implemented
and enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is "implemented and enabled".

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I30182c3893416af65b55fca9a913cb4512430434
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(mte): use ATA bit with FEAT_MTE2" into integration

Merge "refactor(cm): minor update on conditions used in prepare_el3_exit" into integration