1 /* 2 * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_features.h> 15 #include <arch_helpers.h> 16 #include <common/bl_common.h> 17 #include <context.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/extensions/amu.h> 20 #include <lib/extensions/pmuv3.h> 21 #include <lib/extensions/sys_reg_trace.h> 22 #include <lib/extensions/trf.h> 23 #include <lib/utils.h> 24 25 /******************************************************************************* 26 * Context management library initialisation routine. This library is used by 27 * runtime services to share pointers to 'cpu_context' structures for the secure 28 * and non-secure states. Management of the structures and their associated 29 * memory is not done by the context management library e.g. the PSCI service 30 * manages the cpu context used for entry from and exit to the non-secure state. 31 * The Secure payload manages the context(s) corresponding to the secure state. 32 * It also uses this library to get access to the non-secure 33 * state cpu context pointers. 34 ******************************************************************************/ 35 void cm_init(void) 36 { 37 /* 38 * The context management library has only global data to initialize, but 39 * that will be done when the BSS is zeroed out 40 */ 41 } 42 43 /******************************************************************************* 44 * The following function initializes the cpu_context 'ctx' for 45 * first use, and sets the initial entrypoint state as specified by the 46 * entry_point_info structure. 47 * 48 * The security state to initialize is determined by the SECURE attribute 49 * of the entry_point_info. 50 * 51 * The EE and ST attributes are used to configure the endianness and secure 52 * timer availability for the new execution context. 53 * 54 * To prepare the register state for entry call cm_prepare_el3_exit() and 55 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 56 * cm_el1_sysregs_context_restore(). 57 ******************************************************************************/ 58 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 59 { 60 unsigned int security_state; 61 uint32_t scr, sctlr; 62 regs_t *reg_ctx; 63 64 assert(ctx != NULL); 65 66 security_state = GET_SECURITY_STATE(ep->h.attr); 67 68 /* Clear any residual register values from the context */ 69 zeromem(ctx, sizeof(*ctx)); 70 71 reg_ctx = get_regs_ctx(ctx); 72 73 /* 74 * Base the context SCR on the current value, adjust for entry point 75 * specific requirements 76 */ 77 scr = read_scr(); 78 scr &= ~(SCR_NS_BIT | SCR_HCE_BIT); 79 80 if (security_state != SECURE) 81 scr |= SCR_NS_BIT; 82 83 if (security_state != SECURE) { 84 /* 85 * Set up SCTLR for the Non-secure context. 86 * 87 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 88 * 89 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 90 * required by PSCI specification) 91 * 92 * Set remaining SCTLR fields to their architecturally defined 93 * values. Some fields reset to an IMPLEMENTATION DEFINED value: 94 * 95 * SCTLR.TE: Set to zero so that exceptions to an Exception 96 * Level executing at PL1 are taken to A32 state. 97 * 98 * SCTLR.V: Set to zero to select the normal exception vectors 99 * with base address held in VBAR. 100 */ 101 assert(((ep->spsr >> SPSR_E_SHIFT) & SPSR_E_MASK) == 102 (EP_GET_EE(ep->h.attr) >> EP_EE_SHIFT)); 103 104 sctlr = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 105 sctlr |= (SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_V_BIT)); 106 write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr); 107 } 108 109 /* 110 * The target exception level is based on the spsr mode requested. If 111 * execution is requested to hyp mode, HVC is enabled via SCR.HCE. 112 */ 113 if (GET_M32(ep->spsr) == MODE32_hyp) 114 scr |= SCR_HCE_BIT; 115 116 /* 117 * Store the initialised values for SCTLR and SCR in the cpu_context. 118 * The Hyp mode registers are not part of the saved context and are 119 * set-up in cm_prepare_el3_exit(). 120 */ 121 write_ctx_reg(reg_ctx, CTX_SCR, scr); 122 write_ctx_reg(reg_ctx, CTX_LR, ep->pc); 123 write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr); 124 125 /* 126 * Store the r0-r3 value from the entrypoint into the context 127 * Use memcpy as we are in control of the layout of the structures 128 */ 129 memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t)); 130 } 131 132 /******************************************************************************* 133 * Enable architecture extensions on first entry to Non-secure world. 134 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 135 * it is zero. 136 ******************************************************************************/ 137 static void enable_extensions_nonsecure(bool el2_unused) 138 { 139 #if IMAGE_BL32 140 if (is_feat_amu_supported()) { 141 amu_enable(el2_unused); 142 } 143 144 if (is_feat_sys_reg_trace_supported()) { 145 sys_reg_trace_init_el3(); 146 } 147 148 if (is_feat_trf_supported()) { 149 trf_init_el3(); 150 } 151 152 if (read_feat_pmuv3_id_field() >= 3U) { 153 pmuv3_init_el3(); 154 } 155 #endif /* IMAGE_BL32 */ 156 } 157 158 /******************************************************************************* 159 * The following function initializes the cpu_context for a CPU specified by 160 * its `cpu_idx` for first use, and sets the initial entrypoint state as 161 * specified by the entry_point_info structure. 162 ******************************************************************************/ 163 void cm_init_context_by_index(unsigned int cpu_idx, 164 const entry_point_info_t *ep) 165 { 166 cpu_context_t *ctx; 167 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 168 cm_setup_context(ctx, ep); 169 } 170 171 /******************************************************************************* 172 * The following function initializes the cpu_context for the current CPU 173 * for first use, and sets the initial entrypoint state as specified by the 174 * entry_point_info structure. 175 ******************************************************************************/ 176 void cm_init_my_context(const entry_point_info_t *ep) 177 { 178 cpu_context_t *ctx; 179 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 180 cm_setup_context(ctx, ep); 181 } 182 183 /******************************************************************************* 184 * Prepare the CPU system registers for first entry into secure or normal world 185 * 186 * If execution is requested to hyp mode, HSCTLR is initialized 187 * If execution is requested to non-secure PL1, and the CPU supports 188 * HYP mode then HYP mode is disabled by configuring all necessary HYP mode 189 * registers. 190 ******************************************************************************/ 191 void cm_prepare_el3_exit(uint32_t security_state) 192 { 193 uint32_t hsctlr, scr; 194 cpu_context_t *ctx = cm_get_context(security_state); 195 bool el2_unused = false; 196 197 assert(ctx != NULL); 198 199 if (security_state == NON_SECURE) { 200 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); 201 if ((scr & SCR_HCE_BIT) != 0U) { 202 /* Use SCTLR value to initialize HSCTLR */ 203 hsctlr = read_ctx_reg(get_regs_ctx(ctx), 204 CTX_NS_SCTLR); 205 hsctlr |= HSCTLR_RES1; 206 /* Temporarily set the NS bit to access HSCTLR */ 207 write_scr(read_scr() | SCR_NS_BIT); 208 /* 209 * Make sure the write to SCR is complete so that 210 * we can access HSCTLR 211 */ 212 isb(); 213 write_hsctlr(hsctlr); 214 isb(); 215 216 write_scr(read_scr() & ~SCR_NS_BIT); 217 isb(); 218 } else if ((read_id_pfr1() & 219 (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) != 0U) { 220 el2_unused = true; 221 222 /* 223 * Set the NS bit to access NS copies of certain banked 224 * registers 225 */ 226 write_scr(read_scr() | SCR_NS_BIT); 227 isb(); 228 229 /* 230 * Hyp / PL2 present but unused, need to disable safely. 231 * HSCTLR can be ignored in this case. 232 * 233 * Set HCR to its architectural reset value so that 234 * Non-secure operations do not trap to Hyp mode. 235 */ 236 write_hcr(HCR_RESET_VAL); 237 238 /* 239 * Set HCPTR to its architectural reset value so that 240 * Non-secure access from EL1 or EL0 to trace and to 241 * Advanced SIMD and floating point functionality does 242 * not trap to Hyp mode. 243 */ 244 write_hcptr(HCPTR_RESET_VAL); 245 246 /* 247 * Initialise CNTHCTL. All fields are architecturally 248 * UNKNOWN on reset and are set to zero except for 249 * field(s) listed below. 250 * 251 * CNTHCTL.PL1PCEN: Disable traps to Hyp mode of 252 * Non-secure EL0 and EL1 accessed to the physical 253 * timer registers. 254 * 255 * CNTHCTL.PL1PCTEN: Disable traps to Hyp mode of 256 * Non-secure EL0 and EL1 accessed to the physical 257 * counter registers. 258 */ 259 write_cnthctl(CNTHCTL_RESET_VAL | 260 PL1PCEN_BIT | PL1PCTEN_BIT); 261 262 /* 263 * Initialise CNTVOFF to zero as it resets to an 264 * IMPLEMENTATION DEFINED value. 265 */ 266 write64_cntvoff(0); 267 268 /* 269 * Set VPIDR and VMPIDR to match MIDR_EL1 and MPIDR 270 * respectively. 271 */ 272 write_vpidr(read_midr()); 273 write_vmpidr(read_mpidr()); 274 275 /* 276 * Initialise VTTBR, setting all fields rather than 277 * relying on the hw. Some fields are architecturally 278 * UNKNOWN at reset. 279 * 280 * VTTBR.VMID: Set to zero which is the architecturally 281 * defined reset value. Even though EL1&0 stage 2 282 * address translation is disabled, cache maintenance 283 * operations depend on the VMID. 284 * 285 * VTTBR.BADDR: Set to zero as EL1&0 stage 2 address 286 * translation is disabled. 287 */ 288 write64_vttbr(VTTBR_RESET_VAL & 289 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 290 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 291 292 /* 293 * Initialise HDCR, setting all the fields rather than 294 * relying on hw. 295 * 296 * HDCR.HPMN: Set to value of PMCR.N which is the 297 * architecturally-defined reset value. 298 * 299 * HDCR.HLP: Set to one so that event counter 300 * overflow, that is recorded in PMOVSCLR[0-30], 301 * occurs on the increment that changes 302 * PMEVCNTR<n>[63] from 1 to 0, when ARMv8.5-PMU is 303 * implemented. This bit is RES0 in versions of the 304 * architecture earlier than ARMv8.5, setting it to 1 305 * doesn't have any effect on them. 306 * This bit is Reserved, UNK/SBZP in ARMv7. 307 * 308 * HDCR.HPME: Set to zero to disable EL2 Event 309 * counters. 310 */ 311 #if (ARM_ARCH_MAJOR > 7) 312 write_hdcr((HDCR_RESET_VAL | HDCR_HLP_BIT | 313 ((read_pmcr() & PMCR_N_BITS) >> 314 PMCR_N_SHIFT)) & ~HDCR_HPME_BIT); 315 #else 316 write_hdcr((HDCR_RESET_VAL | 317 ((read_pmcr() & PMCR_N_BITS) >> 318 PMCR_N_SHIFT)) & ~HDCR_HPME_BIT); 319 #endif 320 /* 321 * Set HSTR to its architectural reset value so that 322 * access to system registers in the cproc=1111 323 * encoding space do not trap to Hyp mode. 324 */ 325 write_hstr(HSTR_RESET_VAL); 326 /* 327 * Set CNTHP_CTL to its architectural reset value to 328 * disable the EL2 physical timer and prevent timer 329 * interrupts. Some fields are architecturally UNKNOWN 330 * on reset and are set to zero. 331 */ 332 write_cnthp_ctl(CNTHP_CTL_RESET_VAL); 333 isb(); 334 335 write_scr(read_scr() & ~SCR_NS_BIT); 336 isb(); 337 } 338 enable_extensions_nonsecure(el2_unused); 339 } 340 } 341 342 /******************************************************************************* 343 * This function is used to exit to Non-secure world. It simply calls the 344 * cm_prepare_el3_exit function for AArch32. 345 ******************************************************************************/ 346 void cm_prepare_el3_exit_ns(void) 347 { 348 cm_prepare_el3_exit(NON_SECURE); 349 } 350