1 /* 2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <arch_helpers.h> 14 #include <arch/aarch64/arch_features.h> 15 #include <bl31/bl31.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/debug.h> 18 #include <common/runtime_svc.h> 19 #include <common/tbbr/tbbr_img_def.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/fconf/fconf.h> 22 #include <lib/fconf/fconf_dyn_cfg_getter.h> 23 #include <lib/smccc.h> 24 #include <lib/spinlock.h> 25 #include <lib/utils.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/common_def.h> 28 #include <plat/common/platform.h> 29 #include <platform_def.h> 30 #include <services/el3_spmd_logical_sp.h> 31 #include <services/ffa_svc.h> 32 #include <services/spmc_svc.h> 33 #include <services/spmd_svc.h> 34 #include <smccc_helpers.h> 35 #include "spmd_private.h" 36 37 /******************************************************************************* 38 * SPM Core context information. 39 ******************************************************************************/ 40 static spmd_spm_core_context_t spm_core_context[PLATFORM_CORE_COUNT]; 41 42 /******************************************************************************* 43 * SPM Core attribute information is read from its manifest if the SPMC is not 44 * at EL3. Else, it is populated from the SPMC directly. 45 ******************************************************************************/ 46 static spmc_manifest_attribute_t spmc_attrs; 47 48 /******************************************************************************* 49 * SPM Core entry point information. Discovered on the primary core and reused 50 * on secondary cores. 51 ******************************************************************************/ 52 static entry_point_info_t *spmc_ep_info; 53 54 /******************************************************************************* 55 * SPM Core context on CPU based on mpidr. 56 ******************************************************************************/ 57 spmd_spm_core_context_t *spmd_get_context_by_mpidr(uint64_t mpidr) 58 { 59 int core_idx = plat_core_pos_by_mpidr(mpidr); 60 61 if (core_idx < 0) { 62 ERROR("Invalid mpidr: %" PRIx64 ", returned ID: %d\n", mpidr, core_idx); 63 panic(); 64 } 65 66 return &spm_core_context[core_idx]; 67 } 68 69 /******************************************************************************* 70 * SPM Core context on current CPU get helper. 71 ******************************************************************************/ 72 spmd_spm_core_context_t *spmd_get_context(void) 73 { 74 return spmd_get_context_by_mpidr(read_mpidr()); 75 } 76 77 /******************************************************************************* 78 * SPM Core ID getter. 79 ******************************************************************************/ 80 uint16_t spmd_spmc_id_get(void) 81 { 82 return spmc_attrs.spmc_id; 83 } 84 85 /******************************************************************************* 86 * Static function declaration. 87 ******************************************************************************/ 88 static int32_t spmd_init(void); 89 static int spmd_spmc_init(void *pm_addr); 90 91 static uint64_t spmd_smc_forward(uint32_t smc_fid, 92 bool secure_origin, 93 uint64_t x1, 94 uint64_t x2, 95 uint64_t x3, 96 uint64_t x4, 97 void *cookie, 98 void *handle, 99 uint64_t flags); 100 101 /****************************************************************************** 102 * Builds an SPMD to SPMC direct message request. 103 *****************************************************************************/ 104 void spmd_build_spmc_message(gp_regs_t *gpregs, uint8_t target_func, 105 unsigned long long message) 106 { 107 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); 108 write_ctx_reg(gpregs, CTX_GPREG_X1, 109 (SPMD_DIRECT_MSG_ENDPOINT_ID << FFA_DIRECT_MSG_SOURCE_SHIFT) | 110 spmd_spmc_id_get()); 111 write_ctx_reg(gpregs, CTX_GPREG_X2, BIT(31) | target_func); 112 write_ctx_reg(gpregs, CTX_GPREG_X3, message); 113 114 /* Zero out x4-x7 for the direct request emitted towards the SPMC. */ 115 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); 116 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 117 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 118 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 119 } 120 121 122 /******************************************************************************* 123 * This function takes an SPMC context pointer and performs a synchronous 124 * SPMC entry. 125 ******************************************************************************/ 126 uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *spmc_ctx) 127 { 128 uint64_t rc; 129 130 assert(spmc_ctx != NULL); 131 132 cm_set_context(&(spmc_ctx->cpu_ctx), SECURE); 133 134 /* Restore the context assigned above */ 135 #if SPMD_SPM_AT_SEL2 136 cm_el2_sysregs_context_restore(SECURE); 137 #else 138 cm_el1_sysregs_context_restore(SECURE); 139 #endif 140 cm_set_next_eret_context(SECURE); 141 142 /* Enter SPMC */ 143 rc = spmd_spm_core_enter(&spmc_ctx->c_rt_ctx); 144 145 /* Save secure state */ 146 #if SPMD_SPM_AT_SEL2 147 cm_el2_sysregs_context_save(SECURE); 148 #else 149 cm_el1_sysregs_context_save(SECURE); 150 #endif 151 152 return rc; 153 } 154 155 /******************************************************************************* 156 * This function returns to the place where spmd_spm_core_sync_entry() was 157 * called originally. 158 ******************************************************************************/ 159 __dead2 void spmd_spm_core_sync_exit(uint64_t rc) 160 { 161 spmd_spm_core_context_t *ctx = spmd_get_context(); 162 163 /* Get current CPU context from SPMC context */ 164 assert(cm_get_context(SECURE) == &(ctx->cpu_ctx)); 165 166 /* 167 * The SPMD must have initiated the original request through a 168 * synchronous entry into SPMC. Jump back to the original C runtime 169 * context with the value of rc in x0; 170 */ 171 spmd_spm_core_exit(ctx->c_rt_ctx, rc); 172 173 panic(); 174 } 175 176 /******************************************************************************* 177 * Jump to the SPM Core for the first time. 178 ******************************************************************************/ 179 static int32_t spmd_init(void) 180 { 181 spmd_spm_core_context_t *ctx = spmd_get_context(); 182 uint64_t rc; 183 184 VERBOSE("SPM Core init start.\n"); 185 186 /* Primary boot core enters the SPMC for initialization. */ 187 ctx->state = SPMC_STATE_ON_PENDING; 188 189 rc = spmd_spm_core_sync_entry(ctx); 190 if (rc != 0ULL) { 191 ERROR("SPMC initialisation failed 0x%" PRIx64 "\n", rc); 192 return 0; 193 } 194 195 ctx->state = SPMC_STATE_ON; 196 197 VERBOSE("SPM Core init end.\n"); 198 199 spmd_logical_sp_set_spmc_initialized(); 200 rc = spmd_logical_sp_init(); 201 if (rc != 0) { 202 WARN("SPMD Logical partitions failed init.\n"); 203 } 204 205 return 1; 206 } 207 208 /******************************************************************************* 209 * spmd_secure_interrupt_handler 210 * Enter the SPMC for further handling of the secure interrupt by the SPMC 211 * itself or a Secure Partition. 212 ******************************************************************************/ 213 static uint64_t spmd_secure_interrupt_handler(uint32_t id, 214 uint32_t flags, 215 void *handle, 216 void *cookie) 217 { 218 spmd_spm_core_context_t *ctx = spmd_get_context(); 219 gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx); 220 unsigned int linear_id = plat_my_core_pos(); 221 int64_t rc; 222 223 /* Sanity check the security state when the exception was generated */ 224 assert(get_interrupt_src_ss(flags) == NON_SECURE); 225 226 /* Sanity check the pointer to this cpu's context */ 227 assert(handle == cm_get_context(NON_SECURE)); 228 229 /* Save the non-secure context before entering SPMC */ 230 cm_el1_sysregs_context_save(NON_SECURE); 231 #if SPMD_SPM_AT_SEL2 232 cm_el2_sysregs_context_save(NON_SECURE); 233 #endif 234 235 /* Convey the event to the SPMC through the FFA_INTERRUPT interface. */ 236 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_INTERRUPT); 237 write_ctx_reg(gpregs, CTX_GPREG_X1, 0); 238 write_ctx_reg(gpregs, CTX_GPREG_X2, 0); 239 write_ctx_reg(gpregs, CTX_GPREG_X3, 0); 240 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); 241 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 242 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 243 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 244 245 /* Mark current core as handling a secure interrupt. */ 246 ctx->secure_interrupt_ongoing = true; 247 248 rc = spmd_spm_core_sync_entry(ctx); 249 if (rc != 0ULL) { 250 ERROR("%s failed (%" PRId64 ") on CPU%u\n", __func__, rc, linear_id); 251 } 252 253 ctx->secure_interrupt_ongoing = false; 254 255 cm_el1_sysregs_context_restore(NON_SECURE); 256 #if SPMD_SPM_AT_SEL2 257 cm_el2_sysregs_context_restore(NON_SECURE); 258 #endif 259 cm_set_next_eret_context(NON_SECURE); 260 261 SMC_RET0(&ctx->cpu_ctx); 262 } 263 264 #if (EL3_EXCEPTION_HANDLING == 0) 265 /******************************************************************************* 266 * spmd_group0_interrupt_handler_nwd 267 * Group0 secure interrupt in the normal world are trapped to EL3. Delegate the 268 * handling of the interrupt to the platform handler, and return only upon 269 * successfully handling the Group0 interrupt. 270 ******************************************************************************/ 271 static uint64_t spmd_group0_interrupt_handler_nwd(uint32_t id, 272 uint32_t flags, 273 void *handle, 274 void *cookie) 275 { 276 uint32_t intid; 277 278 /* Sanity check the security state when the exception was generated. */ 279 assert(get_interrupt_src_ss(flags) == NON_SECURE); 280 281 /* Sanity check the pointer to this cpu's context. */ 282 assert(handle == cm_get_context(NON_SECURE)); 283 284 assert(id == INTR_ID_UNAVAILABLE); 285 286 assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3); 287 288 intid = plat_ic_acknowledge_interrupt(); 289 290 if (plat_spmd_handle_group0_interrupt(intid) < 0) { 291 ERROR("Group0 interrupt %u not handled\n", intid); 292 panic(); 293 } 294 295 /* Deactivate the corresponding Group0 interrupt. */ 296 plat_ic_end_of_interrupt(intid); 297 298 return 0U; 299 } 300 #endif 301 302 /******************************************************************************* 303 * spmd_handle_group0_intr_swd 304 * SPMC delegates handling of Group0 secure interrupt to EL3 firmware using 305 * FFA_EL3_INTR_HANDLE SMC call. Further, SPMD delegates the handling of the 306 * interrupt to the platform handler, and returns only upon successfully 307 * handling the Group0 interrupt. 308 ******************************************************************************/ 309 static uint64_t spmd_handle_group0_intr_swd(void *handle) 310 { 311 uint32_t intid; 312 313 /* Sanity check the pointer to this cpu's context */ 314 assert(handle == cm_get_context(SECURE)); 315 316 assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3); 317 318 intid = plat_ic_acknowledge_interrupt(); 319 320 /* 321 * TODO: Currently due to a limitation in SPMD implementation, the 322 * platform handler is expected to not delegate handling to NWd while 323 * processing Group0 secure interrupt. 324 */ 325 if (plat_spmd_handle_group0_interrupt(intid) < 0) { 326 /* Group0 interrupt was not handled by the platform. */ 327 ERROR("Group0 interrupt %u not handled\n", intid); 328 panic(); 329 } 330 331 /* Deactivate the corresponding Group0 interrupt. */ 332 plat_ic_end_of_interrupt(intid); 333 334 /* Return success. */ 335 SMC_RET8(handle, FFA_SUCCESS_SMC32, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 336 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 337 FFA_PARAM_MBZ); 338 } 339 340 #if ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 341 static int spmd_dynamic_map_mem(uintptr_t base_addr, size_t size, 342 unsigned int attr, uintptr_t *align_addr, 343 size_t *align_size) 344 { 345 uintptr_t base_addr_align; 346 size_t mapped_size_align; 347 int rc; 348 349 /* Page aligned address and size if necessary */ 350 base_addr_align = page_align(base_addr, DOWN); 351 mapped_size_align = page_align(size, UP); 352 353 if ((base_addr != base_addr_align) && 354 (size == mapped_size_align)) { 355 mapped_size_align += PAGE_SIZE; 356 } 357 358 /* 359 * Map dynamically given region with its aligned base address and 360 * size 361 */ 362 rc = mmap_add_dynamic_region((unsigned long long)base_addr_align, 363 base_addr_align, 364 mapped_size_align, 365 attr); 366 if (rc == 0) { 367 *align_addr = base_addr_align; 368 *align_size = mapped_size_align; 369 } 370 371 return rc; 372 } 373 374 static void spmd_do_sec_cpy(uintptr_t root_base_addr, uintptr_t sec_base_addr, 375 size_t size) 376 { 377 uintptr_t root_base_addr_align, sec_base_addr_align; 378 size_t root_mapped_size_align, sec_mapped_size_align; 379 int rc; 380 381 assert(root_base_addr != 0UL); 382 assert(sec_base_addr != 0UL); 383 assert(size != 0UL); 384 385 /* Map the memory with required attributes */ 386 rc = spmd_dynamic_map_mem(root_base_addr, size, MT_RO_DATA | MT_ROOT, 387 &root_base_addr_align, 388 &root_mapped_size_align); 389 if (rc != 0) { 390 ERROR("%s %s %lu (%d)\n", "Error while mapping", "root region", 391 root_base_addr, rc); 392 panic(); 393 } 394 395 rc = spmd_dynamic_map_mem(sec_base_addr, size, MT_RW_DATA | MT_SECURE, 396 &sec_base_addr_align, &sec_mapped_size_align); 397 if (rc != 0) { 398 ERROR("%s %s %lu (%d)\n", "Error while mapping", 399 "secure region", sec_base_addr, rc); 400 panic(); 401 } 402 403 /* Do copy operation */ 404 (void)memcpy((void *)sec_base_addr, (void *)root_base_addr, size); 405 406 /* Unmap root memory region */ 407 rc = mmap_remove_dynamic_region(root_base_addr_align, 408 root_mapped_size_align); 409 if (rc != 0) { 410 ERROR("%s %s %lu (%d)\n", "Error while unmapping", 411 "root region", root_base_addr_align, rc); 412 panic(); 413 } 414 415 /* Unmap secure memory region */ 416 rc = mmap_remove_dynamic_region(sec_base_addr_align, 417 sec_mapped_size_align); 418 if (rc != 0) { 419 ERROR("%s %s %lu (%d)\n", "Error while unmapping", 420 "secure region", sec_base_addr_align, rc); 421 panic(); 422 } 423 } 424 #endif /* ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */ 425 426 /******************************************************************************* 427 * Loads SPMC manifest and inits SPMC. 428 ******************************************************************************/ 429 static int spmd_spmc_init(void *pm_addr) 430 { 431 cpu_context_t *cpu_ctx; 432 unsigned int core_id; 433 uint32_t ep_attr, flags; 434 int rc; 435 const struct dyn_cfg_dtb_info_t *image_info __unused; 436 437 /* Load the SPM Core manifest */ 438 rc = plat_spm_core_manifest_load(&spmc_attrs, pm_addr); 439 if (rc != 0) { 440 WARN("No or invalid SPM Core manifest image provided by BL2\n"); 441 return rc; 442 } 443 444 /* 445 * Ensure that the SPM Core version is compatible with the SPM 446 * Dispatcher version. 447 */ 448 if ((spmc_attrs.major_version != FFA_VERSION_MAJOR) || 449 (spmc_attrs.minor_version > FFA_VERSION_MINOR)) { 450 WARN("Unsupported FFA version (%u.%u)\n", 451 spmc_attrs.major_version, spmc_attrs.minor_version); 452 return -EINVAL; 453 } 454 455 VERBOSE("FFA version (%u.%u)\n", spmc_attrs.major_version, 456 spmc_attrs.minor_version); 457 458 VERBOSE("SPM Core run time EL%x.\n", 459 SPMD_SPM_AT_SEL2 ? MODE_EL2 : MODE_EL1); 460 461 /* Validate the SPMC ID, Ensure high bit is set */ 462 if (((spmc_attrs.spmc_id >> SPMC_SECURE_ID_SHIFT) & 463 SPMC_SECURE_ID_MASK) == 0U) { 464 WARN("Invalid ID (0x%x) for SPMC.\n", spmc_attrs.spmc_id); 465 return -EINVAL; 466 } 467 468 /* Validate the SPM Core execution state */ 469 if ((spmc_attrs.exec_state != MODE_RW_64) && 470 (spmc_attrs.exec_state != MODE_RW_32)) { 471 WARN("Unsupported %s%x.\n", "SPM Core execution state 0x", 472 spmc_attrs.exec_state); 473 return -EINVAL; 474 } 475 476 VERBOSE("%s%x.\n", "SPM Core execution state 0x", 477 spmc_attrs.exec_state); 478 479 #if SPMD_SPM_AT_SEL2 480 /* Ensure manifest has not requested AArch32 state in S-EL2 */ 481 if (spmc_attrs.exec_state == MODE_RW_32) { 482 WARN("AArch32 state at S-EL2 is not supported.\n"); 483 return -EINVAL; 484 } 485 486 /* 487 * Check if S-EL2 is supported on this system if S-EL2 488 * is required for SPM 489 */ 490 if (!is_feat_sel2_supported()) { 491 WARN("SPM Core run time S-EL2 is not supported.\n"); 492 return -EINVAL; 493 } 494 #endif /* SPMD_SPM_AT_SEL2 */ 495 496 /* Initialise an entrypoint to set up the CPU context */ 497 ep_attr = SECURE | EP_ST_ENABLE; 498 if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0ULL) { 499 ep_attr |= EP_EE_BIG; 500 } 501 502 SET_PARAM_HEAD(spmc_ep_info, PARAM_EP, VERSION_1, ep_attr); 503 504 /* 505 * Populate SPSR for SPM Core based upon validated parameters from the 506 * manifest. 507 */ 508 if (spmc_attrs.exec_state == MODE_RW_32) { 509 spmc_ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 510 SPSR_E_LITTLE, 511 DAIF_FIQ_BIT | 512 DAIF_IRQ_BIT | 513 DAIF_ABT_BIT); 514 } else { 515 516 #if SPMD_SPM_AT_SEL2 517 static const uint32_t runtime_el = MODE_EL2; 518 #else 519 static const uint32_t runtime_el = MODE_EL1; 520 #endif 521 spmc_ep_info->spsr = SPSR_64(runtime_el, 522 MODE_SP_ELX, 523 DISABLE_ALL_EXCEPTIONS); 524 } 525 526 #if ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 527 image_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TOS_FW_CONFIG_ID); 528 assert(image_info != NULL); 529 530 if ((image_info->config_addr == 0UL) || 531 (image_info->secondary_config_addr == 0UL) || 532 (image_info->config_max_size == 0UL)) { 533 return -EINVAL; 534 } 535 536 /* Copy manifest from root->secure region */ 537 spmd_do_sec_cpy(image_info->config_addr, 538 image_info->secondary_config_addr, 539 image_info->config_max_size); 540 541 /* Update ep info of BL32 */ 542 assert(spmc_ep_info != NULL); 543 spmc_ep_info->args.arg0 = image_info->secondary_config_addr; 544 #endif /* ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */ 545 546 /* Set an initial SPMC context state for all cores. */ 547 for (core_id = 0U; core_id < PLATFORM_CORE_COUNT; core_id++) { 548 spm_core_context[core_id].state = SPMC_STATE_OFF; 549 550 /* Setup an initial cpu context for the SPMC. */ 551 cpu_ctx = &spm_core_context[core_id].cpu_ctx; 552 cm_setup_context(cpu_ctx, spmc_ep_info); 553 554 /* 555 * Pass the core linear ID to the SPMC through x4. 556 * (TF-A implementation defined behavior helping 557 * a legacy TOS migration to adopt FF-A). 558 */ 559 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4, core_id); 560 } 561 562 /* Register power management hooks with PSCI */ 563 psci_register_spd_pm_hook(&spmd_pm); 564 565 /* Register init function for deferred init. */ 566 bl31_register_bl32_init(&spmd_init); 567 568 INFO("SPM Core setup done.\n"); 569 570 /* 571 * Register an interrupt handler routing secure interrupts to SPMD 572 * while the NWd is running. 573 */ 574 flags = 0; 575 set_interrupt_rm_flag(flags, NON_SECURE); 576 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 577 spmd_secure_interrupt_handler, 578 flags); 579 if (rc != 0) { 580 panic(); 581 } 582 583 /* 584 * Permit configurations where the SPM resides at S-EL1/2 and upon a 585 * Group0 interrupt triggering while the normal world runs, the 586 * interrupt is routed either through the EHF or directly to the SPMD: 587 * 588 * EL3_EXCEPTION_HANDLING=0: the Group0 interrupt is routed to the SPMD 589 * for handling by spmd_group0_interrupt_handler_nwd. 590 * 591 * EL3_EXCEPTION_HANDLING=1: the Group0 interrupt is routed to the EHF. 592 * 593 */ 594 #if (EL3_EXCEPTION_HANDLING == 0) 595 /* 596 * If EL3 interrupts are supported by the platform, register an 597 * interrupt handler routing Group0 interrupts to SPMD while the NWd is 598 * running. 599 */ 600 if (plat_ic_has_interrupt_type(INTR_TYPE_EL3)) { 601 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 602 spmd_group0_interrupt_handler_nwd, 603 flags); 604 if (rc != 0) { 605 panic(); 606 } 607 } 608 #endif 609 610 return 0; 611 } 612 613 /******************************************************************************* 614 * Initialize context of SPM Core. 615 ******************************************************************************/ 616 int spmd_setup(void) 617 { 618 int rc; 619 void *spmc_manifest; 620 621 /* 622 * If the SPMC is at EL3, then just initialise it directly. The 623 * shenanigans of when it is at a lower EL are not needed. 624 */ 625 if (is_spmc_at_el3()) { 626 /* Allow the SPMC to populate its attributes directly. */ 627 spmc_populate_attrs(&spmc_attrs); 628 629 rc = spmc_setup(); 630 if (rc != 0) { 631 WARN("SPMC initialisation failed 0x%x.\n", rc); 632 } 633 return 0; 634 } 635 636 spmc_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 637 if (spmc_ep_info == NULL) { 638 WARN("No SPM Core image provided by BL2 boot loader.\n"); 639 return 0; 640 } 641 642 /* Under no circumstances will this parameter be 0 */ 643 assert(spmc_ep_info->pc != 0ULL); 644 645 /* 646 * Check if BL32 ep_info has a reference to 'tos_fw_config'. This will 647 * be used as a manifest for the SPM Core at the next lower EL/mode. 648 */ 649 spmc_manifest = (void *)spmc_ep_info->args.arg0; 650 if (spmc_manifest == NULL) { 651 WARN("Invalid or absent SPM Core manifest.\n"); 652 return 0; 653 } 654 655 /* Load manifest, init SPMC */ 656 rc = spmd_spmc_init(spmc_manifest); 657 if (rc != 0) { 658 WARN("Booting device without SPM initialization.\n"); 659 } 660 661 return 0; 662 } 663 664 /******************************************************************************* 665 * Forward FF-A SMCs to the other security state. 666 ******************************************************************************/ 667 uint64_t spmd_smc_switch_state(uint32_t smc_fid, 668 bool secure_origin, 669 uint64_t x1, 670 uint64_t x2, 671 uint64_t x3, 672 uint64_t x4, 673 void *handle, 674 uint64_t flags) 675 { 676 unsigned int secure_state_in = (secure_origin) ? SECURE : NON_SECURE; 677 unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE; 678 679 #if SPMD_SPM_AT_SEL2 680 if ((secure_state_out == SECURE) && (is_sve_hint_set(flags) == true)) { 681 /* 682 * Set the SVE hint bit in x0 and pass to the lower secure EL, 683 * if it was set by the caller. 684 */ 685 smc_fid |= (FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT); 686 } 687 #endif 688 689 /* Save incoming security state */ 690 #if SPMD_SPM_AT_SEL2 691 if (secure_state_in == NON_SECURE) { 692 cm_el1_sysregs_context_save(secure_state_in); 693 } 694 cm_el2_sysregs_context_save(secure_state_in); 695 #else 696 cm_el1_sysregs_context_save(secure_state_in); 697 #endif 698 699 /* Restore outgoing security state */ 700 #if SPMD_SPM_AT_SEL2 701 if (secure_state_out == NON_SECURE) { 702 cm_el1_sysregs_context_restore(secure_state_out); 703 } 704 cm_el2_sysregs_context_restore(secure_state_out); 705 #else 706 cm_el1_sysregs_context_restore(secure_state_out); 707 #endif 708 cm_set_next_eret_context(secure_state_out); 709 710 #if SPMD_SPM_AT_SEL2 711 /* 712 * If SPMC is at SEL2, save additional registers x8-x17, which may 713 * be used in FF-A calls such as FFA_PARTITION_INFO_GET_REGS. 714 * Note that technically, all SPMCs can support this, but this code is 715 * under ifdef to minimize breakage in case other SPMCs do not save 716 * and restore x8-x17. 717 * We also need to pass through these registers since not all FF-A ABIs 718 * modify x8-x17, in which case, SMCCC requires that these registers be 719 * preserved, so the SPMD passes through these registers and expects the 720 * SPMC to save and restore (potentially also modify) them. 721 */ 722 SMC_RET18(cm_get_context(secure_state_out), smc_fid, x1, x2, x3, x4, 723 SMC_GET_GP(handle, CTX_GPREG_X5), 724 SMC_GET_GP(handle, CTX_GPREG_X6), 725 SMC_GET_GP(handle, CTX_GPREG_X7), 726 SMC_GET_GP(handle, CTX_GPREG_X8), 727 SMC_GET_GP(handle, CTX_GPREG_X9), 728 SMC_GET_GP(handle, CTX_GPREG_X10), 729 SMC_GET_GP(handle, CTX_GPREG_X11), 730 SMC_GET_GP(handle, CTX_GPREG_X12), 731 SMC_GET_GP(handle, CTX_GPREG_X13), 732 SMC_GET_GP(handle, CTX_GPREG_X14), 733 SMC_GET_GP(handle, CTX_GPREG_X15), 734 SMC_GET_GP(handle, CTX_GPREG_X16), 735 SMC_GET_GP(handle, CTX_GPREG_X17) 736 ); 737 738 #else 739 SMC_RET8(cm_get_context(secure_state_out), smc_fid, x1, x2, x3, x4, 740 SMC_GET_GP(handle, CTX_GPREG_X5), 741 SMC_GET_GP(handle, CTX_GPREG_X6), 742 SMC_GET_GP(handle, CTX_GPREG_X7)); 743 #endif 744 } 745 746 /******************************************************************************* 747 * Forward SMCs to the other security state. 748 ******************************************************************************/ 749 static uint64_t spmd_smc_forward(uint32_t smc_fid, 750 bool secure_origin, 751 uint64_t x1, 752 uint64_t x2, 753 uint64_t x3, 754 uint64_t x4, 755 void *cookie, 756 void *handle, 757 uint64_t flags) 758 { 759 if (is_spmc_at_el3() && !secure_origin) { 760 return spmc_smc_handler(smc_fid, secure_origin, x1, x2, x3, x4, 761 cookie, handle, flags); 762 } 763 764 return spmd_smc_switch_state(smc_fid, secure_origin, x1, x2, x3, x4, 765 handle, flags); 766 767 } 768 769 /******************************************************************************* 770 * Return FFA_ERROR with specified error code 771 ******************************************************************************/ 772 uint64_t spmd_ffa_error_return(void *handle, int error_code) 773 { 774 SMC_RET8(handle, (uint32_t) FFA_ERROR, 775 FFA_TARGET_INFO_MBZ, (uint32_t)error_code, 776 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 777 FFA_PARAM_MBZ, FFA_PARAM_MBZ); 778 } 779 780 /******************************************************************************* 781 * spmd_check_address_in_binary_image 782 ******************************************************************************/ 783 bool spmd_check_address_in_binary_image(uint64_t address) 784 { 785 assert(!check_uptr_overflow(spmc_attrs.load_address, spmc_attrs.binary_size)); 786 787 return ((address >= spmc_attrs.load_address) && 788 (address < (spmc_attrs.load_address + spmc_attrs.binary_size))); 789 } 790 791 /****************************************************************************** 792 * spmd_is_spmc_message 793 *****************************************************************************/ 794 static bool spmd_is_spmc_message(unsigned int ep) 795 { 796 if (is_spmc_at_el3()) { 797 return false; 798 } 799 800 return ((ffa_endpoint_destination(ep) == SPMD_DIRECT_MSG_ENDPOINT_ID) 801 && (ffa_endpoint_source(ep) == spmc_attrs.spmc_id)); 802 } 803 804 /****************************************************************************** 805 * spmd_handle_spmc_message 806 *****************************************************************************/ 807 static int spmd_handle_spmc_message(unsigned long long msg, 808 unsigned long long parm1, unsigned long long parm2, 809 unsigned long long parm3, unsigned long long parm4) 810 { 811 VERBOSE("%s %llx %llx %llx %llx %llx\n", __func__, 812 msg, parm1, parm2, parm3, parm4); 813 814 return -EINVAL; 815 } 816 817 /******************************************************************************* 818 * This function forwards FF-A SMCs to either the main SPMD handler or the 819 * SPMC at EL3, depending on the origin security state, if enabled. 820 ******************************************************************************/ 821 uint64_t spmd_ffa_smc_handler(uint32_t smc_fid, 822 uint64_t x1, 823 uint64_t x2, 824 uint64_t x3, 825 uint64_t x4, 826 void *cookie, 827 void *handle, 828 uint64_t flags) 829 { 830 if (is_spmc_at_el3()) { 831 /* 832 * If we have an SPMC at EL3 allow handling of the SMC first. 833 * The SPMC will call back through to SPMD handler if required. 834 */ 835 if (is_caller_secure(flags)) { 836 return spmc_smc_handler(smc_fid, 837 is_caller_secure(flags), 838 x1, x2, x3, x4, cookie, 839 handle, flags); 840 } 841 } 842 return spmd_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 843 handle, flags); 844 } 845 846 /******************************************************************************* 847 * This function handles all SMCs in the range reserved for FFA. Each call is 848 * either forwarded to the other security state or handled by the SPM dispatcher 849 ******************************************************************************/ 850 uint64_t spmd_smc_handler(uint32_t smc_fid, 851 uint64_t x1, 852 uint64_t x2, 853 uint64_t x3, 854 uint64_t x4, 855 void *cookie, 856 void *handle, 857 uint64_t flags) 858 { 859 unsigned int linear_id = plat_my_core_pos(); 860 spmd_spm_core_context_t *ctx = spmd_get_context(); 861 bool secure_origin; 862 int ret; 863 uint32_t input_version; 864 865 /* Determine which security state this SMC originated from */ 866 secure_origin = is_caller_secure(flags); 867 868 VERBOSE("SPM(%u): 0x%x 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 869 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 "\n", 870 linear_id, smc_fid, x1, x2, x3, x4, 871 SMC_GET_GP(handle, CTX_GPREG_X5), 872 SMC_GET_GP(handle, CTX_GPREG_X6), 873 SMC_GET_GP(handle, CTX_GPREG_X7)); 874 875 /* 876 * If there is an on-going info regs from EL3 SPMD LP, unconditionally 877 * return, we don't expect any other FF-A ABIs to be called between 878 * calls to FFA_PARTITION_INFO_GET_REGS. 879 */ 880 if (is_spmd_logical_sp_info_regs_req_in_progress(ctx)) { 881 assert(secure_origin); 882 spmd_spm_core_sync_exit(0ULL); 883 } 884 885 switch (smc_fid) { 886 case FFA_ERROR: 887 /* 888 * Check if this is the first invocation of this interface on 889 * this CPU. If so, then indicate that the SPM Core initialised 890 * unsuccessfully. 891 */ 892 if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) { 893 spmd_spm_core_sync_exit(x2); 894 } 895 896 /* 897 * If there was an SPMD logical partition direct request on-going, 898 * return back to the SPMD logical partition so the error can be 899 * consumed. 900 */ 901 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 902 assert(secure_origin); 903 spmd_spm_core_sync_exit(0ULL); 904 } 905 906 return spmd_smc_forward(smc_fid, secure_origin, 907 x1, x2, x3, x4, cookie, 908 handle, flags); 909 break; /* not reached */ 910 911 case FFA_VERSION: 912 input_version = (uint32_t)(0xFFFFFFFF & x1); 913 /* 914 * If caller is secure and SPMC was initialized, 915 * return FFA_VERSION of SPMD. 916 * If caller is non secure and SPMC was initialized, 917 * forward to the EL3 SPMC if enabled, otherwise return 918 * the SPMC version if implemented at a lower EL. 919 * Sanity check to "input_version". 920 * If the EL3 SPMC is enabled, ignore the SPMC state as 921 * this is not used. 922 */ 923 if ((input_version & FFA_VERSION_BIT31_MASK) || 924 (!is_spmc_at_el3() && (ctx->state == SPMC_STATE_RESET))) { 925 ret = FFA_ERROR_NOT_SUPPORTED; 926 } else if (!secure_origin) { 927 if (is_spmc_at_el3()) { 928 /* 929 * Forward the call directly to the EL3 SPMC, if 930 * enabled, as we don't need to wrap the call in 931 * a direct request. 932 */ 933 return spmd_smc_forward(smc_fid, secure_origin, 934 x1, x2, x3, x4, cookie, 935 handle, flags); 936 } 937 938 gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx); 939 uint64_t rc; 940 941 if (spmc_attrs.major_version == 1 && 942 spmc_attrs.minor_version == 0) { 943 ret = MAKE_FFA_VERSION(spmc_attrs.major_version, 944 spmc_attrs.minor_version); 945 SMC_RET8(handle, (uint32_t)ret, 946 FFA_TARGET_INFO_MBZ, 947 FFA_TARGET_INFO_MBZ, 948 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 949 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 950 FFA_PARAM_MBZ); 951 break; 952 } 953 /* Save non-secure system registers context */ 954 cm_el1_sysregs_context_save(NON_SECURE); 955 #if SPMD_SPM_AT_SEL2 956 cm_el2_sysregs_context_save(NON_SECURE); 957 #endif 958 959 /* 960 * The incoming request has FFA_VERSION as X0 smc_fid 961 * and requested version in x1. Prepare a direct request 962 * from SPMD to SPMC with FFA_VERSION framework function 963 * identifier in X2 and requested version in X3. 964 */ 965 spmd_build_spmc_message(gpregs, 966 SPMD_FWK_MSG_FFA_VERSION_REQ, 967 input_version); 968 969 /* 970 * Ensure x8-x17 NS GP register values are untouched when returning 971 * from the SPMC. 972 */ 973 write_ctx_reg(gpregs, CTX_GPREG_X8, SMC_GET_GP(handle, CTX_GPREG_X8)); 974 write_ctx_reg(gpregs, CTX_GPREG_X9, SMC_GET_GP(handle, CTX_GPREG_X9)); 975 write_ctx_reg(gpregs, CTX_GPREG_X10, SMC_GET_GP(handle, CTX_GPREG_X10)); 976 write_ctx_reg(gpregs, CTX_GPREG_X11, SMC_GET_GP(handle, CTX_GPREG_X11)); 977 write_ctx_reg(gpregs, CTX_GPREG_X12, SMC_GET_GP(handle, CTX_GPREG_X12)); 978 write_ctx_reg(gpregs, CTX_GPREG_X13, SMC_GET_GP(handle, CTX_GPREG_X13)); 979 write_ctx_reg(gpregs, CTX_GPREG_X14, SMC_GET_GP(handle, CTX_GPREG_X14)); 980 write_ctx_reg(gpregs, CTX_GPREG_X15, SMC_GET_GP(handle, CTX_GPREG_X15)); 981 write_ctx_reg(gpregs, CTX_GPREG_X16, SMC_GET_GP(handle, CTX_GPREG_X16)); 982 write_ctx_reg(gpregs, CTX_GPREG_X17, SMC_GET_GP(handle, CTX_GPREG_X17)); 983 984 rc = spmd_spm_core_sync_entry(ctx); 985 986 if ((rc != 0ULL) || 987 (SMC_GET_GP(gpregs, CTX_GPREG_X0) != 988 FFA_MSG_SEND_DIRECT_RESP_SMC32) || 989 (SMC_GET_GP(gpregs, CTX_GPREG_X2) != 990 (FFA_FWK_MSG_BIT | 991 SPMD_FWK_MSG_FFA_VERSION_RESP))) { 992 ERROR("Failed to forward FFA_VERSION\n"); 993 ret = FFA_ERROR_NOT_SUPPORTED; 994 } else { 995 ret = SMC_GET_GP(gpregs, CTX_GPREG_X3); 996 } 997 998 /* 999 * x0-x4 are updated by spmd_smc_forward below. 1000 * Zero out x5-x7 in the FFA_VERSION response. 1001 */ 1002 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 1003 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 1004 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 1005 1006 /* 1007 * Return here after SPMC has handled FFA_VERSION. 1008 * The returned SPMC version is held in X3. 1009 * Forward this version in X0 to the non-secure caller. 1010 */ 1011 return spmd_smc_forward(ret, true, FFA_PARAM_MBZ, 1012 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1013 FFA_PARAM_MBZ, cookie, gpregs, 1014 flags); 1015 } else { 1016 ret = MAKE_FFA_VERSION(FFA_VERSION_MAJOR, 1017 FFA_VERSION_MINOR); 1018 } 1019 1020 SMC_RET8(handle, (uint32_t)ret, FFA_TARGET_INFO_MBZ, 1021 FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1022 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ); 1023 break; /* not reached */ 1024 1025 case FFA_FEATURES: 1026 /* 1027 * This is an optional interface. Do the minimal checks and 1028 * forward to SPM Core which will handle it if implemented. 1029 */ 1030 1031 /* Forward SMC from Normal world to the SPM Core */ 1032 if (!secure_origin) { 1033 return spmd_smc_forward(smc_fid, secure_origin, 1034 x1, x2, x3, x4, cookie, 1035 handle, flags); 1036 } 1037 1038 /* 1039 * Return success if call was from secure world i.e. all 1040 * FFA functions are supported. This is essentially a 1041 * nop. 1042 */ 1043 SMC_RET8(handle, FFA_SUCCESS_SMC32, x1, x2, x3, x4, 1044 SMC_GET_GP(handle, CTX_GPREG_X5), 1045 SMC_GET_GP(handle, CTX_GPREG_X6), 1046 SMC_GET_GP(handle, CTX_GPREG_X7)); 1047 1048 break; /* not reached */ 1049 1050 case FFA_ID_GET: 1051 /* 1052 * Returns the ID of the calling FFA component. 1053 */ 1054 if (!secure_origin) { 1055 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1056 FFA_TARGET_INFO_MBZ, FFA_NS_ENDPOINT_ID, 1057 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1058 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1059 FFA_PARAM_MBZ); 1060 } 1061 1062 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1063 FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id, 1064 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1065 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1066 FFA_PARAM_MBZ); 1067 1068 break; /* not reached */ 1069 1070 case FFA_SECONDARY_EP_REGISTER_SMC64: 1071 if (secure_origin) { 1072 ret = spmd_pm_secondary_ep_register(x1); 1073 1074 if (ret < 0) { 1075 SMC_RET8(handle, FFA_ERROR_SMC64, 1076 FFA_TARGET_INFO_MBZ, ret, 1077 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1078 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1079 FFA_PARAM_MBZ); 1080 } else { 1081 SMC_RET8(handle, FFA_SUCCESS_SMC64, 1082 FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ, 1083 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1084 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1085 FFA_PARAM_MBZ); 1086 } 1087 } 1088 1089 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1090 break; /* Not reached */ 1091 1092 case FFA_SPM_ID_GET: 1093 if (MAKE_FFA_VERSION(1, 1) > FFA_VERSION_COMPILED) { 1094 return spmd_ffa_error_return(handle, 1095 FFA_ERROR_NOT_SUPPORTED); 1096 } 1097 /* 1098 * Returns the ID of the SPMC or SPMD depending on the FF-A 1099 * instance where this function is invoked 1100 */ 1101 if (!secure_origin) { 1102 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1103 FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id, 1104 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1105 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1106 FFA_PARAM_MBZ); 1107 } 1108 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1109 FFA_TARGET_INFO_MBZ, SPMD_DIRECT_MSG_ENDPOINT_ID, 1110 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1111 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1112 FFA_PARAM_MBZ); 1113 1114 break; /* not reached */ 1115 1116 case FFA_MSG_SEND_DIRECT_REQ_SMC32: 1117 case FFA_MSG_SEND_DIRECT_REQ_SMC64: 1118 /* 1119 * Regardless of secure_origin, SPMD logical partitions cannot 1120 * handle direct messages. They can only initiate direct 1121 * messages and consume direct responses or errors. 1122 */ 1123 if (is_spmd_lp_id(ffa_endpoint_source(x1)) || 1124 is_spmd_lp_id(ffa_endpoint_destination(x1))) { 1125 return spmd_ffa_error_return(handle, 1126 FFA_ERROR_INVALID_PARAMETER 1127 ); 1128 } 1129 1130 /* 1131 * When there is an ongoing SPMD logical partition direct 1132 * request, there cannot be another direct request. Return 1133 * error in this case. Panic'ing is an option but that does 1134 * not provide the opportunity for caller to abort based on 1135 * error codes. 1136 */ 1137 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 1138 assert(secure_origin); 1139 return spmd_ffa_error_return(handle, 1140 FFA_ERROR_DENIED); 1141 } 1142 1143 if (!secure_origin) { 1144 /* Validate source endpoint is non-secure for non-secure caller. */ 1145 if (ffa_is_secure_world_id(ffa_endpoint_source(x1))) { 1146 return spmd_ffa_error_return(handle, 1147 FFA_ERROR_INVALID_PARAMETER); 1148 } 1149 } 1150 if (secure_origin && spmd_is_spmc_message(x1)) { 1151 ret = spmd_handle_spmc_message(x3, x4, 1152 SMC_GET_GP(handle, CTX_GPREG_X5), 1153 SMC_GET_GP(handle, CTX_GPREG_X6), 1154 SMC_GET_GP(handle, CTX_GPREG_X7)); 1155 1156 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1157 FFA_TARGET_INFO_MBZ, ret, 1158 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1159 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1160 FFA_PARAM_MBZ); 1161 } else { 1162 /* Forward direct message to the other world */ 1163 return spmd_smc_forward(smc_fid, secure_origin, 1164 x1, x2, x3, x4, cookie, 1165 handle, flags); 1166 } 1167 break; /* Not reached */ 1168 1169 case FFA_MSG_SEND_DIRECT_REQ2_SMC64: 1170 if (!secure_origin) { 1171 /* Validate source endpoint is non-secure for non-secure caller. */ 1172 if (ffa_is_secure_world_id(ffa_endpoint_source(x1))) { 1173 return spmd_ffa_error_return(handle, 1174 FFA_ERROR_INVALID_PARAMETER); 1175 } 1176 } 1177 /* FFA_MSG_SEND_DIRECT_REQ2 not used for framework messages. */ 1178 if (secure_origin && spmd_is_spmc_message(x1)) { 1179 return spmd_ffa_error_return(handle, FFA_ERROR_INVALID_PARAMETER); 1180 } else { 1181 /* Forward direct message to the other world */ 1182 return spmd_smc_forward(smc_fid, secure_origin, 1183 x1, x2, x3, x4, cookie, 1184 handle, flags); 1185 } 1186 break; /* Not reached */ 1187 1188 case FFA_MSG_SEND_DIRECT_RESP_SMC32: 1189 case FFA_MSG_SEND_DIRECT_RESP_SMC64: 1190 if (secure_origin && (spmd_is_spmc_message(x1) || 1191 is_spmd_logical_sp_dir_req_in_progress(ctx))) { 1192 spmd_spm_core_sync_exit(0ULL); 1193 } else { 1194 /* Forward direct message to the other world */ 1195 return spmd_smc_forward(smc_fid, secure_origin, 1196 x1, x2, x3, x4, cookie, 1197 handle, flags); 1198 } 1199 break; /* Not reached */ 1200 case FFA_MSG_SEND_DIRECT_RESP2_SMC64: 1201 /* Forward direct message to the other world */ 1202 return spmd_smc_forward(smc_fid, secure_origin, 1203 x1, x2, x3, x4, cookie, 1204 handle, flags); 1205 break; /* Not reached */ 1206 case FFA_RX_RELEASE: 1207 case FFA_RXTX_MAP_SMC32: 1208 case FFA_RXTX_MAP_SMC64: 1209 case FFA_RXTX_UNMAP: 1210 case FFA_PARTITION_INFO_GET: 1211 #if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED 1212 case FFA_NOTIFICATION_BITMAP_CREATE: 1213 case FFA_NOTIFICATION_BITMAP_DESTROY: 1214 case FFA_NOTIFICATION_BIND: 1215 case FFA_NOTIFICATION_UNBIND: 1216 case FFA_NOTIFICATION_SET: 1217 case FFA_NOTIFICATION_GET: 1218 case FFA_NOTIFICATION_INFO_GET: 1219 case FFA_NOTIFICATION_INFO_GET_SMC64: 1220 case FFA_MSG_SEND2: 1221 case FFA_RX_ACQUIRE: 1222 #endif 1223 case FFA_MSG_RUN: 1224 /* 1225 * Above calls should be invoked only by the Normal world and 1226 * must not be forwarded from Secure world to Normal world. 1227 */ 1228 if (secure_origin) { 1229 return spmd_ffa_error_return(handle, 1230 FFA_ERROR_NOT_SUPPORTED); 1231 } 1232 1233 /* Forward the call to the other world */ 1234 /* fallthrough */ 1235 case FFA_MSG_SEND: 1236 case FFA_MEM_DONATE_SMC32: 1237 case FFA_MEM_DONATE_SMC64: 1238 case FFA_MEM_LEND_SMC32: 1239 case FFA_MEM_LEND_SMC64: 1240 case FFA_MEM_SHARE_SMC32: 1241 case FFA_MEM_SHARE_SMC64: 1242 case FFA_MEM_RETRIEVE_REQ_SMC32: 1243 case FFA_MEM_RETRIEVE_REQ_SMC64: 1244 case FFA_MEM_RETRIEVE_RESP: 1245 case FFA_MEM_RELINQUISH: 1246 case FFA_MEM_RECLAIM: 1247 case FFA_MEM_FRAG_TX: 1248 case FFA_MEM_FRAG_RX: 1249 case FFA_SUCCESS_SMC32: 1250 case FFA_SUCCESS_SMC64: 1251 /* 1252 * If there is an ongoing direct request from an SPMD logical 1253 * partition, return an error. 1254 */ 1255 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 1256 assert(secure_origin); 1257 return spmd_ffa_error_return(handle, 1258 FFA_ERROR_DENIED); 1259 } 1260 1261 return spmd_smc_forward(smc_fid, secure_origin, 1262 x1, x2, x3, x4, cookie, 1263 handle, flags); 1264 break; /* not reached */ 1265 1266 case FFA_MSG_WAIT: 1267 /* 1268 * Check if this is the first invocation of this interface on 1269 * this CPU from the Secure world. If so, then indicate that the 1270 * SPM Core initialised successfully. 1271 */ 1272 if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) { 1273 spmd_spm_core_sync_exit(0ULL); 1274 } 1275 1276 /* Forward the call to the other world */ 1277 /* fallthrough */ 1278 case FFA_INTERRUPT: 1279 case FFA_MSG_YIELD: 1280 /* This interface must be invoked only by the Secure world */ 1281 if (!secure_origin) { 1282 return spmd_ffa_error_return(handle, 1283 FFA_ERROR_NOT_SUPPORTED); 1284 } 1285 1286 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 1287 assert(secure_origin); 1288 return spmd_ffa_error_return(handle, 1289 FFA_ERROR_DENIED); 1290 } 1291 1292 return spmd_smc_forward(smc_fid, secure_origin, 1293 x1, x2, x3, x4, cookie, 1294 handle, flags); 1295 break; /* not reached */ 1296 1297 case FFA_NORMAL_WORLD_RESUME: 1298 if (secure_origin && ctx->secure_interrupt_ongoing) { 1299 spmd_spm_core_sync_exit(0ULL); 1300 } else { 1301 return spmd_ffa_error_return(handle, FFA_ERROR_DENIED); 1302 } 1303 break; /* Not reached */ 1304 #if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED 1305 case FFA_PARTITION_INFO_GET_REGS_SMC64: 1306 if (secure_origin) { 1307 return spmd_el3_populate_logical_partition_info(handle, x1, 1308 x2, x3); 1309 } 1310 1311 /* Call only supported with SMCCC 1.2+ */ 1312 if (MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION) < 0x10002) { 1313 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1314 } 1315 1316 return spmd_smc_forward(smc_fid, secure_origin, 1317 x1, x2, x3, x4, cookie, 1318 handle, flags); 1319 break; /* Not reached */ 1320 #endif 1321 case FFA_CONSOLE_LOG_SMC32: 1322 case FFA_CONSOLE_LOG_SMC64: 1323 /* This interface must not be forwarded to other worlds. */ 1324 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1325 break; /* not reached */ 1326 1327 case FFA_EL3_INTR_HANDLE: 1328 if (secure_origin) { 1329 return spmd_handle_group0_intr_swd(handle); 1330 } else { 1331 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1332 } 1333 default: 1334 WARN("SPM: Unsupported call 0x%08x\n", smc_fid); 1335 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1336 } 1337 } 1338