Merge "feat(cpus): add support for Canyon CPU" into integration

refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of

refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of assembly was
that the get_cpu_ops_ptr() function was not PCS compliant and needed a
wrapper to do that instead. That has now been fixed so move this to C so
it's more readable and more optimise-able by the compiler.

Change-Id: I5fcfe8ddb122dd35d58adc6d44a7484c5c595815
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.

When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.

At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e

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feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
S

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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Merge changes from topic "xlnx_misra_fix_gen_pmuv3" into integration

* changes:
fix(lib): modify function to have single return
fix(lib): use 64-bit constants in MDCR_EL2 bit macros

Merge "fix(psci): add missing curly braces" into integration

Merge "fix(psci): initialise variable to default zero" into integration

fix(smccc): resolve caller world confusion

TF-A checks the SMC caller world using is_caller_secure,
is_caller_non_secure and is_caller_realm macros. Until
realm world was introduced it was fine to u

fix(smccc): resolve caller world confusion

TF-A checks the SMC caller world using is_caller_secure,
is_caller_non_secure and is_caller_realm macros. Until
realm world was introduced it was fine to use a pattern like

if (is_caller_non_secure(flags))
return DENY;

// Handle secure call
secure_operation();

is_caller_non_secure would be false for a realm caller, so this pattern
treats this like a secure world caller. This patch fixes
improper use of is_caller_non_secure and is_caller_secure
to handle realm world caller properly.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I60b125853183ac2ac15277f06d2efb7f3a9d3977

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fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body w

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: Ida2460b7fe6f27b23382a1259a5ac93fe36bd48d
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(cm): use safe casting in memcpy

This corrects the MISRA violation C2012-21.15:
Both gp_regs and ep->args were cast to the correct pointer types to
avoid incompatible argument types in memcpy().

fix(cm): use safe casting in memcpy

This corrects the MISRA violation C2012-21.15:
Both gp_regs and ep->args were cast to the correct pointer types to
avoid incompatible argument types in memcpy(). This fix ensures type
compatibility and adheres to MISRA 21.15, which disallows implicit
casting between unrelated types

Change-Id: Iad1d78574e423b46934a5978bdcbe2d5fb78e910
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge "fix(cpus): correct alto library" into integration

fix(aarch32): make get_cpu_ops_ptr() PCS compliant

The get_cpu_ops_ptr() function gets called from C (mainly in errata
reporting) but it is not PCS compliant - it clobbers r4 and r5. This
doesn't us

fix(aarch32): make get_cpu_ops_ptr() PCS compliant

The get_cpu_ops_ptr() function gets called from C (mainly in errata
reporting) but it is not PCS compliant - it clobbers r4 and r5. This
doesn't usually cause any problems, but if the stars align it blows up.

Convert the heart of the function to a non-PCS compliant macro that can
be invoked in the early entrypoint code and change the get_cpu_ops_ptr()
to a PCS compliant wrapper for calling into C. Additionally, the
resultant inlining in the entrypoint will lead to a tiny performance
bump due to the one fewer jump to an uncached memory location.

Change-Id: I7f3b50e56a1288d2a8136a7b8c01544bab19c57b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpus): correct alto library

Powerdown handling is updated to reflect powerdown
abandon changes and incorrect error message has been fixed.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@a

fix(cpus): correct alto library

Powerdown handling is updated to reflect powerdown
abandon changes and incorrect error message has been fixed.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I7d33542c13c52e74261937f96327951c0116fbd1

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fix(xlat): typecast expressions to match data type

This corrects the MISRA violation C2012-11.5:
type casting the void pointer expression with the object pointer type.

Change-Id: I9f4b648509662e6f6

fix(xlat): typecast expressions to match data type

This corrects the MISRA violation C2012-11.5:
type casting the void pointer expression with the object pointer type.

Change-Id: I9f4b648509662e6f6e676613f3cc3984815c9862
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(lib): modify function to have single return

This corrects the MISRA violation C2012-15.5:
function should have a single point of exit at the end.
Introduced a temporary variable to store the ret

fix(lib): modify function to have single return

This corrects the MISRA violation C2012-15.5:
function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function

Change-Id: Ib9941afe23f5988e5c569171563169f8f10f2b94
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(psci): initialize the variables

This corrects the MISRA violation C2012-9.1:
All variables are explicitly initialized with zero or default values
during declaration. This helps, even if a functi

fix(psci): initialize the variables

This corrects the MISRA violation C2012-9.1:
All variables are explicitly initialized with zero or default values
during declaration. This helps, even if a function fails, the
variables contain predictable values, preventing undefined behavior

Change-Id: I910467fd03e434e32da01e421fe77ec1402bc15a
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:
The value of an object with automatic storage duration shall not
be read before it has been set.
Initializ

fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:
The value of an object with automatic storage duration shall not
be read before it has been set.
Initialized the variable to default value zero.

Change-Id: I225ae4487b05fc47728222765029d6e1fe292ac1
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(lib): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I

fix(lib): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I979ba118fd209be5d4f0bff3978479c22428d79b
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(cpus): workaround for Cortex-X4 erratum 3887999

Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.

The erratum can be avoided by setting CPUAC

fix(cpus): workaround for Cortex-X4 erratum 3887999

Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I851746b7b430eac85184c8d402d1aa5bb3c94a8e

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fix(cpus): workaround for Cortex-X4 erratum 3133195

Cortex-X4 erratum 3133195 is a Cat B erratum that applies
to all revisions = r0p2 and is fixed in r0p3.

This erratum can be avoided by writing to

fix(cpus): workaround for Cortex-X4 erratum 3133195

Cortex-X4 erratum 3133195 is a Cat B erratum that applies
to all revisions = r0p2 and is fixed in r0p3.

This erratum can be avoided by writing to a set of implementation
defined registers which will execute a PSB instruction following
the TSB CSYNC instruction.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Id44daf950124e7c2d46cb5d6d6a1083d06fad12d

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fix(cpus): organize Cortex-X2 errata entries

The entries in cpu-ops.mk and cpu-specific-build-macros.rst are out of
order and the formatting is not consistent. This patch corrects these
minor format

fix(cpus): organize Cortex-X2 errata entries

The entries in cpu-ops.mk and cpu-specific-build-macros.rst are out of
order and the formatting is not consistent. This patch corrects these
minor formatting issues.

Change-Id: Ic01517d58d3ca1b2d39be5282b0058c94fa5d0e7
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 2291219

Cortex-X2 erratum 2291219 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTL

fix(cpus): workaround for Cortex-X2 erratum 2291219

Cortex-X2 erratum 2291219 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTLR2_EL1[36] before the power
down sequence that sets PWRDN_EN and executes WFI. This bit
should be be cleared after exiting WFI.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I43af57961feba3a1c001d09ad804740b996f1db7
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 2267065

Cortex-X2 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTL

fix(cpus): workaround for Cortex-X2 erratum 2267065

Cortex-X2 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTLR_EL1[22].

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I540e113f209ef11ec7103d4ef4e48ffb52416b4e
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 2136059

Cortex-X2 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTL

fix(cpus): workaround for Cortex-X2 erratum 2136059

Cortex-X2 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTLR5_EL1[44].

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I156467537c3f235b50fc8aa19a969f2798bd891b
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 1934260

Cortex-X2 erratum 1934260 is a Cat B erratum that applies only
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[25:18

fix(cpus): workaround for Cortex-X2 erratum 1934260

Cortex-X2 erratum 1934260 is a Cat B erratum that applies only
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[25:18] to 0xFF. This
workaround will result in reduced performance for workloads
that benefit from write streaming.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I180d38fee27175dc8ac5fa6726e5b71c3340285f
Signed-off-by: John Powell <john.powell@arm.com>

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