| bb9549ba | 02-Dec-2019 |
Jan Dabros <jsd@semihalf.com> |
aarch64: Fix stack pointer maintenance on EA handling path
EA handlers for exceptions taken from lower ELs at the end invokes
el3_exit function. However there was a bug with sp maintenance which
res
aarch64: Fix stack pointer maintenance on EA handling path
EA handlers for exceptions taken from lower ELs at the end invokes
el3_exit function. However there was a bug with sp maintenance which
resulted in el3_exit setting runtime stack to context. This in turn
caused memory corruption on consecutive EL3 entries.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0424245c27c369c864506f4baa719968890ce659
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|
| d310239d | 06-Nov-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
debugfs: add FIP device
Add a FIP driver hooked to debugfs 9p interface. This is an
abstraction of the FIP filesystem layer on top of a mass storage,
or memory block driver.
Signed-off-by: Olivier
debugfs: add FIP device
Add a FIP driver hooked to debugfs 9p interface. This is an
abstraction of the FIP filesystem layer on top of a mass storage,
or memory block driver.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: If275ea0824763de43ab666dab2a06de5352ff940
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|
| 0ca3913d | 19-Sep-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
debugfs: add 9p device interface
The 9p interface provides abstraction layers allowing the software
that uses devices to be independent from the hardware.
This patch provides a file system abstract
debugfs: add 9p device interface
The 9p interface provides abstraction layers allowing the software
that uses devices to be independent from the hardware.
This patch provides a file system abstraction to link drivers to their
devices and propose a common interface to expose driver operations to
higher layers. This file system can be used to access and configure a
device by doing read/write operations.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia9662393baf489855dc0c8f389fe4a0afbc9c255
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|
| 2bcc672f | 13-Dec-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "aa/sel2_support" into integration
* changes:
S-EL2 Support: Check for AArch64
Add support for enabling S-EL2 |
| fcccd358 | 11-Dec-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "libc: add memrchr" into integration |
| ebff1072 | 19-Jun-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
libc: add memrchr
This function scans a string backwards from the end for the first
instance of a character.
Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763
Signed-off-by: Ambroise Vincent <am
libc: add memrchr
This function scans a string backwards from the end for the first
instance of a character.
Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| db3ae853 | 26-Nov-2019 |
Artsem Artsemenka <artsem.artsemenka@arm.com> |
S-EL2 Support: Check for AArch64
Check that entry point information requesting S-EL2
has AArch64 as an execution state during context setup.
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.
S-EL2 Support: Check for AArch64
Check that entry point information requesting S-EL2
has AArch64 as an execution state during context setup.
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I447263692fed6e55c1b076913e6eb73b1ea735b7
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|
| 0376e7c4 | 11-Oct-2019 |
Achin Gupta <achin.gupta@arm.com> |
Add support for enabling S-EL2
This patch adds support for enabling S-EL2 if this EL is specified in the entry
point information being used to initialise a secure context. It is the caller's
respons
Add support for enabling S-EL2
This patch adds support for enabling S-EL2 if this EL is specified in the entry
point information being used to initialise a secure context. It is the caller's
responsibility to check if S-EL2 is available on the system before requesting
this EL through the entry point information.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Change-Id: I2752964f078ab528b2e80de71c7d2f35e60569e1
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|
| ab4df50c | 15-Oct-2019 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
adding support to enable different personality of the same soc.
Same SoC has different personality by creating different number of:
- cores
- clusters.
As a result, the platform specific power doma
adding support to enable different personality of the same soc.
Same SoC has different personality by creating different number of:
- cores
- clusters.
As a result, the platform specific power domain tree will be created
after identify the personality of the SoC.
Hence, platform specific power domain tree may not be same for all the
personality of the soc.
Thus, psci library code will deduce the 'plat_core_count', while
populating the power domain tree topology and return the number of
cores.
PLATFORM_CORE_COUNT will still be valid for a SoC, such that
psci_plat_core_count <= PLATFORM_CORE_COUNT.
PLATFORM_CORE_COUNT will continued to be defined by platform to create
the data structures.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I1f5c47647631cae2dcdad540d64cf09757db7185
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|
| b27280a8 | 15-Nov-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "Coding guideline suggest not to use unsigned long" into integration |
| 0efb83e1 | 13-Nov-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "Fix white space errors + remove #if defined" into integration |
| 9afe8cdc | 03-Sep-2019 |
Deepika Bhavnani <deepika.bhavnani@arm.com> |
Coding guideline suggest not to use unsigned long
`unsigned long` should be replaced to
1. `unsigned int` or `unsigned long long` - If fixed,
based on the architecture AArch32 or AArch64
2. `u_regis
Coding guideline suggest not to use unsigned long
`unsigned long` should be replaced to
1. `unsigned int` or `unsigned long long` - If fixed,
based on the architecture AArch32 or AArch64
2. `u_register_t` - If it is supposed to be 32-bit
wide in AArch32 and 64-bit wide in AArch64.
Translation descriptors are always 32-bit wide, here
`uint32_t` is used to describe the `exact size` of
translation descriptors instead of `unsigned int` which
guarantees minimum 32-bits
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I6a2af2e8b3c71170e2634044e0b887f07a41677e
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|
| 494d57e8 | 12-Nov-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "Disable stack protection explicitly" into integration |
| 22cab650 | 11-Oct-2019 |
laurenw-arm <lauren.wehrmeister@arm.com> |
Fix white space errors + remove #if defined
Fix a few white space errors and remove #if defined in workaround
for N1 Errata 1542419.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
C
Fix white space errors + remove #if defined
Fix a few white space errors and remove #if defined in workaround
for N1 Errata 1542419.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad
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|
| 7af195e2 | 20-Oct-2019 |
Simon South <simon@simonsouth.net> |
Disable stack protection explicitly
Explicitly disable stack protection via the "-fno-stack-protector"
compiler option when the ENABLE_STACK_PROTECTOR build option is
set to "none" (the default).
T
Disable stack protection explicitly
Explicitly disable stack protection via the "-fno-stack-protector"
compiler option when the ENABLE_STACK_PROTECTOR build option is
set to "none" (the default).
This allows the build to complete without link errors on systems where
stack protection is enabled by default in the compiler.
Change-Id: I0a676aa672815235894fb2cd05fa2b196fabb972
Signed-off-by: Simon South <simon@simonsouth.net>
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|
| 0e7a0540 | 17-Oct-2019 |
Artsem Artsemenka <artsem.artsemenka@arm.com> |
xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config
The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during
the boot. But the xlat_change_mem_attributes_ctx() API did n
xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config
The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during
the boot. But the xlat_change_mem_attributes_ctx() API did not do the required
cache maintenance after the mmap tables are modified if
WARMBOOT_ENABLE_DCACHE_EARLY is enabled. This meant that when the caches are turned
off during power down, the tables in memory are accessed as part of cache
maintenance for power down, and the tables are not correct at this point which
results in a data abort.
This patch removes the optimization within xlat_change_mem_attributes_ctx()
when WARMBOOT_ENABLE_DCACHE_EARLY is enabled.
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I82de3decba87dd13e9856b5f3620a1c8571c8d87
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|
| 25792ce4 | 07-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Neoverse N1 Errata Workaround 1542419" into integration |
| 5b567758 | 07-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Fix the CAS spinlock implementation" into integration |
| 80942622 | 20-Aug-2019 |
laurenw-arm <lauren.wehrmeister@arm.com> |
Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instr
Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
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|
| c97cba4e | 25-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Fix the CAS spinlock implementation
Make the spinlock implementation use ARMv8.1-LSE CAS instruction based
on a platform build option. The CAS-based implementation used to be
unconditionally selecte
Fix the CAS spinlock implementation
Make the spinlock implementation use ARMv8.1-LSE CAS instruction based
on a platform build option. The CAS-based implementation used to be
unconditionally selected for all ARM8.1+ platforms.
The previous CAS spinlock implementation had a bug wherein the spin_unlock()
implementation had an `sev` after `stlr` which is not sufficient. A dsb is
needed to ensure that the stlr completes prior to the sev. Having a dsb is
heavyweight and a better solution would be to use load exclusive semantics
to monitor the lock and wake up from wfe when a store happens to the lock.
The patch implements the same.
Change-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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|
| cf9319f4 | 03-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U" into integration |
| 530ceda5 | 01-Oct-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U
This patch adds support for ARMv8.3-PAuth in BL1 SMC calls and
BL2U image for firmware updates by programming APIAKey_EL1 registers
and
TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U
This patch adds support for ARMv8.3-PAuth in BL1 SMC calls and
BL2U image for firmware updates by programming APIAKey_EL1 registers
and enabling Pointer Authentication in EL3 and EL1 respectively.
Change-Id: I875d952aba8242caf74fb5f4f2d2af6f0c768c08
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| 78f02ae2 | 22-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Introducing support for Cortex-A65AE
Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422
Signed-off-by: Imre Kis <imre.kis@arm.com> |
| 6ad216dc | 18-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Introducing support for Cortex-A65
Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47
Signed-off-by: Imre Kis <imre.kis@arm.com> |
| 3bdade5d | 01-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Cortex_hercules: Add support for Hercules-AE" into integration |