1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/twed.h> 26 #include <lib/utils.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_e1_sysreg_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 u_register_t scr_el3; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 u_register_t sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if !HANDLE_EA_EL3_FIRST 112 /* 113 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 114 * to EL3 when executing at a lower EL. When executing at EL3, External 115 * Aborts are taken to EL3. 116 */ 117 scr_el3 &= ~SCR_EA_BIT; 118 #endif 119 120 #if FAULT_INJECTION_SUPPORT 121 /* Enable fault injection from lower ELs */ 122 scr_el3 |= SCR_FIEN_BIT; 123 #endif 124 125 #if !CTX_INCLUDE_PAUTH_REGS 126 /* 127 * If the pointer authentication registers aren't saved during world 128 * switches the value of the registers can be leaked from the Secure to 129 * the Non-secure world. To prevent this, rather than enabling pointer 130 * authentication everywhere, we only enable it in the Non-secure world. 131 * 132 * If the Secure world wants to use pointer authentication, 133 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 134 */ 135 if (security_state == NON_SECURE) 136 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 137 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 138 139 /* 140 * Enable MTE support. Support is enabled unilaterally for the normal 141 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 142 * set. 143 */ 144 #if CTX_INCLUDE_MTE_REGS 145 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); 146 scr_el3 |= SCR_ATA_BIT; 147 #else 148 unsigned int mte = get_armv8_5_mte_support(); 149 if (mte == MTE_IMPLEMENTED_EL0) { 150 /* 151 * Can enable MTE across both worlds as no MTE registers are 152 * used 153 */ 154 scr_el3 |= SCR_ATA_BIT; 155 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { 156 /* 157 * Can only enable MTE in Non-Secure world without register 158 * saving 159 */ 160 scr_el3 |= SCR_ATA_BIT; 161 } 162 #endif 163 164 #ifdef IMAGE_BL31 165 /* 166 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 167 * indicated by the interrupt routing model for BL31. 168 */ 169 scr_el3 |= get_scr_el3_from_routing_model(security_state); 170 #endif 171 172 /* 173 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 174 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 175 * next mode is Hyp. 176 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 177 * same conditions as HVC instructions and when the processor supports 178 * ARMv8.6-FGT. 179 */ 180 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 181 || ((GET_RW(ep->spsr) != MODE_RW_64) 182 && (GET_M32(ep->spsr) == MODE32_hyp))) { 183 scr_el3 |= SCR_HCE_BIT; 184 185 if (is_armv8_6_fgt_present()) { 186 scr_el3 |= SCR_FGTEN_BIT; 187 } 188 } 189 190 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 191 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 192 if (GET_RW(ep->spsr) != MODE_RW_64) { 193 ERROR("S-EL2 can not be used in AArch32."); 194 panic(); 195 } 196 197 scr_el3 |= SCR_EEL2_BIT; 198 } 199 200 /* 201 * Initialise SCTLR_EL1 to the reset value corresponding to the target 202 * execution state setting all fields rather than relying of the hw. 203 * Some fields have architecturally UNKNOWN reset values and these are 204 * set to zero. 205 * 206 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 207 * 208 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 209 * required by PSCI specification) 210 */ 211 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 212 if (GET_RW(ep->spsr) == MODE_RW_64) 213 sctlr_elx |= SCTLR_EL1_RES1; 214 else { 215 /* 216 * If the target execution state is AArch32 then the following 217 * fields need to be set. 218 * 219 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 220 * instructions are not trapped to EL1. 221 * 222 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 223 * instructions are not trapped to EL1. 224 * 225 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 226 * CP15DMB, CP15DSB, and CP15ISB instructions. 227 */ 228 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 229 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 230 } 231 232 #if ERRATA_A75_764081 233 /* 234 * If workaround of errata 764081 for Cortex-A75 is used then set 235 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 236 */ 237 sctlr_elx |= SCTLR_IESB_BIT; 238 #endif 239 240 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 241 if (is_armv8_6_twed_present()) { 242 uint32_t delay = plat_arm_set_twedel_scr_el3(); 243 244 if (delay != TWED_DISABLED) { 245 /* Make sure delay value fits */ 246 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 247 248 /* Set delay in SCR_EL3 */ 249 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 250 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 251 << SCR_TWEDEL_SHIFT); 252 253 /* Enable WFE delay */ 254 scr_el3 |= SCR_TWEDEn_BIT; 255 } 256 } 257 258 /* 259 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 260 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 261 * are not part of the stored cpu_context. 262 */ 263 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 264 265 /* 266 * Base the context ACTLR_EL1 on the current value, as it is 267 * implementation defined. The context restore process will write 268 * the value from the context to the actual register and can cause 269 * problems for processor cores that don't expect certain bits to 270 * be zero. 271 */ 272 actlr_elx = read_actlr_el1(); 273 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 274 275 /* 276 * Populate EL3 state so that we've the right context 277 * before doing ERET 278 */ 279 state = get_el3state_ctx(ctx); 280 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 281 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 282 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 283 284 /* 285 * Store the X0-X7 value from the entrypoint into the context 286 * Use memcpy as we are in control of the layout of the structures 287 */ 288 gp_regs = get_gpregs_ctx(ctx); 289 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 290 } 291 292 /******************************************************************************* 293 * Enable architecture extensions on first entry to Non-secure world. 294 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 295 * it is zero. 296 ******************************************************************************/ 297 static void enable_extensions_nonsecure(bool el2_unused) 298 { 299 #if IMAGE_BL31 300 #if ENABLE_SPE_FOR_LOWER_ELS 301 spe_enable(el2_unused); 302 #endif 303 304 #if ENABLE_AMU 305 amu_enable(el2_unused); 306 #endif 307 308 #if ENABLE_SVE_FOR_NS 309 sve_enable(el2_unused); 310 #endif 311 312 #if ENABLE_MPAM_FOR_LOWER_ELS 313 mpam_enable(el2_unused); 314 #endif 315 #endif 316 } 317 318 /******************************************************************************* 319 * The following function initializes the cpu_context for a CPU specified by 320 * its `cpu_idx` for first use, and sets the initial entrypoint state as 321 * specified by the entry_point_info structure. 322 ******************************************************************************/ 323 void cm_init_context_by_index(unsigned int cpu_idx, 324 const entry_point_info_t *ep) 325 { 326 cpu_context_t *ctx; 327 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 328 cm_setup_context(ctx, ep); 329 } 330 331 /******************************************************************************* 332 * The following function initializes the cpu_context for the current CPU 333 * for first use, and sets the initial entrypoint state as specified by the 334 * entry_point_info structure. 335 ******************************************************************************/ 336 void cm_init_my_context(const entry_point_info_t *ep) 337 { 338 cpu_context_t *ctx; 339 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 340 cm_setup_context(ctx, ep); 341 } 342 343 /******************************************************************************* 344 * Prepare the CPU system registers for first entry into secure or normal world 345 * 346 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 347 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 348 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 349 * For all entries, the EL1 registers are initialized from the cpu_context 350 ******************************************************************************/ 351 void cm_prepare_el3_exit(uint32_t security_state) 352 { 353 u_register_t sctlr_elx, scr_el3, mdcr_el2; 354 cpu_context_t *ctx = cm_get_context(security_state); 355 bool el2_unused = false; 356 uint64_t hcr_el2 = 0U; 357 358 assert(ctx != NULL); 359 360 if (security_state == NON_SECURE) { 361 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 362 CTX_SCR_EL3); 363 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 364 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 365 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 366 CTX_SCTLR_EL1); 367 sctlr_elx &= SCTLR_EE_BIT; 368 sctlr_elx |= SCTLR_EL2_RES1; 369 #if ERRATA_A75_764081 370 /* 371 * If workaround of errata 764081 for Cortex-A75 is used 372 * then set SCTLR_EL2.IESB to enable Implicit Error 373 * Synchronization Barrier. 374 */ 375 sctlr_elx |= SCTLR_IESB_BIT; 376 #endif 377 write_sctlr_el2(sctlr_elx); 378 } else if (el_implemented(2) != EL_IMPL_NONE) { 379 el2_unused = true; 380 381 /* 382 * EL2 present but unused, need to disable safely. 383 * SCTLR_EL2 can be ignored in this case. 384 * 385 * Set EL2 register width appropriately: Set HCR_EL2 386 * field to match SCR_EL3.RW. 387 */ 388 if ((scr_el3 & SCR_RW_BIT) != 0U) 389 hcr_el2 |= HCR_RW_BIT; 390 391 /* 392 * For Armv8.3 pointer authentication feature, disable 393 * traps to EL2 when accessing key registers or using 394 * pointer authentication instructions from lower ELs. 395 */ 396 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 397 398 write_hcr_el2(hcr_el2); 399 400 /* 401 * Initialise CPTR_EL2 setting all fields rather than 402 * relying on the hw. All fields have architecturally 403 * UNKNOWN reset values. 404 * 405 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 406 * accesses to the CPACR_EL1 or CPACR from both 407 * Execution states do not trap to EL2. 408 * 409 * CPTR_EL2.TTA: Set to zero so that Non-secure System 410 * register accesses to the trace registers from both 411 * Execution states do not trap to EL2. 412 * 413 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 414 * to SIMD and floating-point functionality from both 415 * Execution states do not trap to EL2. 416 */ 417 write_cptr_el2(CPTR_EL2_RESET_VAL & 418 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 419 | CPTR_EL2_TFP_BIT)); 420 421 /* 422 * Initialise CNTHCTL_EL2. All fields are 423 * architecturally UNKNOWN on reset and are set to zero 424 * except for field(s) listed below. 425 * 426 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 427 * Hyp mode of Non-secure EL0 and EL1 accesses to the 428 * physical timer registers. 429 * 430 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 431 * Hyp mode of Non-secure EL0 and EL1 accesses to the 432 * physical counter registers. 433 */ 434 write_cnthctl_el2(CNTHCTL_RESET_VAL | 435 EL1PCEN_BIT | EL1PCTEN_BIT); 436 437 /* 438 * Initialise CNTVOFF_EL2 to zero as it resets to an 439 * architecturally UNKNOWN value. 440 */ 441 write_cntvoff_el2(0); 442 443 /* 444 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 445 * MPIDR_EL1 respectively. 446 */ 447 write_vpidr_el2(read_midr_el1()); 448 write_vmpidr_el2(read_mpidr_el1()); 449 450 /* 451 * Initialise VTTBR_EL2. All fields are architecturally 452 * UNKNOWN on reset. 453 * 454 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 455 * 2 address translation is disabled, cache maintenance 456 * operations depend on the VMID. 457 * 458 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 459 * translation is disabled. 460 */ 461 write_vttbr_el2(VTTBR_RESET_VAL & 462 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 463 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 464 465 /* 466 * Initialise MDCR_EL2, setting all fields rather than 467 * relying on hw. Some fields are architecturally 468 * UNKNOWN on reset. 469 * 470 * MDCR_EL2.HLP: Set to one so that event counter 471 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 472 * occurs on the increment that changes 473 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 474 * implemented. This bit is RES0 in versions of the 475 * architecture earlier than ARMv8.5, setting it to 1 476 * doesn't have any effect on them. 477 * 478 * MDCR_EL2.TTRF: Set to zero so that access to Trace 479 * Filter Control register TRFCR_EL1 at EL1 is not 480 * trapped to EL2. This bit is RES0 in versions of 481 * the architecture earlier than ARMv8.4. 482 * 483 * MDCR_EL2.HPMD: Set to one so that event counting is 484 * prohibited at EL2. This bit is RES0 in versions of 485 * the architecture earlier than ARMv8.1, setting it 486 * to 1 doesn't have any effect on them. 487 * 488 * MDCR_EL2.TPMS: Set to zero so that accesses to 489 * Statistical Profiling control registers from EL1 490 * do not trap to EL2. This bit is RES0 when SPE is 491 * not implemented. 492 * 493 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 494 * EL1 System register accesses to the Debug ROM 495 * registers are not trapped to EL2. 496 * 497 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 498 * System register accesses to the powerdown debug 499 * registers are not trapped to EL2. 500 * 501 * MDCR_EL2.TDA: Set to zero so that System register 502 * accesses to the debug registers do not trap to EL2. 503 * 504 * MDCR_EL2.TDE: Set to zero so that debug exceptions 505 * are not routed to EL2. 506 * 507 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 508 * Monitors. 509 * 510 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 511 * EL1 accesses to all Performance Monitors registers 512 * are not trapped to EL2. 513 * 514 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 515 * and EL1 accesses to the PMCR_EL0 or PMCR are not 516 * trapped to EL2. 517 * 518 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 519 * architecturally-defined reset value. 520 */ 521 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 522 MDCR_EL2_HPMD) | 523 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 524 >> PMCR_EL0_N_SHIFT)) & 525 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 526 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 527 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 528 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 529 MDCR_EL2_TPMCR_BIT); 530 531 write_mdcr_el2(mdcr_el2); 532 533 /* 534 * Initialise HSTR_EL2. All fields are architecturally 535 * UNKNOWN on reset. 536 * 537 * HSTR_EL2.T<n>: Set all these fields to zero so that 538 * Non-secure EL0 or EL1 accesses to System registers 539 * do not trap to EL2. 540 */ 541 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 542 /* 543 * Initialise CNTHP_CTL_EL2. All fields are 544 * architecturally UNKNOWN on reset. 545 * 546 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 547 * physical timer and prevent timer interrupts. 548 */ 549 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 550 ~(CNTHP_CTL_ENABLE_BIT)); 551 } 552 enable_extensions_nonsecure(el2_unused); 553 } 554 555 cm_el1_sysregs_context_restore(security_state); 556 cm_set_next_eret_context(security_state); 557 } 558 559 #if CTX_INCLUDE_EL2_REGS 560 /******************************************************************************* 561 * Save EL2 sysreg context 562 ******************************************************************************/ 563 void cm_el2_sysregs_context_save(uint32_t security_state) 564 { 565 u_register_t scr_el3 = read_scr(); 566 567 /* 568 * Always save the non-secure EL2 context, only save the 569 * S-EL2 context if S-EL2 is enabled. 570 */ 571 if ((security_state == NON_SECURE) || 572 ((scr_el3 & SCR_EEL2_BIT) != 0U)) { 573 cpu_context_t *ctx; 574 575 ctx = cm_get_context(security_state); 576 assert(ctx != NULL); 577 578 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 579 } 580 } 581 582 /******************************************************************************* 583 * Restore EL2 sysreg context 584 ******************************************************************************/ 585 void cm_el2_sysregs_context_restore(uint32_t security_state) 586 { 587 u_register_t scr_el3 = read_scr(); 588 589 /* 590 * Always restore the non-secure EL2 context, only restore the 591 * S-EL2 context if S-EL2 is enabled. 592 */ 593 if ((security_state == NON_SECURE) || 594 ((scr_el3 & SCR_EEL2_BIT) != 0U)) { 595 cpu_context_t *ctx; 596 597 ctx = cm_get_context(security_state); 598 assert(ctx != NULL); 599 600 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 601 } 602 } 603 #endif /* CTX_INCLUDE_EL2_REGS */ 604 605 /******************************************************************************* 606 * The next four functions are used by runtime services to save and restore 607 * EL1 context on the 'cpu_context' structure for the specified security 608 * state. 609 ******************************************************************************/ 610 void cm_el1_sysregs_context_save(uint32_t security_state) 611 { 612 cpu_context_t *ctx; 613 614 ctx = cm_get_context(security_state); 615 assert(ctx != NULL); 616 617 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 618 619 #if IMAGE_BL31 620 if (security_state == SECURE) 621 PUBLISH_EVENT(cm_exited_secure_world); 622 else 623 PUBLISH_EVENT(cm_exited_normal_world); 624 #endif 625 } 626 627 void cm_el1_sysregs_context_restore(uint32_t security_state) 628 { 629 cpu_context_t *ctx; 630 631 ctx = cm_get_context(security_state); 632 assert(ctx != NULL); 633 634 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 635 636 #if IMAGE_BL31 637 if (security_state == SECURE) 638 PUBLISH_EVENT(cm_entering_secure_world); 639 else 640 PUBLISH_EVENT(cm_entering_normal_world); 641 #endif 642 } 643 644 /******************************************************************************* 645 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 646 * given security state with the given entrypoint 647 ******************************************************************************/ 648 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 649 { 650 cpu_context_t *ctx; 651 el3_state_t *state; 652 653 ctx = cm_get_context(security_state); 654 assert(ctx != NULL); 655 656 /* Populate EL3 state so that ERET jumps to the correct entry */ 657 state = get_el3state_ctx(ctx); 658 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 659 } 660 661 /******************************************************************************* 662 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 663 * pertaining to the given security state 664 ******************************************************************************/ 665 void cm_set_elr_spsr_el3(uint32_t security_state, 666 uintptr_t entrypoint, uint32_t spsr) 667 { 668 cpu_context_t *ctx; 669 el3_state_t *state; 670 671 ctx = cm_get_context(security_state); 672 assert(ctx != NULL); 673 674 /* Populate EL3 state so that ERET jumps to the correct entry */ 675 state = get_el3state_ctx(ctx); 676 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 677 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 678 } 679 680 /******************************************************************************* 681 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 682 * pertaining to the given security state using the value and bit position 683 * specified in the parameters. It preserves all other bits. 684 ******************************************************************************/ 685 void cm_write_scr_el3_bit(uint32_t security_state, 686 uint32_t bit_pos, 687 uint32_t value) 688 { 689 cpu_context_t *ctx; 690 el3_state_t *state; 691 u_register_t scr_el3; 692 693 ctx = cm_get_context(security_state); 694 assert(ctx != NULL); 695 696 /* Ensure that the bit position is a valid one */ 697 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 698 699 /* Ensure that the 'value' is only a bit wide */ 700 assert(value <= 1U); 701 702 /* 703 * Get the SCR_EL3 value from the cpu context, clear the desired bit 704 * and set it to its new value. 705 */ 706 state = get_el3state_ctx(ctx); 707 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 708 scr_el3 &= ~(1U << bit_pos); 709 scr_el3 |= (u_register_t)value << bit_pos; 710 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 711 } 712 713 /******************************************************************************* 714 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 715 * given security state. 716 ******************************************************************************/ 717 u_register_t cm_get_scr_el3(uint32_t security_state) 718 { 719 cpu_context_t *ctx; 720 el3_state_t *state; 721 722 ctx = cm_get_context(security_state); 723 assert(ctx != NULL); 724 725 /* Populate EL3 state so that ERET jumps to the correct entry */ 726 state = get_el3state_ctx(ctx); 727 return read_ctx_reg(state, CTX_SCR_EL3); 728 } 729 730 /******************************************************************************* 731 * This function is used to program the context that's used for exception 732 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 733 * the required security state 734 ******************************************************************************/ 735 void cm_set_next_eret_context(uint32_t security_state) 736 { 737 cpu_context_t *ctx; 738 739 ctx = cm_get_context(security_state); 740 assert(ctx != NULL); 741 742 cm_set_next_context(ctx); 743 } 744