fix(cpus): workaround for Cortex-X2 erratum 3324338

Cortex-X2 erratum 3324338 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0 and r2p1, and is still open.

This errata can be avoided b

fix(cpus): workaround for Cortex-X2 erratum 3324338

Cortex-X2 erratum 3324338 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0 and r2p1, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100

Change-Id: Ibbe55a55bd6cf5e159dab92a78ecb55c5a4d7eb1
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 3324338

Cortex-A710 erratum 3324338 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0 and r2p1, and is still open.

This errata can be avoid

fix(cpus): workaround for Cortex-A710 erratum 3324338

Cortex-A710 erratum 3324338 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0 and r2p1, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101

Change-Id: I9325f3715f4fa17bfb7ded9d5c69c59645f65b27
Signed-off-by: John Powell <john.powell@arm.com>

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Merge changes from topic "xl/c1ultra-errata" into integration

* changes:
fix(cpus): workaround for C1-Ultra erratum 3324333
fix(cpus): workaround for C1-Ultra erratum 3658374
fix(cpus): workar

Merge changes from topic "xl/c1ultra-errata" into integration

* changes:
fix(cpus): workaround for C1-Ultra erratum 3324333
fix(cpus): workaround for C1-Ultra erratum 3658374
fix(cpus): workaround for C1-Ultra erratum 3926381
fix(cpus): workaround for C1-Ultra erratum 4102704
fix(cpus): workaround for C1-Ultra erratum 3865171
fix(cpus): workaround for C1-Ultra erratum 3815514
fix(cpus): workaround for C1-Ultra erratum 3705939
fix(cpus): workaround for C1-Ultra erratum 3684152
fix(cpus): workaround for C1-Ultra erratum 3651221
fix(cpus): workaround for C1-Ultra erratum 3502731

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fix(cpus): workaround for C1-Ultra erratum 3324333

C1-Ultra erratum 3324333 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation

fix(cpus): workaround for C1-Ultra erratum 3324333

C1-Ultra erratum 3324333 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I203238cbb8561cee683c22a6dbe4742702f82763
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3658374

C1-Ultra erratum 3658374 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

This is workaround for accessing ICH_VMCR_EL2.

fix(cpus): workaround for C1-Ultra erratum 3658374

C1-Ultra erratum 3658374 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

This is workaround for accessing ICH_VMCR_EL2.
When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0)
and then subsequently read in Non-secure state (SCR_EL3.NS==1), a
wrong value might be returned. The same issue exists in the opposite way.

Adding workaround in EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored. For example, EL3 software should set
SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for
Non-secure(or Realm) state. EL3 software should clear
SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for
Secure state.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I945477b2432fefc04049e8576b66cea0cbffb03a
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3926381

C1-Ultra erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is open.

This errata can be avoided by executing an implementation
s

fix(cpus): workaround for C1-Ultra erratum 3926381

C1-Ultra erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is open.

This errata can be avoided by executing an implementation
specific instruction patching sequence as soon as possible
after boot. After it is applied, the code only converts
WFx and WFxT instructions to NOP when PSTATE.SM=1 or when
PSTATE.ZA=1.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I2e0f3a715670aaac116c7d3c5f5992ff7ab05ba3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 4102704

C1-Ultra erratum 4102704 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 4102704

C1-Ultra erratum 4102704 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR4_EL1[23] to 1.
Overall expected performance degradation is ~1.36%, but
isolated benchmark components might see higher or lower impact.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I414df1af006484dd120f928bd8fdf9e6f4a513fd
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3865171

C1-Ultra erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3865171

C1-Ultra erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I8bfe15fdd1d028d43d8730e7d43f72c9f15810d7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3815514

C1-Ultra erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3815514

C1-Ultra erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR5_EL1[13] to 1.
Setting CPUACTLR5_EL1[13] to 1 is expected to result in a small
performance degradation for workloads that use MTE. The
degradation might be approximately 1.6% when using MTE imprecise
mode or 0.9% for MTE precise mode.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I2d6b0ee282010139d8dc406800f2738b39113957
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3705939

C1-Ultra erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3705939

C1-Ultra erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR_EL1[48] to 1,
which disables a RDFFR optimization. Setting this bit has
negligible impact on GB6/SPECint performance, but will have an
impact on SVE RDFFR performance.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I88343236af86a9bb0b0ce644296d5929d7b956d1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3684152

C1-Ultra erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL

fix(cpus): workaround for C1-Ultra erratum 3684152

C1-Ultra erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL1[60:58] to
3'b001, which has a small perf impact.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I3747b2a99785602bd2a3bddac3a69a934e7f4b37
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3651221

C1-Ultra erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by disabling the affec

fix(cpus): workaround for C1-Ultra erratum 3651221

C1-Ultra erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by disabling the affected prefetcher
by setting CPUACTLR6_EL1[41] to 1.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I0498a81a62bbea666b503cdd5a6dbcae7eab0dce
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3502731

C1-Ultra erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3502731

C1-Ultra erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR4[23] to 1,
which will disable Memory Renaming optimization.
The performance impact of setting this chicken bit is about
0.82% in GB6.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: Iaf832b66aeed937edbb1e9be29de41b0f2b5d70c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): register ARCH_WORKAROUND_3 for Neoverse V2

Neoverse V2 never registered ARCH_WORKAROUND_3 in the errata
framework, causing SMCCC_ARCH_WORKAROUND_3 discovery to always return 1.

The SMCCC

fix(cpus): register ARCH_WORKAROUND_3 for Neoverse V2

Neoverse V2 never registered ARCH_WORKAROUND_3 in the errata
framework, causing SMCCC_ARCH_WORKAROUND_3 discovery to always return 1.

The SMCCC specification language prior to 1.6 G EAC1 was ambiguous
regarding the meaning of return value 1, leading to inconsistent
interpretations by callers. This ambiguity has since been resolved in
1.6 G EAC1 release, which clarifies that a return value of 1 does *not*
mean the core is unaffected and that callers must independently
determine the erratum status.

While TF-A has always followed this interpretation, some consumers may
still treat a return value of 1 as “not affected”, potentially leading
to security issues if the OS does not apply its own workaround.

Firmware originally returned 1 on V2 to avoid unnecessary WA3 SMC calls
on every syscall return, since this would negatively impact performance.
For Cortex-A57/72/73/75, SMCCC_ARCH_WORKAROUND_3 returns 0, while for
many newer cores (A76, A78, X2, A715, Neoverse V1/V2) the return value
is 1 because a local OS mitigation is available and calling into
firmware is not required.

Because this interface was expected to age out, we do not want to change
the status quo for other CPUs. This patch confines the fix to Neoverse
V2 only by adding the missing ARCH_WORKAROUND_3 registration, allowing
affected V2 revisions to return 0 as intended.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I8c08c26e0b7c268772d75d36d759564a7d67cd76

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Merge "fix(psci): gate suspend end_pwrlvl override in OS_INIT mode at runtime" into integration

fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which v

fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which verified this feature.

BREAKING CHANGE: platforms can no longer retrieve the host ROTPK from
the RSE as these are no longer provisioned.

Change-Id: I2c852855e53c36e77f639f17f4c181290d95ccff
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've gained
lots of quality of life features that allow for better feature
enablement. This patch converts USE_SPINLOCK_CAS to tri-state and adds
it to FEATURE_DETECTION to align with all other features.

Instead of introducing the assembly checking for tri-state, this patch
translates all locking routines to C inline assembly and uses the
standard C helpers. The main benefit is that this gives greater
visibility to the compiler about what the functions are doing and lets
it optimise better. Namely, it is able to allocate registers itself and
inline the functions when LTO is enabled.

An unsuccessful attempt was made to use the instructions directly and
have even flow control in C. This, however, made code very complicated
and less efficient in the tight loops of the spinlock.

The last use of ARM_ARCH_AT_LEAST goes away with this change and so this
macro is removed. It has now been fully superseded by the FEAT_STATE
framework.

This change exposes a limitation - RME_GPT_BITLOCK_BLOCK requires
USE_SPINLOCK_CAS. This patch does not address this in any way but makes
the relationship explicit.

Change-Id: I580081549aceded2dca3e0f4564ee7510a7e56ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(cpus): fix C1 Pro powerdown abandon behavior" into integration

Merge "refactor(cm): reduce conditional compilation" into integration

fix(cpus): fix C1 Pro powerdown abandon behavior

This change restores a toggle to IMP_CPUPWRCTLR_EL1.CORE_PWRDN_EN
that was accidentally changed to a bitset in [1]. Without this change, a
powerdown

fix(cpus): fix C1 Pro powerdown abandon behavior

This change restores a toggle to IMP_CPUPWRCTLR_EL1.CORE_PWRDN_EN
that was accidentally changed to a bitset in [1]. Without this change, a
powerdown abandon followed by a non-powerdown CPU_SUSPEND will
incorrectly trigger a power down.

This change is similar to [2].

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/42920/
[2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/43236/

Change-Id: Ife86bd2b5bac4829e695a1aa180926dfad19a470
Signed-off-by: Jim Ray <jimray@google.com>

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fix(cpufeat): enable FEAT_FGWTE3 after FEAT_CPA

FEAT_CPA needs to write SCTLR2_EL3 which will be forbidden after
initialising FEAT_FGWTE3. Correct the order.

Change-Id: I3a0554d2a73f773b3ad672eb1e4

fix(cpufeat): enable FEAT_FGWTE3 after FEAT_CPA

FEAT_CPA needs to write SCTLR2_EL3 which will be forbidden after
initialising FEAT_FGWTE3. Correct the order.

Change-Id: I3a0554d2a73f773b3ad672eb1e4b0db0171d38bd
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(cm): reduce conditional compilation

Context debug needs to switch between EL1 and EL2 context but it can
re-use its variables and function calls with a bit of clever naming.
Unify them to r

refactor(cm): reduce conditional compilation

Context debug needs to switch between EL1 and EL2 context but it can
re-use its variables and function calls with a bit of clever naming.
Unify them to reduce #if-s.

Change-Id: I401667c4bc07938c99163c035dbed1101d986859
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(psci): gate suspend end_pwrlvl override in OS_INIT mode at runtime

This change adds an additional runtime gate to override the
suspend power level. The build-time check already existed, but
it's

fix(psci): gate suspend end_pwrlvl override in OS_INIT mode at runtime

This change adds an additional runtime gate to override the
suspend power level. The build-time check already existed, but
it's possible that PSCI might not be in OS_INIT mode. In that
case, no override should occur.

Change-Id: I695cef3f4ddd8957360fe056c8715c170df6f1f4
Signed-off-by: Bill Peckham <bpeckham@google.com>
Signed-off-by: Karunatharaka Bodduluri <karunatharaka@google.com>

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fix(security): update Neoverse-V2 fix version for CVE-2024-7881

This patch updates the Neoverse-V2 revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3696445 [2] applies.
The erratum applies

fix(security): update Neoverse-V2 fix version for CVE-2024-7881

This patch updates the Neoverse-V2 revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3696445 [2] applies.
The erratum applies to r0p0, r0p1, r0p2 and is still open.

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-2332927/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I1ae196fa8ce4579524faba4916f631e7c4db358b

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fix(security): update Cortex-X3 fix version for CVE-2024-7881

This patch updates the Cortex-X3 revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3692984 [2] applies.
The erratum applies to r

fix(security): update Cortex-X3 fix version for CVE-2024-7881

This patch updates the Cortex-X3 revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3692984 [2] applies.
The erratum applies to r0p0, r1p0, r1p1, r1p2 and is still open.

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-2055130/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia1ff75602a0dfa758a223549d92ea87543fa44b6

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