feat(cpu): add support for Hunter CPU

This patch adds the basic CPU library code to support the Hunter CPU
in TF-A. This CPU is based on the Makalu core so that library code
was adapted as the basis

feat(cpu): add support for Hunter CPU

This patch adds the basic CPU library code to support the Hunter CPU
in TF-A. This CPU is based on the Makalu core so that library code
was adapted as the basis for this patch.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I956b2dc0f43da7cec3e015252392e2694363e1b3

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Merge "fix(errata): workaround for Cortex-A710 erratum 2058056" into integration

Merge changes If7dec725,Iedcb84a7,Ife0a4bec into integration

* changes:
errata: workaround for Cortex-A78 erratum 2132060
errata: workaround for Neoverse-V1 erratum 2108267
fix(errata): workar

Merge changes If7dec725,Iedcb84a7,Ife0a4bec into integration

* changes:
errata: workaround for Cortex-A78 erratum 2132060
errata: workaround for Neoverse-V1 erratum 2108267
fix(errata): workaround for Neoverse-N2 erratum 2138953

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errata: workaround for Cortex-A78 erratum 2132060

Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to wr

errata: workaround for Cortex-A78 erratum 2132060

Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to write the value 2'b11 to the PF_MODE bits
in the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: If7dec72578633d37d110d103099e406c3a970ff7

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errata: workaround for Neoverse-V1 erratum 2108267

Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write

errata: workaround for Neoverse-V1 erratum 2108267

Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write the value 2'b11 to the PF_MODE bits in
the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Iedcb84a7ad34af7083116818f49d7296f7d9bf94

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fix(errata): workaround for Neoverse-N2 erratum 2138953

Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'

fix(errata): workaround for Neoverse-N2 erratum 2138953

Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Ife0a4bece7ccf83cc99c1d5f5b5a43084bb69d64

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fix(errata): workaround for Cortex-A710 erratum 2058056

Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write th

fix(errata): workaround for Cortex-A710 erratum 2058056

Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I7ce5181b3b469fbbb16501e633116e119b8bf4f1

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feat(cpu): add support for Hayes CPU

This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use he

feat(cpu): add support for Hayes CPU

This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use here.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If0e0070cfa77fee8f6eebfee13d3c4f209ad84fc

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errata: workaround for Cortex-A710 erratum 2083908

Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.

S

errata: workaround for Cortex-A710 erratum 2083908

Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I876d26a7ac6ab0d7c567a9ec9f34fc0f952589d8

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Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2138956
errata: workaround for Neoverse N2 erratum 2189731
errata: workaround for Cort

Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2138956
errata: workaround for Neoverse N2 erratum 2189731
errata: workaround for Cortex-A710 erratum 2017096
errata: workaround for Cortex-A710 erratum 2055002

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errata: workaround for Neoverse N2 erratum 2138956

Neoverse N2 erratum 2138956 is a Cat B erratum that applies to
revision r0p0 and is still open. This erratum can be avoided by
inserting a sequence

errata: workaround for Neoverse N2 erratum 2138956

Neoverse N2 erratum 2138956 is a Cat B erratum that applies to
revision r0p0 and is still open. This erratum can be avoided by
inserting a sequence of 16 DMB ST instructions prior to WFI or WFE.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I1aac87b3075992f875451e4767b21857f596d0b2

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errata: workaround for Neoverse N2 erratum 2189731

Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 whi

errata: workaround for Neoverse N2 erratum 2189731

Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to
invalidate the hardware prefetcher state trained from any EL.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iddc6a59adf9fa3cab560c46f2133e1f5a8b3ad03

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errata: workaround for Cortex-A710 erratum 2017096

Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1

errata: workaround for Cortex-A710 erratum 2017096

Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3

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errata: workaround for Cortex-A710 erratum 2055002

Cortex-A710 erratum 2055002 is a Cat B erratum that applies to
revisions r1p0 & r2p0 and is still open. The workaround is to
set CPUACTLR_EL1[46] t

errata: workaround for Cortex-A710 erratum 2055002

Cortex-A710 erratum 2055002 is a Cat B erratum that applies to
revisions r1p0 & r2p0 and is still open. The workaround is to
set CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r1p0 & r2p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I67be1dce53c4651167d8cee33c116e73b9dafe81

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Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2025414
errata: workaround for Neoverse N2 erratum 2067956

Merge "errata: workaround for Cortex-A78 errata 1952683" into integration

errata: workaround for Neoverse N2 erratum 2025414

Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which

errata: workaround for Neoverse N2 erratum 2025414

Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a

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errata: workaround for Neoverse N2 erratum 2067956

Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force

errata: workaround for Neoverse N2 erratum 2067956

Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r0p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21

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Merge "errata: workaround for Neoverse-N2 errata 2002655" into integration

Merge changes I1e8c2bc3,I9bcff306 into integration

* changes:
errata: workaround for Cortex-A710 errata 2081180
errata: workaround for Cortex-A710 errata 1987031

errata: workaround for Neoverse-N2 errata 2002655

Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of
the Neoverse-N2 processor core, and it is still open.

Neoverse-N2 SDEN: https://d

errata: workaround for Neoverse-N2 errata 2002655

Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of
the Neoverse-N2 processor core, and it is still open.

Neoverse-N2 SDEN: https://documentation-service.arm.com/static/61098b4e3d73a34b640e32c9?token=

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1380418146807527abd97cdd4918265949ba5c01

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Merge "feat(cpus): workaround for Cortex A78 AE erratum 1941500" into integration

errata: workaround for Cortex-A710 errata 2081180

Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN:

errata: workaround for Cortex-A710 errata 2081180

Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542

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Merge "cpu: add support for Demeter CPU" into integration

errata: workaround for Cortex-A710 errata 1987031

Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN:

errata: workaround for Cortex-A710 errata 1987031

Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://documentation-service.arm.com/static/61099dc59ebe3a7dbd3a8a88?token=

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I9bcff306f82328ad5a0f6e9836020d23c07f7179

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