Merge "fix(nuvoton): prevent changing clock frequency" into integration

Merge changes from topic "mte_fixes" into integration

* changes:
build(changelog): move mte to mte2
refactor(mte): remove mte, mte_perm

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Sign

chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(nuvoton): prevent changing clock frequency

prevent changing clock frequency already set in BootBlock based on PLL value

Change-Id: I8b4b53448cc8e703fd88ad6166f85a4fe3ba9e46
Signed-off-by: Marga

fix(nuvoton): prevent changing clock frequency

prevent changing clock frequency already set in BootBlock based on PLL value

Change-Id: I8b4b53448cc8e703fd88ad6166f85a4fe3ba9e46
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>

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Merge "fix(cpus): workaround for Cortex-A720 erratum 2926083" into integration

Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPID

Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPIDR
refactor(rpi): move register definitions out of rpi_hw.h
refactor(rpi): add platform macro for the crash UART base address
refactor(rpi): split out console registration logic
refactor(rpi): move more platform-specific code into common

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fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE

fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE (Statistical Profiling Extension) is implemented
and enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is "implemented and enabled".

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I30182c3893416af65b55fca9a913cb4512430434
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(nuvoton): gfx frame buffer memory corruption during secondary boot" into integration

Merge "fix(cpus): workaround for Cortex-A720 erratum 2940794" into integration

fix(cpus): workaround for Cortex-A720 erratum 2940794

Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[37] of

fix(cpus): workaround for Cortex-A720 erratum 2940794

Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[37] of the CPUACTLR2_EL1 to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I1488802e0ec7c16349c9633bb45de4d0e1faa9ad
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

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feat(st-clock): add function to control MCU subsystem

Add a new function to control the MCU subsystem
security state.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I070eec06fc93a

feat(st-clock): add function to control MCU subsystem

Add a new function to control the MCU subsystem
security state.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I070eec06fc93a1214227f25a6a4f1c40c66c86b0

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Merge "refactor(guid-partition): list.entry_count to unsigned int" into integration

fix(nuvoton): gfx frame buffer memory corruption during secondary boot

gfx frame buffer memory corruption because of moving TF-A to DDR

Change-Id: I6f1e0c8d048273b8047497adec631160aaf393d6
Signed-o

fix(nuvoton): gfx frame buffer memory corruption during secondary boot

gfx frame buffer memory corruption because of moving TF-A to DDR

Change-Id: I6f1e0c8d048273b8047497adec631160aaf393d6
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>

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refactor(guid-partition): list.entry_count to unsigned int

Change list.entry_count to unsigned int to align with header.list_num,
removing the need for casting.

Change-Id: Id4259d9e841c8d34fe23fb74

refactor(guid-partition): list.entry_count to unsigned int

Change list.entry_count to unsigned int to align with header.list_num,
removing the need for casting.

Change-Id: Id4259d9e841c8d34fe23fb74a7c627f2a643cbf2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "refactor(mbedtls): remove mbedtls 2.x support" into integration

Merge "refactor(sdei): use common create_spsr() in SDEI library" into integration

refactor(mbedtls): remove mbedtls 2.x support

Deprecation notice was sent to the community and no objection was
raised, so removing mbedtls 2.x support.

Change-Id: Id3eb98b55692df98aabe6a7c5a5ec910

refactor(mbedtls): remove mbedtls 2.x support

Deprecation notice was sent to the community and no objection was
raised, so removing mbedtls 2.x support.

Change-Id: Id3eb98b55692df98aabe6a7c5a5ec910222c8abd
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(S

fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(Statistical Profiling Extension) is enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is enabled, ENABLE_SPE_FOR_NS=1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Iaeb258c8b0a92e93d70b7dad6ba59d1056aeb135
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(rpi): move register definitions out of rpi_hw.h

Change-Id: I2bd48441359468efb9e94fd2fffb079683f7a7fd
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

Merge "refactor(cm): couple el2 registers with dependent feature flags" into integration

Merge "fix(misra): fix MISRA defects" into integration

Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level

Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level for region validity
feat(tc): add dummy TRNG support to be able to boot pVMs
feat(tc): get the parent component provided DPE context_handle
feat(tc): share DPE context handle with child component
feat(tc): add DPE context handle node to device tree
feat(tc): add DPE backend to the measured boot framework
feat(auth): add explicit entries for key OIDs
feat(dice): add DPE driver to measured boot
feat(dice): add client API for DICE Protection Environment
feat(dice): add QCBOR library as a dependency of DPE
feat(dice): add typedefs from the Open DICE repo
docs(changelog): add 'dice' scope
refactor(tc): align image identifier string macros
refactor(fvp): align image identifier string macros
refactor(imx8m): align image identifier string macros
refactor(qemu): align image identifier string macros
fix(measured-boot): add missing image identifier string
refactor(measured-boot): move metadata size macros to a common header
refactor(measured-boot): move image identifier strings to a common header

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refactor(sdei): use common create_spsr() in SDEI library

The current SPSR updation code as part of the SDEI interrupt handler
code is outdated. This patch replaces the legacy code with a call to
an

refactor(sdei): use common create_spsr() in SDEI library

The current SPSR updation code as part of the SDEI interrupt handler
code is outdated. This patch replaces the legacy code with a call to
an up-to-date create_spsr()

Change-Id: I1f5fdd41dd14f4b09601310fe881fa3783d7f505
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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fix(misra): fix MISRA defects

This patch resolves the MISRA issues reported in mailing list.
It addresses the following MISRA Rules violations - Rule 15.7 and
Rule 2.4.

* As per Rule 15.7, All if..

fix(misra): fix MISRA defects

This patch resolves the MISRA issues reported in mailing list.
It addresses the following MISRA Rules violations - Rule 15.7 and
Rule 2.4.

* As per Rule 15.7, All if.. else if constructs should be terminated
with an else statement and hence the conditional block
has been changed to switch..case. Updated get_el_str() to include
all EL cases.

* As per Rule 2.4, A project should not contain unused tag declarations,
hence intr_type_desc tag is removed.

* bl31_lib_init is only used in translation unit and hence it's
declaration is removed from bl31.h and the definition is made static to
maintain visibility.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ica1d3041566baf51befcad5fd3714189117ba193

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