| 9be5ca7a | 10-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "arm: Fix current RECLAIM_INIT_CODE behavior" into integration |
| a71c59d5 | 16-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
arm: Fix current RECLAIM_INIT_CODE behavior
Previously the .init section was created even when the reclaim flag was
manually set to 0.
Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8
Signed-of
arm: Fix current RECLAIM_INIT_CODE behavior
Previously the .init section was created even when the reclaim flag was
manually set to 0.
Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Zelalem Aweke <zelalem.aweke@arm.com>
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|
| db3ae853 | 26-Nov-2019 |
Artsem Artsemenka <artsem.artsemenka@arm.com> |
S-EL2 Support: Check for AArch64
Check that entry point information requesting S-EL2
has AArch64 as an execution state during context setup.
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.
S-EL2 Support: Check for AArch64
Check that entry point information requesting S-EL2
has AArch64 as an execution state during context setup.
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I447263692fed6e55c1b076913e6eb73b1ea735b7
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|
| 0376e7c4 | 11-Oct-2019 |
Achin Gupta <achin.gupta@arm.com> |
Add support for enabling S-EL2
This patch adds support for enabling S-EL2 if this EL is specified in the entry
point information being used to initialise a secure context. It is the caller's
respons
Add support for enabling S-EL2
This patch adds support for enabling S-EL2 if this EL is specified in the entry
point information being used to initialise a secure context. It is the caller's
responsibility to check if S-EL2 is available on the system before requesting
this EL through the entry point information.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Change-Id: I2752964f078ab528b2e80de71c7d2f35e60569e1
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|
| ade3f5df | 06-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "bs/libc" into integration
* changes:
libc: Consolidate the size_t and NULL definitions
libc: Consolidate unified definitions
libc: Unify intmax_t and uintmax_t on AAr
Merge changes from topic "bs/libc" into integration
* changes:
libc: Consolidate the size_t and NULL definitions
libc: Consolidate unified definitions
libc: Unify intmax_t and uintmax_t on AArch32/64
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|
| d45c323a | 25-Oct-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
libc: Consolidate the size_t and NULL definitions
Consolidate the definition of size_t to one header per AArch, and
the definition of NULL to one header
Signed-off-by: Bence Szépkúti <bence.szepkut
libc: Consolidate the size_t and NULL definitions
Consolidate the definition of size_t to one header per AArch, and
the definition of NULL to one header
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Iecfbad2cf360cfb705ce7aaa981700fd16219b82
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|
| b382ac68 | 25-Oct-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
libc: Consolidate unified definitions
As supporting architectures aside from AArch32 and AArch64 is not a
concern, keeping identical definitions in two places for a large part
of the libc seems coun
libc: Consolidate unified definitions
As supporting architectures aside from AArch32 and AArch64 is not a
concern, keeping identical definitions in two places for a large part
of the libc seems counterproductive
The int128 types were left un-unified as __int128 is not supported by
gcc on AArch32
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Idf08e6fab7e4680d9da62d3c57266ea2d80472cf
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|
| d005cfbf | 25-Oct-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
libc: Unify intmax_t and uintmax_t on AArch32/64
Conceptually, these are supposed to be the largest integers
representable in C, but GCC and Clang define them as long long for
compatibility.
Signed
libc: Unify intmax_t and uintmax_t on AArch32/64
Conceptually, these are supposed to be the largest integers
representable in C, but GCC and Clang define them as long long for
compatibility.
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: I7c0117f3be167342814d260a371889120dcf6576
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|
| e34cc0ce | 10-Nov-2019 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Changes to support updated register usage in SMCCC v1.2
From AArch64 state, arguments are passed in registers W0-W7(X0-X7)
and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls.
From AArch
Changes to support updated register usage in SMCCC v1.2
From AArch64 state, arguments are passed in registers W0-W7(X0-X7)
and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls.
From AArch32 state, arguments are passed in registers R0-R7 and
results are returned in registers R0-R7 for SMC32 calls.
Most of the functions and macros already existed to support using
upto 8 registers for passing/returning parameters/results. Added
few helper macros for SMC calls from AArch32 state.
Link to the specification:
https://developer.arm.com/docs/den0028/c
Change-Id: I87976b42454dc3fc45c8343e9640aa78210e9741
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| 63b96271 | 12-Nov-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "plat/arm: Re-enable PIE when RESET_TO_BL31=1" into integration |
| fcc337cf | 16-Sep-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
gic/gic600: add support for multichip configuration
Add support to configure GIC-600's multichip routing table registers.
Introduce a new gic600 multichip structure in order to support platforms
to
gic/gic600: add support for multichip configuration
Add support to configure GIC-600's multichip routing table registers.
Introduce a new gic600 multichip structure in order to support platforms
to pass their GIC-600 multichip information such as routing table owner,
SPI blocks ownership.
This driver is currently experimental and the driver api may change in
the future.
Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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|
| 133a5c68 | 06-Nov-2019 |
Manish Pandey <manish.pandey2@arm.com> |
plat/arm: Re-enable PIE when RESET_TO_BL31=1
Earlier PIE support was enabled for all arm platforms when
RESET_TO_BL31=1, but later on it was restricted only to FVP with patch
SHA d4580d17 because of
plat/arm: Re-enable PIE when RESET_TO_BL31=1
Earlier PIE support was enabled for all arm platforms when
RESET_TO_BL31=1, but later on it was restricted only to FVP with patch
SHA d4580d17 because of n1sdp platform.
Now it has been verified that PIE does work for n1sdp platform also, so
enabling it again for all arm platforms.
Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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|
| 74c21244 | 11-Oct-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
plat/arm/gicv3: add support for probing multiple GIC Redistributor frames
ARM platform can have a non-contiguous GICR frames. For instance, a
multi socket platform can have two or more GIC Redistrib
plat/arm/gicv3: add support for probing multiple GIC Redistributor frames
ARM platform can have a non-contiguous GICR frames. For instance, a
multi socket platform can have two or more GIC Redistributor frames
which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe`
function to probe all the GICR frames available in the platform.
Introduce `plat_arm_override_gicr_frames` function which platforms can
use to override the default gicr_frames which holds the GICR base
address of the primary cpu.
Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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|
| 89632e6a | 11-Oct-2019 |
Balint Dobszay <balint.dobszay@arm.com> |
Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__
Change-Id: I497072575231730a216220f84a6d349a48eaf5e3
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> |
| 9d811b85 | 08-Oct-2019 |
Yann Gautier <yann.gautier@st.com> |
delay: correct timeout_init_us()
The function has to use read_cntpct_el0() to update the counter, and not
read_cntfrq_el0().
Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7
Signed-off-by: Yann
delay: correct timeout_init_us()
The function has to use read_cntpct_el0() to update the counter, and not
read_cntfrq_el0().
Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| 80003d86 | 07-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Explicitly disable the SPME bit in MDCR_EL3" into integration |
| 25792ce4 | 07-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Neoverse N1 Errata Workaround 1542419" into integration |
| 2a7adf25 | 03-Oct-2019 |
Petre-Ionut Tudor <petre-ionut.tudor@arm.com> |
Explicitly disable the SPME bit in MDCR_EL3
Currently the MDCR_EL3 initialisation implicitly disables
MDCR_EL3.SPME by using mov_imm.
This patch makes the SPME bit more visible by explicitly
disabl
Explicitly disable the SPME bit in MDCR_EL3
Currently the MDCR_EL3 initialisation implicitly disables
MDCR_EL3.SPME by using mov_imm.
This patch makes the SPME bit more visible by explicitly
disabling it and documenting its use in different versions
of the architecture.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I221fdf314f01622f46ac5aa43388f59fa17a29b3
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|
| 80942622 | 20-Aug-2019 |
laurenw-arm <lauren.wehrmeister@arm.com> |
Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instr
Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
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|
| 0711ee5c | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
delay: timeout detection support
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.
timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided mic
delay: timeout detection support
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.
timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided microsecond delay value from current time.
timeout_elapsed(reference) return true/false whether the reference
timeout is elapsed.
Cherry picked from OP-TEE implementation [1].
[1] commit 33d30a74502b ("core: timeout detection support")
Minor:
- Remove stm32mp platform duplicated implementation.
- Add new include in marvell ble.mk
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
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|
| 78f02ae2 | 22-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Introducing support for Cortex-A65AE
Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422
Signed-off-by: Imre Kis <imre.kis@arm.com> |
| 2d35bc13 | 03-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "stm32mp_corrections_w40" into integration
* changes:
gpio: stm32_gpio: do not mix error code types
fdts: stm32mp1: move FDCAN to PLL4_R
mmc: increase delay between AC
Merge changes from topic "stm32mp_corrections_w40" into integration
* changes:
gpio: stm32_gpio: do not mix error code types
fdts: stm32mp1: move FDCAN to PLL4_R
mmc: increase delay between ACMD41 retries
crypto: stm32_hash: align stm32_hash_update() prototype
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|
| 34c4f86a | 03-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Add missing support for BL2_AT_EL3 in XIP memory" into integration |
| 19e2af79 | 02-Oct-2019 |
Yann Gautier <yann.gautier@st.com> |
crypto: stm32_hash: align stm32_hash_update() prototype
Use size_t for length parameter in header file, as in .c file.
Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec
Signed-off-by: Yann Gauti
crypto: stm32_hash: align stm32_hash_update() prototype
Use size_t for length parameter in header file, as in .c file.
Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| 6ad216dc | 18-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Introducing support for Cortex-A65
Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47
Signed-off-by: Imre Kis <imre.kis@arm.com> |