refactor(st-pmic): split initialize_pmic()

print_pmic_info_and_debug() prints the PMIC version ID and displays
regulator information if debug is enabled.
It is under DEBUG flag and called after init

refactor(st-pmic): split initialize_pmic()

print_pmic_info_and_debug() prints the PMIC version ID and displays
regulator information if debug is enabled.
It is under DEBUG flag and called after initialize_pmic() in BL2.

Change-Id: Ib81a625740b7ec6abb49cfca05e44c69efaa4718
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(regulator): add a regulator framework

Add a regulator framework to:
- provide an interface to consumers and drivers,
- connect consumers with drivers,
- handle most of devicetree-parsing,
- han

feat(regulator): add a regulator framework

Add a regulator framework to:
- provide an interface to consumers and drivers,
- connect consumers with drivers,
- handle most of devicetree-parsing,
- handle always-on and boot-on regulators,
- handle min/max voltages,

Change-Id: I23c939fdef2c71a416c44c9de332f70db0d2aa53
Signed-off-by: Pascal Paillet <p.paillet@st.com>

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feat(stpmic1): add new services

Add support for ICC, sink mode, bypass mode,
active discharge and list voltages.
Handle LDO3 sink source mode in a different way to avoid
setting voltage while in sin

feat(stpmic1): add new services

Add support for ICC, sink mode, bypass mode,
active discharge and list voltages.
Handle LDO3 sink source mode in a different way to avoid
setting voltage while in sink source mode.

Change-Id: Ib1b909fd8a153f542917f650e43e24317a570534
Signed-off-by: Pascal Paillet <p.paillet@st.com>

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feat(stpmic1): add USB OTG regulators

Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to
USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are
needed since manipulated durin

feat(stpmic1): add USB OTG regulators

Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to
USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are
needed since manipulated during the suspend/resume power sequence
as per FDT description for stm32mp15x-xxx boards from
STMicroelectronics.

Change-Id: I6217de707e49882bd5a9100db43e0d354908800d
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean

Improve use and readability.

Change-Id: Ia99fc38287f36c9dd12bfe51352afa5da68c0e47
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@

refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean

Improve use and readability.

Change-Id: Ia99fc38287f36c9dd12bfe51352afa5da68c0e47
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(clk): add a minimal clock framework

This is mainly a clock interface with clk_ops callbacks.
Those callbacks are: enable, disable, get_rate, set_parent,
and is_enabled.
This framework is compil

feat(clk): add a minimal clock framework

This is mainly a clock interface with clk_ops callbacks.
Those callbacks are: enable, disable, get_rate, set_parent,
and is_enabled.
This framework is compiled for STM32MP1.

Change-Id: I5119a2aeaf103ceaae7a60d9e423caf0c148d794
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

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fix(errata): workaround for Cortex X2 erratum 2058056

Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.

There are

fix(errata): workaround for Cortex X2 erratum 2058056

Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.

There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for
details)

However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3

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fix(errata): workaround for Cortex X2 erratum 2083908

Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.

SDEN can be found he

fix(errata): workaround for Cortex X2 erratum 2083908

Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Id9dca2b042bf48e75fb3013ab37d1c5925824728

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Merge changes from topic "fconf_get_index" into integration

* changes:
feat(stm32mp1): skip TOS_FW_CONFIG if not in FIP
feat(fconf): add a helper to get image index

feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX

FEAT_CCIDX modifies the register fields in CCSIDR/CCSIDR2 (aarch32)
and CCSIDR_EL1 (aarch64). This patch adds a check to the do_dcsw

feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX

FEAT_CCIDX modifies the register fields in CCSIDR/CCSIDR2 (aarch32)
and CCSIDR_EL1 (aarch64). This patch adds a check to the do_dcsw_op
function to use the right register format rather than assuming
that FEAT_CCIDX is not implemented.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I12cd00cd7b5889525d4d2750281a751dd74ef5dc

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feat(stm32_gpio): add a function to reset a pin

Add set_gpio_reset_cfg() to set a pin in its reset configuration:
analog, no-pull, speed low, and its secure configuration, thanks to
stm32_gpio_is_se

feat(stm32_gpio): add a function to reset a pin

Add set_gpio_reset_cfg() to set a pin in its reset configuration:
analog, no-pull, speed low, and its secure configuration, thanks to
stm32_gpio_is_secure_at_reset().

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b73c3636859f97fcc57f81cf68b42efc727922e

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feat(fconf): add a helper to get image index

A new function dyn_cfg_dtb_info_get_index() is created to get the index
of the given image config_id in the dtb_infos pool.
This allows checking if an im

feat(fconf): add a helper to get image index

A new function dyn_cfg_dtb_info_get_index() is created to get the index
of the given image config_id in the dtb_infos pool.
This allows checking if an image with a specific ID is in the FIP.

Change-Id: Ib300ed08e5b8a683dc7980a90221c305fb3f457d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topic "jc/AMUv1" into integration

* changes:
docs(build-options): add build macros for features FGT,AMUv1 and ECV
fix(amu): fault handling on EL2 context switch

Merge changes from topic "mb_critical_data" into integration

* changes:
docs(measured-boot): add a platform function for critical data
feat(fvp): measure critical data

fix(amu): fault handling on EL2 context switch

The HAFGRTR_EL2 register is UNDEFINED unless the CPU supports both
FEAT_FGT and FEAT_AMUv1. FEAT_FGT is mandatory for v8.6-A and upwards,
but FEAT_AMUv

fix(amu): fault handling on EL2 context switch

The HAFGRTR_EL2 register is UNDEFINED unless the CPU supports both
FEAT_FGT and FEAT_AMUv1. FEAT_FGT is mandatory for v8.6-A and upwards,
but FEAT_AMUv1 is optional (from v8.4-A upwards), and as such any
8.6-A cores today without support for FEAT_AMUv1 will trigger an
undefined instruction exception on accessing this register.

Currently ARM_ARCH_AT_LEAST macro has been used to associate with an
architecture extension allowing to access HAFGRTR_EL2 register. This
condition should be replaced with macros specific to individual
features. This patch adds a new set of macros "ENABLE_FEAT_FGT,
ENABLE_FEAT_AMUv1, ENABLE_FEAT_ECV" under build options to provide
controlled access to the HAFGRTR_EL2 register.

Further to ensure that the the build options passed comply
with the given hardware implementation, a feature detection mechanism,
checking whether build options match with the architecture is required
at bootime. This will be implemented and pushed later in a separate
patch.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie390f4babe233b8b09455290277edbddecd33ead

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Merge "fix(rmmd): align RMI and GTSI FIDs with SMCCC" into integration

feat(fvp): measure critical data

Implemented a platform function 'plat_mboot_measure_critical_data' to
measure critical data and record its measurement using the Event Log
driver.
'bl2_plat_mboot_fi

feat(fvp): measure critical data

Implemented a platform function 'plat_mboot_measure_critical_data' to
measure critical data and record its measurement using the Event Log
driver.
'bl2_plat_mboot_finish' function invokes this platform function
immediately after populating the critical data.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia198295c6e07ab26d436eab1ff90df2cf28303af

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refactor(measured-boot): add generic macros for using Crypto library

It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in

refactor(measured-boot): add generic macros for using Crypto library

It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in future.
Hence mbed TLS Crypto dependency on Event Log driver is removed by
introducing generic Crypto defines and uses those in the Event Log
driver to call Crypto functions.
Also, updated mbed TLS glue layer to map these generic Crypto defines
to mbed TLS library defines.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ibc9c751f60cbce4d3f3cf049b7c53b3d05cc6735

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fix(rmmd): align RMI and GTSI FIDs with SMCCC

This patch allocates the RMI and GTSI FIDs from the reserved
range in Standard Secure Service call range of SMCCC.

Signed-off-by: Subhasish Ghosh <subh

fix(rmmd): align RMI and GTSI FIDs with SMCCC

This patch allocates the RMI and GTSI FIDs from the reserved
range in Standard Secure Service call range of SMCCC.

Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I82e77778882194c2a78ca6340788d53bab7c3a50

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Merge "refactor(measured boot): rename a macro INVALID_ID to EVLOG_INVALID_ID" into integration

feat(drivers/st/uart): add uart driver for STM32MP1

Add a UART/USART driver for STM32 with complete a hardware support;
it used for STM32CubeProgrammer support with even parity.

This driver is not

feat(drivers/st/uart): add uart driver for STM32MP1

Add a UART/USART driver for STM32 with complete a hardware support;
it used for STM32CubeProgrammer support with even parity.

This driver is not used for console, which is already handle
by a simple driver (drivers/st/uart/aarch32/stm32_console.S).

Change-Id: Ia9266e5d177fe7fd09c8a15b81da1a05b1bc8b2d
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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fix(plat/marvell/a3720/uart): do external reset during initialization

Sometimes when changing UART clock from TBG to XTAL, UART HW enters into
some broken state. It does not transit characters from

fix(plat/marvell/a3720/uart): do external reset during initialization

Sometimes when changing UART clock from TBG to XTAL, UART HW enters into
some broken state. It does not transit characters from TX FIFO anymore
and TX FIFO stays always empty. TX FIFO reset does not recover UART HW
from this broken state.

Experiments show that external reset can fix UART HW from this broken
state.

TF-A fatal error handler calls console_a3700_core_init() function to
initialize UART HW. This handler may be called anytime during CPU
runtime, also when kernel is running.

U-Boot or Linux kernel may change UART clock to TBG to achieve higher
baudrates. During initialization, console_a3700_core_init() resets UART
configuration to default settings, which means that it also changes
UART clock from TBG to XTAL.

Do an external reset of UART via North Bridge Peripheral reset register
to prevent this UART hangup.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8990bce24d1a6fd8ccc47a2cd0a5ff932fcfcf14

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refactor(measured boot): rename a macro INVALID_ID to EVLOG_INVALID_ID

Renamed a macro 'INVALID_ID' to 'EVLOG_INVALID_ID' to avoid its clash
with other macro names and to show it is explicitly used

refactor(measured boot): rename a macro INVALID_ID to EVLOG_INVALID_ID

Renamed a macro 'INVALID_ID' to 'EVLOG_INVALID_ID' to avoid its clash
with other macro names and to show it is explicitly used for Event
Log driver.

Change-Id: Ie4c92b3cd1366d9a59cd6f43221e24734865f427
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(sme): enable SME functionality

This patch adds two new compile time options to enable SME in TF-A:
ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and
secure worlds respectively.

feat(sme): enable SME functionality

This patch adds two new compile time options to enable SME in TF-A:
ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and
secure worlds respectively. Setting ENABLE_SME_FOR_NS=1 will enable
SME for non-secure worlds and trap SME, SVE, and FPU/SIMD instructions
in secure context. Setting ENABLE_SME_FOR_SWD=1 will disable these
traps, but support for SME context management does not yet exist in
SPM so building with SPD=spmd will fail.

The existing ENABLE_SVE_FOR_NS and ENABLE_SVE_FOR_SWD options cannot
be used with SME as it is a superset of SVE and will enable SVE and
FPU/SIMD along with SME.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Iaaac9d22fe37b4a92315207891da848a8fd0ed73

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Merge "Changing SMC code for transitioning Granule" into integration