feat(common): add SZ_* macros

Add the SZ_* macros from 32 to 2G.
This allows removing some defines in raw NAND driver
and STM32MP1 boot device selection code.

Change-Id: I3c4d4959b0f43e785eeb37a43d

feat(common): add SZ_* macros

Add the SZ_* macros from 32 to 2G.
This allows removing some defines in raw NAND driver
and STM32MP1 boot device selection code.

Change-Id: I3c4d4959b0f43e785eeb37a43d03b2906b7fcfbc
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>

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fix(errata): workaround for Cortex-A710 erratum 2136059

Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround i

fix(errata): workaround for Cortex-A710 erratum 2136059

Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause
the CPP instruction to invalidate the hardware prefetcher state
trained from any EL.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc

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fix(errata): workaround for Cortex-A710 erratum 2267065

Cortex-A710 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround

fix(errata): workaround for Cortex-A710 erratum 2267065

Cortex-A710 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR_EL1[22] to 1'b1. Setting
CPUACTLR_EL1[22] will cause the CFP instruction to invalidate
all branch predictor resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia9085aaf9b2b6a2b25d03ab36bd3774839fac9aa

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fix(errata): workaround for Cortex-X2 erratum 2216384

Cortex-X2 erratum 2216384 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of CPU. It is fixed in r2p1.
The workaround is to set

fix(errata): workaround for Cortex-X2 erratum 2216384

Cortex-X2 erratum 2216384 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[17] to 1'b1 followed by
applying an instruction patching sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3c216161678887c06a28c59644e784e0c7d37bab

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fix(errata): workaround for Cortex-X2 errata 2081180

Cortex-X2 erratum 2081180 is a Cat B erratum present in r0p0, r1p0
and r2p0 of the Cortex-X2 processor core.

Cortex-X2 SDEN: https://developer.a

fix(errata): workaround for Cortex-X2 errata 2081180

Cortex-X2 erratum 2081180 is a Cat B erratum present in r0p0, r1p0
and r2p0 of the Cortex-X2 processor core.

Cortex-X2 SDEN: https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I64bed2fd5b7e12932d6de2ae668786e689885188

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fix(errata): workaround for Cortex-X2 errata 2017096

Cortex-X2 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8]
to 1 which dis

fix(errata): workaround for Cortex-X2 errata 2017096

Cortex-X2 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8]
to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05

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Merge "feat(st): update the security based on new compatible" into integration

feat(gic): allow overriding GICD_PIDR2_GICV2 address

Older Qualcomm SoCs seem to have a custom Qualcomm implementation of
the GICv2 specification. It's mostly compliant but unfortunately it
looks li

feat(gic): allow overriding GICD_PIDR2_GICV2 address

Older Qualcomm SoCs seem to have a custom Qualcomm implementation of
the GICv2 specification. It's mostly compliant but unfortunately it
looks like a mistake was made with the GICD_PIDR registers. PIDR2 is
defined to be at offset 0xFE8, but the Qualcomm implementation has it
at 0xFD8.

It looks like the entire PIDR0-3/4-7 block is swapped compared to the
ARM implementation: PIDR0 starts at 0xFD0 (instead of 0xFE0)
and PIDR4 starts at 0xFE0 (instead of 0xFD0).

Actually this only breaks a single assert in gicv2_main.c that checks
the GIC version: assert((gic_version == ARCH_REV_GICV2) ...
In release mode everything seems to work correctly.

To keep the code generic, allow affected platforms to override the
GICD_PIDR2_GICV2 register address in platform_def.h. Since this header
is typically included very early (e.g. from assert.h), add an #ifndef
so the definitions from platform_def.h takes priority.

Change-Id: I2929a8c1726f8d751bc28796567eb30b81eca2fe
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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test(el3-runtime): dit is retained on world switch

Add tsp service to check the value of the PSTATE DIT bit is as
expected and toggle it's value. This is used to ensure that
the DIT bit is maintaine

test(el3-runtime): dit is retained on world switch

Add tsp service to check the value of the PSTATE DIT bit is as
expected and toggle it's value. This is used to ensure that
the DIT bit is maintained during a switch from the Normal to
Secure worlds and back.

Change-Id: I4e8bdfa6530e5e75925c0079d4fa2795133c5105
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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fix(el3-runtime): set unset pstate bits to default

During a transition to a higher EL some of the PSTATE bits are not set
by hardware, this means that their state may be leaked from lower ELs.
This

fix(el3-runtime): set unset pstate bits to default

During a transition to a higher EL some of the PSTATE bits are not set
by hardware, this means that their state may be leaked from lower ELs.
This patch sets those bits to a default value upon entry to EL3.

This patch was tested using a debugger to check the PSTATE values
are correctly set. As well as adding a test in the next patch to
ensure the PSTATE in lower ELs is still maintained after this change.

Change-Id: Ie546acbca7b9aa3c86bd68185edded91b2a64ae5
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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feat(st): update the security based on new compatible

From the new binding, the RCC become secured based on the new
compatible. This must be done only from the secure OS initialisation.

Signed-off-

feat(st): update the security based on new compatible

From the new binding, the RCC become secured based on the new
compatible. This must be done only from the secure OS initialisation.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I7f0a62f22bfcca638ddaefc9563df00f89f01653

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feat(st-gpio): allow to set a gpio in output mode

Allow to set a gpio in output mode from the device tree.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: Ic483324bc5fe916a6

feat(st-gpio): allow to set a gpio in output mode

Allow to set a gpio in output mode from the device tree.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: Ic483324bc5fe916a60df05f74706bd1da4d08aa5

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refactor(st-gpio): code improvements

No functional, change, but some improvements:
- Declare set_gpio() as static (only called locally)
- Handle the type ('open-drain') property independently from t

refactor(st-gpio): code improvements

No functional, change, but some improvements:
- Declare set_gpio() as static (only called locally)
- Handle the type ('open-drain') property independently from the
mode one.
- Replace mmio_clrbits_32() + mmio_setbits_32() with
mmio_clrsetbits_32().
- Add a missing log
- Add missing U() in macro definitions

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: I1a79609609ac8e8001127ebefdb81def573f76fa

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refactor(st-drivers): improve BSEC driver

Rename driver file to BSEC2.
Split header file in IP and feature parts.
Add functions to access BSEC scratch register.
Several corrections and improvements.

refactor(st-drivers): improve BSEC driver

Rename driver file to BSEC2.
Split header file in IP and feature parts.
Add functions to access BSEC scratch register.
Several corrections and improvements.
Probe the driver earlier, especially to check debug features.

Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(cpu): add library support for Poseidon CPU

This patch adds the basic CPU library code to support the Poseidon CPU
in TF-A. Poseidon is derived from HunterELP core, an implementation of
v9.2 arc

feat(cpu): add library support for Poseidon CPU

This patch adds the basic CPU library code to support the Poseidon CPU
in TF-A. Poseidon is derived from HunterELP core, an implementation of
v9.2 architecture. Currently, Hunter CPU the predecessor to HunterELP,
is supported in TF-A. Accordingly the Hunter CPU library code has been
as the base and adapted here.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I406b4de156a67132e6a5523370115aaac933f18d

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refactor(st-clock): update STGEN management

Rework STGEN config function, and move it to stm32mp_clkfunc.c file.

Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6
Signed-off-by: Lionel Debieve <

refactor(st-clock): update STGEN management

Rework STGEN config function, and move it to stm32mp_clkfunc.c file.

Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(st-clock): use refcnt instead of secure status

Rework the internal functions __stm32mp1_clk_enable/disable to check for
reference count instead of secure status for a clock.
Some functions

refactor(st-clock): use refcnt instead of secure status

Rework the internal functions __stm32mp1_clk_enable/disable to check for
reference count instead of secure status for a clock.
Some functions now unused can be removed.

Change-Id: Ie4359110d7144229f85c961dcd5a019222c3fd25
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(fwu): add platform hook for getting the boot index

Add a platform hook for returning the boot index, i.e. the bank from
which the platform has booted the updatable firmware images. This
value w

feat(fwu): add platform hook for getting the boot index

Add a platform hook for returning the boot index, i.e. the bank from
which the platform has booted the updatable firmware images. This
value will be passed to the Update Agent.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: Ic7bef21071c48cfc7b69c50e89df9ff758d95b00

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feat(fwu): add a function to pass metadata structure to platforms

Add a helper function to pass the metadata structure to the
platforms. Platforms can then read the metadata structure and pass the
b

feat(fwu): add a function to pass metadata structure to platforms

Add a helper function to pass the metadata structure to the
platforms. Platforms can then read the metadata structure and pass the
boot index value, i.e. the bank(partition) from which the firmware
images were booted, to the Update Agent.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I571179b9baa0fbc4d0f08d7a6e3b50c0c7165c5c

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feat(partition): add a function to identify a partition by GUID

With the GPT partition scheme, a partition can be identified using
it's UniquePartitionGUID, instead of it's name. Add a function to
i

feat(partition): add a function to identify a partition by GUID

With the GPT partition scheme, a partition can be identified using
it's UniquePartitionGUID, instead of it's name. Add a function to
identify the partition based on this GUID value. This functionality is
useful in identification of a partition whose UniquePartitionGUID
value is known.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I543f794e1f7773f969968a6bce85ecca6f6a1659

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feat(partition): make provision to store partition GUID value

The FWU multi bank feature supports multiple partitions or banks of
firmware components, where a platform can support having an active a

feat(partition): make provision to store partition GUID value

The FWU multi bank feature supports multiple partitions or banks of
firmware components, where a platform can support having an active and
a backup partition(bank) of firmware images to boot from. This feature
identifies the images in a given bank using image GUID's --
this GUID value corresponds to the UniquePartitionGUID value used to
uniquely identify a GPT partition.

To support identification of images, add a member to the
partition_entry structure to store the UniquePartitionGUID value of
the GPT partition entry. This value is subsequently used to select the
firmware image to boot in a multi partition setup.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I2d235467ce7a7f20ebc1cef4db09924a5282e714

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feat(partition): cleanup partition and gpt headers

The EFI_NAMELEN macro has been moved to efi.h header. Get the macro
from efi.h. Use the struct efi_guid structure for declaring GUID
members in gpt

feat(partition): cleanup partition and gpt headers

The EFI_NAMELEN macro has been moved to efi.h header. Get the macro
from efi.h. Use the struct efi_guid structure for declaring GUID
members in gpt.h

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I1c3a2605b9f857b9cf2dcfdaed4dc9d0a2cbf0f0

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feat(fwu): add basic definitions for GUID handling

The FWU metadata structure uses GUID's to identify the updatable
firmware images. Add some basic helper functions and
macros that would be used for

feat(fwu): add basic definitions for GUID handling

The FWU metadata structure uses GUID's to identify the updatable
firmware images. Add some basic helper functions and
macros that would be used for working with the GUID datatype.

With the FWU feature enabled, these would then be used for image
identification and booting of images from a particular
bank(partition).

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: Ia54c0402d72b503d6abd1d94bc751cc14602cd39

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feat(fwu): pass a const metadata structure to platform routines

The metadata structure copy is passed to the platform routine to set
the image source to boot the platform from. This is done by readi

feat(fwu): pass a const metadata structure to platform routines

The metadata structure copy is passed to the platform routine to set
the image source to boot the platform from. This is done by reading
the metadata structure. Pass the metadata as a read-only copy to the
routine -- the routine only needs to consume the metadata values and
should not be able to update the metadata fields.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I399cad99ab89c71483e5a32a1de0e22df304f8b0

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Merge changes from topic "decouple-tb-mb" into integration

* changes:
refactor(renesas): disable CRYPTO_SUPPORT option
refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot
refactor(me

Merge changes from topic "decouple-tb-mb" into integration

* changes:
refactor(renesas): disable CRYPTO_SUPPORT option
refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
build: introduce CRYPTO_SUPPORT build option

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