1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <drivers/arm/gicv3.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/el3_runtime/pubsub_events.h> 22 #include <lib/extensions/amu.h> 23 #include <lib/extensions/mpam.h> 24 #include <lib/extensions/sme.h> 25 #include <lib/extensions/spe.h> 26 #include <lib/extensions/sve.h> 27 #include <lib/extensions/sys_reg_trace.h> 28 #include <lib/extensions/trbe.h> 29 #include <lib/extensions/trf.h> 30 #include <lib/utils.h> 31 32 #if ENABLE_FEAT_TWED 33 /* Make sure delay value fits within the range(0-15) */ 34 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 35 #endif /* ENABLE_FEAT_TWED */ 36 37 static void manage_extensions_secure(cpu_context_t *ctx); 38 /****************************************************************************** 39 * This function performs initializations that are specific to SECURE state 40 * and updates the cpu context specified by 'ctx'. 41 *****************************************************************************/ 42 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t scr_el3; 45 el3_state_t *state; 46 47 state = get_el3state_ctx(ctx); 48 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 49 50 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 51 /* 52 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 53 * indicated by the interrupt routing model for BL31. 54 */ 55 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 56 #endif 57 58 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 59 /* Get Memory Tagging Extension support level */ 60 unsigned int mte = get_armv8_5_mte_support(); 61 #endif 62 /* 63 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 64 * is set, or when MTE is only implemented at EL0. 65 */ 66 #if CTX_INCLUDE_MTE_REGS 67 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 68 scr_el3 |= SCR_ATA_BIT; 69 #else 70 if (mte == MTE_IMPLEMENTED_EL0) { 71 scr_el3 |= SCR_ATA_BIT; 72 } 73 #endif /* CTX_INCLUDE_MTE_REGS */ 74 75 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 76 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 77 if (GET_RW(ep->spsr) != MODE_RW_64) { 78 ERROR("S-EL2 can not be used in AArch32\n."); 79 panic(); 80 } 81 82 scr_el3 |= SCR_EEL2_BIT; 83 } 84 85 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 86 87 manage_extensions_secure(ctx); 88 } 89 90 #if ENABLE_RME 91 /****************************************************************************** 92 * This function performs initializations that are specific to REALM state 93 * and updates the cpu context specified by 'ctx'. 94 *****************************************************************************/ 95 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 96 { 97 u_register_t scr_el3; 98 el3_state_t *state; 99 100 state = get_el3state_ctx(ctx); 101 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 102 103 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 104 105 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 106 } 107 #endif /* ENABLE_RME */ 108 109 /****************************************************************************** 110 * This function performs initializations that are specific to NON-SECURE state 111 * and updates the cpu context specified by 'ctx'. 112 *****************************************************************************/ 113 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 114 { 115 u_register_t scr_el3; 116 el3_state_t *state; 117 118 state = get_el3state_ctx(ctx); 119 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 120 121 /* SCR_NS: Set the NS bit */ 122 scr_el3 |= SCR_NS_BIT; 123 124 #if !CTX_INCLUDE_PAUTH_REGS 125 /* 126 * If the pointer authentication registers aren't saved during world 127 * switches the value of the registers can be leaked from the Secure to 128 * the Non-secure world. To prevent this, rather than enabling pointer 129 * authentication everywhere, we only enable it in the Non-secure world. 130 * 131 * If the Secure world wants to use pointer authentication, 132 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 133 */ 134 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 135 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 136 137 /* Allow access to Allocation Tags when MTE is implemented. */ 138 scr_el3 |= SCR_ATA_BIT; 139 140 #ifdef IMAGE_BL31 141 /* 142 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 143 * indicated by the interrupt routing model for BL31. 144 */ 145 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 146 #endif 147 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 148 149 /* Initialize EL2 context registers */ 150 #if CTX_INCLUDE_EL2_REGS 151 152 /* 153 * Initialize SCTLR_EL2 context register using Endianness value 154 * taken from the entrypoint attribute. 155 */ 156 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 157 sctlr_el2 |= SCTLR_EL2_RES1; 158 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 159 sctlr_el2); 160 161 /* 162 * The GICv3 driver initializes the ICC_SRE_EL2 register during 163 * platform setup. Use the same setting for the corresponding 164 * context register to make sure the correct bits are set when 165 * restoring NS context. 166 */ 167 u_register_t icc_sre_el2 = read_icc_sre_el2(); 168 icc_sre_el2 |= (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT); 169 icc_sre_el2 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 170 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 171 icc_sre_el2); 172 #endif /* CTX_INCLUDE_EL2_REGS */ 173 } 174 175 /******************************************************************************* 176 * The following function performs initialization of the cpu_context 'ctx' 177 * for first use that is common to all security states, and sets the 178 * initial entrypoint state as specified by the entry_point_info structure. 179 * 180 * The EE and ST attributes are used to configure the endianness and secure 181 * timer availability for the new execution context. 182 ******************************************************************************/ 183 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 184 { 185 u_register_t scr_el3; 186 el3_state_t *state; 187 gp_regs_t *gp_regs; 188 u_register_t sctlr_elx, actlr_elx; 189 190 /* Clear any residual register values from the context */ 191 zeromem(ctx, sizeof(*ctx)); 192 193 /* 194 * SCR_EL3 was initialised during reset sequence in macro 195 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 196 * affect the next EL. 197 * 198 * The following fields are initially set to zero and then updated to 199 * the required value depending on the state of the SPSR_EL3 and the 200 * Security state and entrypoint attributes of the next EL. 201 */ 202 scr_el3 = read_scr(); 203 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 204 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 205 206 /* 207 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 208 * Exception level as specified by SPSR. 209 */ 210 if (GET_RW(ep->spsr) == MODE_RW_64) { 211 scr_el3 |= SCR_RW_BIT; 212 } 213 214 /* 215 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 216 * Secure timer registers to EL3, from AArch64 state only, if specified 217 * by the entrypoint attributes. 218 */ 219 if (EP_GET_ST(ep->h.attr) != 0U) { 220 scr_el3 |= SCR_ST_BIT; 221 } 222 223 /* 224 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 225 * SCR_EL3.HXEn. 226 */ 227 #if ENABLE_FEAT_HCX 228 scr_el3 |= SCR_HXEn_BIT; 229 #endif 230 231 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 232 /* 233 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 234 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 235 */ 236 scr_el3 |= SCR_TERR_BIT; 237 #endif 238 239 #if !HANDLE_EA_EL3_FIRST 240 /* 241 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 242 * to EL3 when executing at a lower EL. When executing at EL3, External 243 * Aborts are taken to EL3. 244 */ 245 scr_el3 &= ~SCR_EA_BIT; 246 #endif 247 248 #if FAULT_INJECTION_SUPPORT 249 /* Enable fault injection from lower ELs */ 250 scr_el3 |= SCR_FIEN_BIT; 251 #endif 252 253 /* 254 * CPTR_EL3 was initialized out of reset, copy that value to the 255 * context register. 256 */ 257 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 258 259 /* 260 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 261 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 262 * next mode is Hyp. 263 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 264 * same conditions as HVC instructions and when the processor supports 265 * ARMv8.6-FGT. 266 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 267 * CNTPOFF_EL2 register under the same conditions as HVC instructions 268 * and when the processor supports ECV. 269 */ 270 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 271 || ((GET_RW(ep->spsr) != MODE_RW_64) 272 && (GET_M32(ep->spsr) == MODE32_hyp))) { 273 scr_el3 |= SCR_HCE_BIT; 274 275 if (is_armv8_6_fgt_present()) { 276 scr_el3 |= SCR_FGTEN_BIT; 277 } 278 279 if (get_armv8_6_ecv_support() 280 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 281 scr_el3 |= SCR_ECVEN_BIT; 282 } 283 } 284 285 /* 286 * Initialise SCTLR_EL1 to the reset value corresponding to the target 287 * execution state setting all fields rather than relying of the hw. 288 * Some fields have architecturally UNKNOWN reset values and these are 289 * set to zero. 290 * 291 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 292 * 293 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 294 * required by PSCI specification) 295 */ 296 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 297 if (GET_RW(ep->spsr) == MODE_RW_64) { 298 sctlr_elx |= SCTLR_EL1_RES1; 299 } else { 300 /* 301 * If the target execution state is AArch32 then the following 302 * fields need to be set. 303 * 304 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 305 * instructions are not trapped to EL1. 306 * 307 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 308 * instructions are not trapped to EL1. 309 * 310 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 311 * CP15DMB, CP15DSB, and CP15ISB instructions. 312 */ 313 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 314 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 315 } 316 317 #if ERRATA_A75_764081 318 /* 319 * If workaround of errata 764081 for Cortex-A75 is used then set 320 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 321 */ 322 sctlr_elx |= SCTLR_IESB_BIT; 323 #endif 324 325 #if ENABLE_FEAT_TWED 326 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 327 /* Set delay in SCR_EL3 */ 328 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 329 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 330 << SCR_TWEDEL_SHIFT); 331 332 /* Enable WFE delay */ 333 scr_el3 |= SCR_TWEDEn_BIT; 334 #endif /* ENABLE_FEAT_TWED */ 335 336 /* 337 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 338 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 339 * are not part of the stored cpu_context. 340 */ 341 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 342 343 /* 344 * Base the context ACTLR_EL1 on the current value, as it is 345 * implementation defined. The context restore process will write 346 * the value from the context to the actual register and can cause 347 * problems for processor cores that don't expect certain bits to 348 * be zero. 349 */ 350 actlr_elx = read_actlr_el1(); 351 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 352 353 /* 354 * Populate EL3 state so that we've the right context 355 * before doing ERET 356 */ 357 state = get_el3state_ctx(ctx); 358 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 359 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 360 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 361 362 /* 363 * Store the X0-X7 value from the entrypoint into the context 364 * Use memcpy as we are in control of the layout of the structures 365 */ 366 gp_regs = get_gpregs_ctx(ctx); 367 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 368 } 369 370 /******************************************************************************* 371 * Context management library initialization routine. This library is used by 372 * runtime services to share pointers to 'cpu_context' structures for secure 373 * non-secure and realm states. Management of the structures and their associated 374 * memory is not done by the context management library e.g. the PSCI service 375 * manages the cpu context used for entry from and exit to the non-secure state. 376 * The Secure payload dispatcher service manages the context(s) corresponding to 377 * the secure state. It also uses this library to get access to the non-secure 378 * state cpu context pointers. 379 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 380 * which will be used for programming an entry into a lower EL. The same context 381 * will be used to save state upon exception entry from that EL. 382 ******************************************************************************/ 383 void __init cm_init(void) 384 { 385 /* 386 * The context management library has only global data to intialize, but 387 * that will be done when the BSS is zeroed out. 388 */ 389 } 390 391 /******************************************************************************* 392 * This is the high-level function used to initialize the cpu_context 'ctx' for 393 * first use. It performs initializations that are common to all security states 394 * and initializations specific to the security state specified in 'ep' 395 ******************************************************************************/ 396 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 397 { 398 unsigned int security_state; 399 400 assert(ctx != NULL); 401 402 /* 403 * Perform initializations that are common 404 * to all security states 405 */ 406 setup_context_common(ctx, ep); 407 408 security_state = GET_SECURITY_STATE(ep->h.attr); 409 410 /* Perform security state specific initializations */ 411 switch (security_state) { 412 case SECURE: 413 setup_secure_context(ctx, ep); 414 break; 415 #if ENABLE_RME 416 case REALM: 417 setup_realm_context(ctx, ep); 418 break; 419 #endif 420 case NON_SECURE: 421 setup_ns_context(ctx, ep); 422 break; 423 default: 424 ERROR("Invalid security state\n"); 425 panic(); 426 break; 427 } 428 } 429 430 /******************************************************************************* 431 * Enable architecture extensions on first entry to Non-secure world. 432 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 433 * it is zero. 434 ******************************************************************************/ 435 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 436 { 437 #if IMAGE_BL31 438 #if ENABLE_SPE_FOR_LOWER_ELS 439 spe_enable(el2_unused); 440 #endif 441 442 #if ENABLE_AMU 443 amu_enable(el2_unused, ctx); 444 #endif 445 446 #if ENABLE_SME_FOR_NS 447 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 448 sme_enable(ctx); 449 #elif ENABLE_SVE_FOR_NS 450 /* Enable SVE and FPU/SIMD for non-secure world. */ 451 sve_enable(ctx); 452 #endif 453 454 #if ENABLE_MPAM_FOR_LOWER_ELS 455 mpam_enable(el2_unused); 456 #endif 457 458 #if ENABLE_TRBE_FOR_NS 459 trbe_enable(); 460 #endif /* ENABLE_TRBE_FOR_NS */ 461 462 #if ENABLE_SYS_REG_TRACE_FOR_NS 463 sys_reg_trace_enable(ctx); 464 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 465 466 #if ENABLE_TRF_FOR_NS 467 trf_enable(); 468 #endif /* ENABLE_TRF_FOR_NS */ 469 #endif 470 } 471 472 /******************************************************************************* 473 * Enable architecture extensions on first entry to Secure world. 474 ******************************************************************************/ 475 static void manage_extensions_secure(cpu_context_t *ctx) 476 { 477 #if IMAGE_BL31 478 #if ENABLE_SME_FOR_NS 479 #if ENABLE_SME_FOR_SWD 480 /* 481 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 482 * ensure SME, SVE, and FPU/SIMD context properly managed. 483 */ 484 sme_enable(ctx); 485 #else /* ENABLE_SME_FOR_SWD */ 486 /* 487 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 488 * safely use the associated registers. 489 */ 490 sme_disable(ctx); 491 #endif /* ENABLE_SME_FOR_SWD */ 492 #elif ENABLE_SVE_FOR_NS 493 #if ENABLE_SVE_FOR_SWD 494 /* 495 * Enable SVE and FPU in secure context, secure manager must ensure that 496 * the SVE and FPU register contexts are properly managed. 497 */ 498 sve_enable(ctx); 499 #else /* ENABLE_SVE_FOR_SWD */ 500 /* 501 * Disable SVE and FPU in secure context so non-secure world can safely 502 * use them. 503 */ 504 sve_disable(ctx); 505 #endif /* ENABLE_SVE_FOR_SWD */ 506 #endif /* ENABLE_SVE_FOR_NS */ 507 #endif /* IMAGE_BL31 */ 508 } 509 510 /******************************************************************************* 511 * The following function initializes the cpu_context for a CPU specified by 512 * its `cpu_idx` for first use, and sets the initial entrypoint state as 513 * specified by the entry_point_info structure. 514 ******************************************************************************/ 515 void cm_init_context_by_index(unsigned int cpu_idx, 516 const entry_point_info_t *ep) 517 { 518 cpu_context_t *ctx; 519 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 520 cm_setup_context(ctx, ep); 521 } 522 523 /******************************************************************************* 524 * The following function initializes the cpu_context for the current CPU 525 * for first use, and sets the initial entrypoint state as specified by the 526 * entry_point_info structure. 527 ******************************************************************************/ 528 void cm_init_my_context(const entry_point_info_t *ep) 529 { 530 cpu_context_t *ctx; 531 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 532 cm_setup_context(ctx, ep); 533 } 534 535 /******************************************************************************* 536 * Prepare the CPU system registers for first entry into realm, secure, or 537 * normal world. 538 * 539 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 540 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 541 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 542 * For all entries, the EL1 registers are initialized from the cpu_context 543 ******************************************************************************/ 544 void cm_prepare_el3_exit(uint32_t security_state) 545 { 546 u_register_t sctlr_elx, scr_el3, mdcr_el2; 547 cpu_context_t *ctx = cm_get_context(security_state); 548 bool el2_unused = false; 549 uint64_t hcr_el2 = 0U; 550 551 assert(ctx != NULL); 552 553 if (security_state == NON_SECURE) { 554 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 555 CTX_SCR_EL3); 556 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 557 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 558 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 559 CTX_SCTLR_EL1); 560 sctlr_elx &= SCTLR_EE_BIT; 561 sctlr_elx |= SCTLR_EL2_RES1; 562 #if ERRATA_A75_764081 563 /* 564 * If workaround of errata 764081 for Cortex-A75 is used 565 * then set SCTLR_EL2.IESB to enable Implicit Error 566 * Synchronization Barrier. 567 */ 568 sctlr_elx |= SCTLR_IESB_BIT; 569 #endif 570 write_sctlr_el2(sctlr_elx); 571 } else if (el_implemented(2) != EL_IMPL_NONE) { 572 el2_unused = true; 573 574 /* 575 * EL2 present but unused, need to disable safely. 576 * SCTLR_EL2 can be ignored in this case. 577 * 578 * Set EL2 register width appropriately: Set HCR_EL2 579 * field to match SCR_EL3.RW. 580 */ 581 if ((scr_el3 & SCR_RW_BIT) != 0U) 582 hcr_el2 |= HCR_RW_BIT; 583 584 /* 585 * For Armv8.3 pointer authentication feature, disable 586 * traps to EL2 when accessing key registers or using 587 * pointer authentication instructions from lower ELs. 588 */ 589 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 590 591 write_hcr_el2(hcr_el2); 592 593 /* 594 * Initialise CPTR_EL2 setting all fields rather than 595 * relying on the hw. All fields have architecturally 596 * UNKNOWN reset values. 597 * 598 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 599 * accesses to the CPACR_EL1 or CPACR from both 600 * Execution states do not trap to EL2. 601 * 602 * CPTR_EL2.TTA: Set to zero so that Non-secure System 603 * register accesses to the trace registers from both 604 * Execution states do not trap to EL2. 605 * If PE trace unit System registers are not implemented 606 * then this bit is reserved, and must be set to zero. 607 * 608 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 609 * to SIMD and floating-point functionality from both 610 * Execution states do not trap to EL2. 611 */ 612 write_cptr_el2(CPTR_EL2_RESET_VAL & 613 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 614 | CPTR_EL2_TFP_BIT)); 615 616 /* 617 * Initialise CNTHCTL_EL2. All fields are 618 * architecturally UNKNOWN on reset and are set to zero 619 * except for field(s) listed below. 620 * 621 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 622 * Hyp mode of Non-secure EL0 and EL1 accesses to the 623 * physical timer registers. 624 * 625 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 626 * Hyp mode of Non-secure EL0 and EL1 accesses to the 627 * physical counter registers. 628 */ 629 write_cnthctl_el2(CNTHCTL_RESET_VAL | 630 EL1PCEN_BIT | EL1PCTEN_BIT); 631 632 /* 633 * Initialise CNTVOFF_EL2 to zero as it resets to an 634 * architecturally UNKNOWN value. 635 */ 636 write_cntvoff_el2(0); 637 638 /* 639 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 640 * MPIDR_EL1 respectively. 641 */ 642 write_vpidr_el2(read_midr_el1()); 643 write_vmpidr_el2(read_mpidr_el1()); 644 645 /* 646 * Initialise VTTBR_EL2. All fields are architecturally 647 * UNKNOWN on reset. 648 * 649 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 650 * 2 address translation is disabled, cache maintenance 651 * operations depend on the VMID. 652 * 653 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 654 * translation is disabled. 655 */ 656 write_vttbr_el2(VTTBR_RESET_VAL & 657 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 658 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 659 660 /* 661 * Initialise MDCR_EL2, setting all fields rather than 662 * relying on hw. Some fields are architecturally 663 * UNKNOWN on reset. 664 * 665 * MDCR_EL2.HLP: Set to one so that event counter 666 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 667 * occurs on the increment that changes 668 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 669 * implemented. This bit is RES0 in versions of the 670 * architecture earlier than ARMv8.5, setting it to 1 671 * doesn't have any effect on them. 672 * 673 * MDCR_EL2.TTRF: Set to zero so that access to Trace 674 * Filter Control register TRFCR_EL1 at EL1 is not 675 * trapped to EL2. This bit is RES0 in versions of 676 * the architecture earlier than ARMv8.4. 677 * 678 * MDCR_EL2.HPMD: Set to one so that event counting is 679 * prohibited at EL2. This bit is RES0 in versions of 680 * the architecture earlier than ARMv8.1, setting it 681 * to 1 doesn't have any effect on them. 682 * 683 * MDCR_EL2.TPMS: Set to zero so that accesses to 684 * Statistical Profiling control registers from EL1 685 * do not trap to EL2. This bit is RES0 when SPE is 686 * not implemented. 687 * 688 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 689 * EL1 System register accesses to the Debug ROM 690 * registers are not trapped to EL2. 691 * 692 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 693 * System register accesses to the powerdown debug 694 * registers are not trapped to EL2. 695 * 696 * MDCR_EL2.TDA: Set to zero so that System register 697 * accesses to the debug registers do not trap to EL2. 698 * 699 * MDCR_EL2.TDE: Set to zero so that debug exceptions 700 * are not routed to EL2. 701 * 702 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 703 * Monitors. 704 * 705 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 706 * EL1 accesses to all Performance Monitors registers 707 * are not trapped to EL2. 708 * 709 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 710 * and EL1 accesses to the PMCR_EL0 or PMCR are not 711 * trapped to EL2. 712 * 713 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 714 * architecturally-defined reset value. 715 * 716 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 717 * owning exception level is NS-EL1 and, tracing is 718 * prohibited at NS-EL2. These bits are RES0 when 719 * FEAT_TRBE is not implemented. 720 */ 721 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 722 MDCR_EL2_HPMD) | 723 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 724 >> PMCR_EL0_N_SHIFT)) & 725 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 726 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 727 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 728 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 729 MDCR_EL2_TPMCR_BIT | 730 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 731 732 write_mdcr_el2(mdcr_el2); 733 734 /* 735 * Initialise HSTR_EL2. All fields are architecturally 736 * UNKNOWN on reset. 737 * 738 * HSTR_EL2.T<n>: Set all these fields to zero so that 739 * Non-secure EL0 or EL1 accesses to System registers 740 * do not trap to EL2. 741 */ 742 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 743 /* 744 * Initialise CNTHP_CTL_EL2. All fields are 745 * architecturally UNKNOWN on reset. 746 * 747 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 748 * physical timer and prevent timer interrupts. 749 */ 750 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 751 ~(CNTHP_CTL_ENABLE_BIT)); 752 } 753 manage_extensions_nonsecure(el2_unused, ctx); 754 } 755 756 cm_el1_sysregs_context_restore(security_state); 757 cm_set_next_eret_context(security_state); 758 } 759 760 #if CTX_INCLUDE_EL2_REGS 761 /******************************************************************************* 762 * Save EL2 sysreg context 763 ******************************************************************************/ 764 void cm_el2_sysregs_context_save(uint32_t security_state) 765 { 766 u_register_t scr_el3 = read_scr(); 767 768 /* 769 * Always save the non-secure and realm EL2 context, only save the 770 * S-EL2 context if S-EL2 is enabled. 771 */ 772 if ((security_state != SECURE) || 773 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 774 cpu_context_t *ctx; 775 776 ctx = cm_get_context(security_state); 777 assert(ctx != NULL); 778 779 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 780 } 781 } 782 783 /******************************************************************************* 784 * Restore EL2 sysreg context 785 ******************************************************************************/ 786 void cm_el2_sysregs_context_restore(uint32_t security_state) 787 { 788 u_register_t scr_el3 = read_scr(); 789 790 /* 791 * Always restore the non-secure and realm EL2 context, only restore the 792 * S-EL2 context if S-EL2 is enabled. 793 */ 794 if ((security_state != SECURE) || 795 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 796 cpu_context_t *ctx; 797 798 ctx = cm_get_context(security_state); 799 assert(ctx != NULL); 800 801 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 802 } 803 } 804 #endif /* CTX_INCLUDE_EL2_REGS */ 805 806 /******************************************************************************* 807 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 808 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 809 * updating EL1 and EL2 registers. Otherwise, it calls the generic 810 * cm_prepare_el3_exit function. 811 ******************************************************************************/ 812 void cm_prepare_el3_exit_ns(void) 813 { 814 #if CTX_INCLUDE_EL2_REGS 815 cpu_context_t *ctx = cm_get_context(NON_SECURE); 816 assert(ctx != NULL); 817 818 /* 819 * Currently some extensions are configured using 820 * direct register updates. Therefore, do this here 821 * instead of when setting up context. 822 */ 823 manage_extensions_nonsecure(0, ctx); 824 825 /* 826 * Set the NS bit to be able to access the ICC_SRE_EL2 827 * register when restoring context. 828 */ 829 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 830 831 /* Restore EL2 and EL1 sysreg contexts */ 832 cm_el2_sysregs_context_restore(NON_SECURE); 833 cm_el1_sysregs_context_restore(NON_SECURE); 834 cm_set_next_eret_context(NON_SECURE); 835 #else 836 cm_prepare_el3_exit(NON_SECURE); 837 #endif /* CTX_INCLUDE_EL2_REGS */ 838 } 839 840 /******************************************************************************* 841 * The next four functions are used by runtime services to save and restore 842 * EL1 context on the 'cpu_context' structure for the specified security 843 * state. 844 ******************************************************************************/ 845 void cm_el1_sysregs_context_save(uint32_t security_state) 846 { 847 cpu_context_t *ctx; 848 849 ctx = cm_get_context(security_state); 850 assert(ctx != NULL); 851 852 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 853 854 #if IMAGE_BL31 855 if (security_state == SECURE) 856 PUBLISH_EVENT(cm_exited_secure_world); 857 else 858 PUBLISH_EVENT(cm_exited_normal_world); 859 #endif 860 } 861 862 void cm_el1_sysregs_context_restore(uint32_t security_state) 863 { 864 cpu_context_t *ctx; 865 866 ctx = cm_get_context(security_state); 867 assert(ctx != NULL); 868 869 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 870 871 #if IMAGE_BL31 872 if (security_state == SECURE) 873 PUBLISH_EVENT(cm_entering_secure_world); 874 else 875 PUBLISH_EVENT(cm_entering_normal_world); 876 #endif 877 } 878 879 /******************************************************************************* 880 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 881 * given security state with the given entrypoint 882 ******************************************************************************/ 883 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 884 { 885 cpu_context_t *ctx; 886 el3_state_t *state; 887 888 ctx = cm_get_context(security_state); 889 assert(ctx != NULL); 890 891 /* Populate EL3 state so that ERET jumps to the correct entry */ 892 state = get_el3state_ctx(ctx); 893 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 894 } 895 896 /******************************************************************************* 897 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 898 * pertaining to the given security state 899 ******************************************************************************/ 900 void cm_set_elr_spsr_el3(uint32_t security_state, 901 uintptr_t entrypoint, uint32_t spsr) 902 { 903 cpu_context_t *ctx; 904 el3_state_t *state; 905 906 ctx = cm_get_context(security_state); 907 assert(ctx != NULL); 908 909 /* Populate EL3 state so that ERET jumps to the correct entry */ 910 state = get_el3state_ctx(ctx); 911 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 912 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 913 } 914 915 /******************************************************************************* 916 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 917 * pertaining to the given security state using the value and bit position 918 * specified in the parameters. It preserves all other bits. 919 ******************************************************************************/ 920 void cm_write_scr_el3_bit(uint32_t security_state, 921 uint32_t bit_pos, 922 uint32_t value) 923 { 924 cpu_context_t *ctx; 925 el3_state_t *state; 926 u_register_t scr_el3; 927 928 ctx = cm_get_context(security_state); 929 assert(ctx != NULL); 930 931 /* Ensure that the bit position is a valid one */ 932 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 933 934 /* Ensure that the 'value' is only a bit wide */ 935 assert(value <= 1U); 936 937 /* 938 * Get the SCR_EL3 value from the cpu context, clear the desired bit 939 * and set it to its new value. 940 */ 941 state = get_el3state_ctx(ctx); 942 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 943 scr_el3 &= ~(1UL << bit_pos); 944 scr_el3 |= (u_register_t)value << bit_pos; 945 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 946 } 947 948 /******************************************************************************* 949 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 950 * given security state. 951 ******************************************************************************/ 952 u_register_t cm_get_scr_el3(uint32_t security_state) 953 { 954 cpu_context_t *ctx; 955 el3_state_t *state; 956 957 ctx = cm_get_context(security_state); 958 assert(ctx != NULL); 959 960 /* Populate EL3 state so that ERET jumps to the correct entry */ 961 state = get_el3state_ctx(ctx); 962 return read_ctx_reg(state, CTX_SCR_EL3); 963 } 964 965 /******************************************************************************* 966 * This function is used to program the context that's used for exception 967 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 968 * the required security state 969 ******************************************************************************/ 970 void cm_set_next_eret_context(uint32_t security_state) 971 { 972 cpu_context_t *ctx; 973 974 ctx = cm_get_context(security_state); 975 assert(ctx != NULL); 976 977 cm_set_next_context(ctx); 978 } 979