| b15bab6b | 30-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1066 from islmit01/im/enable_cnp_bit
Enable CnP bit for ARMv8.2 CPUs |
| 80bcf981 | 09-Aug-2017 |
Eleanor Bonnici <Eleanor.bonnici@arm.com> |
CPU: Correct names of implementation-defined aux regs
At present, various CPU register macros that refer to CPUACTLR are named
ACTLR. This patch fixes that.
The previous register names are retained
CPU: Correct names of implementation-defined aux regs
At present, various CPU register macros that refer to CPUACTLR are named
ACTLR. This patch fixes that.
The previous register names are retained, but guarded by the
ERROR_DEPRECATED macro, so as not to break platforms that continue using
the old names.
Change-Id: Ia872196d81803f8f390b887d149e0fd054df519b
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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| e4e6c4be | 09-Aug-2017 |
Eleanor Bonnici <Eleanor.bonnici@arm.com> |
CPU: Make shifted constants unsigned
In order to avoid Undefined behavior, left operand in left-shift
expressions needs to be unsigned, and of sufficient size. The safest and
most consistent approac
CPU: Make shifted constants unsigned
In order to avoid Undefined behavior, left operand in left-shift
expressions needs to be unsigned, and of sufficient size. The safest and
most consistent approach is to use unsigned long long type.
Change-Id: I9612f16a6e6ea4c7df62a02497d862abf19b8e1b
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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| 9fce2725 | 07-Aug-2017 |
Isla Mitchell <isla.mitchell@arm.com> |
Enable CnP bit for ARMv8.2 CPUs
This patch enables the CnP (Common not Private) bit for secure page
tables so that multiple PEs in the same Inner Shareable domain can use
the same translation table
Enable CnP bit for ARMv8.2 CPUs
This patch enables the CnP (Common not Private) bit for secure page
tables so that multiple PEs in the same Inner Shareable domain can use
the same translation table entries for a given stage of translation in
a particular translation regime. This only takes effect when ARM
Trusted Firmware is built with ARM_ARCH_MINOR >= 2.
ARM Trusted Firmware Design has been updated to include a description
of this feature usage.
Change-Id: I698305f047400119aa1900d34c65368022e410b8
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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|
| f45e232a | 16-Aug-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Add macro to test for minimum architecture version
The macro concisely expresses and requires architecture version to be at
least as required by its arguments. This would be useful when extending
Tr
Add macro to test for minimum architecture version
The macro concisely expresses and requires architecture version to be at
least as required by its arguments. This would be useful when extending
Trusted Firmware functionality for future architecture revisions.
Replace similar usage in the current code base with the new macro.
Change-Id: I9dcd0aa71a663eabd02ed9632b8ce87611fa5a57
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| 54661cd2 | 24-Apr-2017 |
Summer Qin <summer.qin@arm.com> |
Add Trusted OS extra image parsing support for ARM standard platforms
Trusted OS may have extra images to be loaded. Load them one by one
and do the parsing. In this patch, ARM TF need to load up to
Add Trusted OS extra image parsing support for ARM standard platforms
Trusted OS may have extra images to be loaded. Load them one by one
and do the parsing. In this patch, ARM TF need to load up to 3 images
for optee os: header, pager and paged images. Header image is the info
about optee os and images. Pager image include pager code and data.
Paged image include the paging parts using virtual memory.
Change-Id: Ia3bcfa6d8a3ed7850deb5729654daca7b00be394
Signed-off-by: Summer Qin <summer.qin@arm.com>
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| 1862d620 | 10-Jul-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
lib: psci: early suspend handler for platforms
This patch adds an early suspend handler, that executes with
SMP and data cache enabled. This handler allows platforms to
perform any early actions dur
lib: psci: early suspend handler for platforms
This patch adds an early suspend handler, that executes with
SMP and data cache enabled. This handler allows platforms to
perform any early actions during the CPU suspend entry sequence.
This handler is optional and platforms can choose to implement it
depending on their needs. The `pwr_domain_suspend` handler still
exists and platforms can keep on using it without any side effects.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| de3d704d | 20-Jul-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Emphasize that TF only supports 4 KB granule size
At the moment, various parts of the Trusted Firmware code assume
that the granule size used is 4 KB. For example, the linker scripts
enforce 4 KB al
Emphasize that TF only supports 4 KB granule size
At the moment, various parts of the Trusted Firmware code assume
that the granule size used is 4 KB. For example, the linker scripts
enforce 4 KB alignment restrictions on some sections.
However, the ARMv8-A architecture allows 16 KB and 64 KB granule
sizes as well. Some other parts of the TF code, particularly the
architectural code and definitions, have been implemented with
this in mind and cater for all 3 cases.
This discrepancy creates some confusion as to what is effectively
supported in TF. This patch adds some code comments and clarification
in the documentation to make this limitation clearer.
Change-Id: I1f202369b240d8bed9d43d57ecd2a548c86c8598
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 0044231d | 19-Jul-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat lib: Fix some types
Fix the type length and signedness of some of the constants and
variables used in the translation table library.
This patch supersedes Pull Request #1018:
https://github.co
xlat lib: Fix some types
Fix the type length and signedness of some of the constants and
variables used in the translation table library.
This patch supersedes Pull Request #1018:
https://github.com/ARM-software/arm-trusted-firmware/pull/1018
Change-Id: Ibd45faf7a4fb428a0bf71c752551d35800212fb2
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| a9ad848c | 18-Jul-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat lib v2: Expose *_ctx() APIs
In a previous patch, the xlat_ctx_t type has been made public.
This patch now makes the *_ctx() APIs public.
Each API now has a *_ctx() variant. Most of them were a
xlat lib v2: Expose *_ctx() APIs
In a previous patch, the xlat_ctx_t type has been made public.
This patch now makes the *_ctx() APIs public.
Each API now has a *_ctx() variant. Most of them were already implemented
and this patch just makes them public. However, some of them were missing
so this patch introduces them.
Now that all these APIs are public, there's no good reason for splitting
them accross 2 files (xlat_tables_internal.c and xlat_tables_common.c).
Therefore, this patch moves all code into xlat_tables_internal.c and
removes xlat_tables_common.c. It removes it from the library's makefile
as well.
This last change introduces a compatibility break for platform ports
that specifically include the xlat_tables_common.c file instead of
including the library's Makefile. The UniPhier platform makefile has
been updated to now omit this file from the list of source files.
The prototype of mmap_add_region_ctx() has been slightly changed. The
mmap_region_t passed in argument needs to be constant because it gets
called from map_add(), which receives a constant region. The former
implementation of mmap_add() used to cast the const qualifier away,
which is not a good practice.
Also remove init_xlation_table(), which was a sub-function of
init_xlat_tables(). Now there's just init_xlat_tables() (and
init_xlat_tables_ctx()). Both names were too similar, which was
confusing. Besides, now that all the code is in a single file,
it's no longer needed to have 2 functions for that.
Change-Id: I4ed88c68e44561c3902fbebb89cb197279c5293b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 55c84964 | 10-Jul-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat lib v2: Export translation context as an opaque type
At the moment, the translation context type (xlat_ctx_t) is a private
type reserved for the internal usage of the translation table library.
xlat lib v2: Export translation context as an opaque type
At the moment, the translation context type (xlat_ctx_t) is a private
type reserved for the internal usage of the translation table library.
All exported APIs (implemented in xlat_tables_common.c) are wrappers
over the internal implementations that use such a translation context.
These wrappers unconditionally pass the current translation context
representing the memory mappings of the executing BL image. This means
that the caller has no control over which translation context the
library functions act on.
As a first step to make this code more flexible, this patch exports
the 'xlat_ctx_t' type. Note that, although the declaration of this type
is now public, its definition stays private. A macro is introduced to
statically allocate and initialize such a translation context.
The library now internally uses this macro to allocate the default
translation context for the running BL image.
Change-Id: Icece1cde4813fac19452c782b682c758142b1489
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 8933c34b | 19-May-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat lib: Reorganize architectural defs
Move the header files that provide translation tables architectural
definitions from the library v2 source files to the library include
directory. This allows
xlat lib: Reorganize architectural defs
Move the header files that provide translation tables architectural
definitions from the library v2 source files to the library include
directory. This allows to share these definitions between both
versions (v1 and v2) of the library.
Create a new header file that includes the AArch32 or AArch64
definitions based on the AARCH32 build flag, so that the library user
doesn't have to worry about handling it on their side.
Also repurpose some of the definitions the header files provide to
concentrate on the things that differ between AArch32 and AArch64.
As a result they now contain the following information:
- the first table level that allows block descriptors;
- the architectural limits of the virtual address space;
- the initial lookup level to cover the entire address space.
Additionally, move the XLAT_TABLE_LEVEL_MIN macro from
xlat_tables_defs.h to the AArch32/AArch64 architectural definitions.
This new organisation eliminates duplicated information in the AArch32
and AArch64 versions. It also decouples these architectural files from
any platform-specific information. Previously, they were dependent on
the address space size, which is platform-specific.
Finally, for the v2 of the library, move the compatibility code for
ADDR_SPACE_SIZE into a C file as it is not needed outside of this
file. For v1, this code hasn't been changed and stays in a header
file because it's needed by several files.
Change-Id: If746c684acd80eebf918abd3ab6e8481d004ac68
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 2a4b4b71 | 11-Jul-2017 |
Isla Mitchell <isla.mitchell@arm.com> |
Fix order of #includes
This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions in order to retain header groupings,
minimise changes to imported
Fix order of #includes
This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions in order to retain header groupings,
minimise changes to imported headers, and where there are headers within
the #if and #ifndef statements.
Change-Id: I65085a142ba6a83792b26efb47df1329153f1624
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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|
| d70a7d0c | 28-Jun-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #978 from etienne-lms/minor-build
Minor build fixes |
| 9151ac0e | 23-Jun-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #997 from dp-arm/dp/spe
aarch64: Enable Statistical Profiling Extensions for lower ELs |
| ee881c15 | 23-Jun-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #995 from davidcunado-arm/dc/init_reg
Fully initialise essential control registers |
| 2ed7b71e | 23-Jun-2017 |
Etienne Carriere <etienne.carriere@st.com> |
context_mgmt: declare extern cm_set_next_context() for AArch32
This change avoids warning when setting -Wmissing-prototypes to
compile bl1_context_mgmt.c.
Reported-by: Yann Gautier <yann.gautier@st
context_mgmt: declare extern cm_set_next_context() for AArch32
This change avoids warning when setting -Wmissing-prototypes to
compile bl1_context_mgmt.c.
Reported-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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|
| 55074083 | 07-Jun-2017 |
Etienne Carriere <etienne.carriere@st.com> |
bl: security_state should be of type unsigned int
security_state is either 0 or 1. Prevent sign conversion potential
error (setting -Werror=sign-conversion results in a build error).
Signed-off-by:
bl: security_state should be of type unsigned int
security_state is either 0 or 1. Prevent sign conversion potential
error (setting -Werror=sign-conversion results in a build error).
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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|
| 6f512a3d | 20-Jun-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
aarch32: Apply workaround for errata 813419 of Cortex-A57
TLBI instructions for monitor mode won't have the desired effect under
specific circumstances in Cortex-A57 r0p0. The workaround is to
execu
aarch32: Apply workaround for errata 813419 of Cortex-A57
TLBI instructions for monitor mode won't have the desired effect under
specific circumstances in Cortex-A57 r0p0. The workaround is to
execute DSB and TLBI twice each time.
Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.
The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.
NOTE: This workaround is present in AArch64 TF and already enabled by
default on Juno.
Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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|
| d832aee9 | 23-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
aarch64: Enable Statistical Profiling Extensions for lower ELs
SPE is only supported in non-secure state. Accesses to SPE specific
registers from SEL1 will trap to EL3. During a world switch, befo
aarch64: Enable Statistical Profiling Extensions for lower ELs
SPE is only supported in non-secure state. Accesses to SPE specific
registers from SEL1 will trap to EL3. During a world switch, before
`TTBR` is modified the SPE profiling buffers are drained. This is to
avoid a potential invalid memory access in SEL1.
SPE is architecturally specified only for AArch64.
Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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| 18f2efd6 | 13-Apr-2017 |
David Cunado <david.cunado@arm.com> |
Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the res
Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
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|
| f9688f27 | 13-Jun-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
aarch32: Fix L2CTRL definition for Cortex A57 and A72
Fixes ARM-software/tf-issues#495
Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@a
aarch32: Fix L2CTRL definition for Cortex A57 and A72
Fixes ARM-software/tf-issues#495
Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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| 3749d853 | 05-Jun-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
aarch32: Implement errata workarounds for Cortex A53
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2
Sig
aarch32: Implement errata workarounds for Cortex A53
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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| 030567e6 | 26-May-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
include: add U()/ULL() macros for constants
This patch uses the U() and ULL() macros for constants, to fix some
of the signed-ness defects flagged by the MISRA scanner.
Signed-off-by: Varun Wadekar
include: add U()/ULL() macros for constants
This patch uses the U() and ULL() macros for constants, to fix some
of the signed-ness defects flagged by the MISRA scanner.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 6176b4fc | 18-May-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Add U() macro to share constants between C and other sources
This patch adds the U(_x) macros to utils_def.h to allow constants to
be shared between C and other sources.
Signed-off-by: Varun Wadeka
Add U() macro to share constants between C and other sources
This patch adds the U(_x) macros to utils_def.h to allow constants to
be shared between C and other sources.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|