1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CSS_DEF_H__ 8 #define __CSS_DEF_H__ 9 10 #include <arm_def.h> 11 #include <tzc400.h> 12 13 /************************************************************************* 14 * Definitions common to all ARM Compute SubSystems (CSS) 15 *************************************************************************/ 16 #define NSROM_BASE 0x1f000000 17 #define NSROM_SIZE 0x00001000 18 19 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 20 #define CSS_DEVICE_BASE 0x20000000 21 #define CSS_DEVICE_SIZE 0x0e000000 22 23 #define NSRAM_BASE 0x2e000000 24 #define NSRAM_SIZE 0x00008000 25 26 /* System Security Control Registers */ 27 #define SSC_REG_BASE 0x2a420000 28 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 29 30 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 31 #define CSS_NIC400_SLAVE_BOOTSECURE 8 32 33 /* Interrupt handling constants */ 34 #define CSS_IRQ_MHU 69 35 #define CSS_IRQ_GPU_SMMU_0 71 36 #define CSS_IRQ_TZC 80 37 #define CSS_IRQ_TZ_WDOG 86 38 #define CSS_IRQ_SEC_SYS_TIMER 91 39 40 /* 41 * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a 42 * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. 43 */ 44 #define CSS_G1S_IRQS CSS_IRQ_MHU, \ 45 CSS_IRQ_GPU_SMMU_0, \ 46 CSS_IRQ_TZC, \ 47 CSS_IRQ_TZ_WDOG, \ 48 CSS_IRQ_SEC_SYS_TIMER 49 50 /* 51 * The lower Non-secure MHU channel is being used for SCMI for ARM Trusted 52 * Firmware. 53 * TODO: Move SCMI to Secure channel once the migration to SCMI in SCP is 54 * complete. 55 */ 56 #define MHU_CPU_INTR_L_SET_OFFSET 0x108 57 #define MHU_CPU_INTR_H_SET_OFFSET 0x128 58 #define CSS_SCMI_PAYLOAD_BASE (NSRAM_BASE + 0x500) 59 #define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_L_SET_OFFSET 60 61 /* 62 * SCP <=> AP boot configuration 63 * 64 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 65 * the start of the Trusted SRAM. 66 * 67 * Note that the value stored at this address is only valid at boot time, before 68 * the SCP_BL2 image is transferred to SCP. 69 */ 70 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 71 72 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 73 CSS_DEVICE_BASE, \ 74 CSS_DEVICE_SIZE, \ 75 MT_DEVICE | MT_RW | MT_SECURE) 76 77 #define CSS_MAP_NSRAM MAP_REGION_FLAT( \ 78 NSRAM_BASE, \ 79 NSRAM_SIZE, \ 80 MT_DEVICE | MT_RW | MT_SECURE) 81 82 /* Platform ID address */ 83 #define SSC_VERSION_OFFSET 0x040 84 85 #define SSC_VERSION_CONFIG_SHIFT 28 86 #define SSC_VERSION_MAJOR_REV_SHIFT 24 87 #define SSC_VERSION_MINOR_REV_SHIFT 20 88 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 89 #define SSC_VERSION_PART_NUM_SHIFT 0x0 90 #define SSC_VERSION_CONFIG_MASK 0xf 91 #define SSC_VERSION_MAJOR_REV_MASK 0xf 92 #define SSC_VERSION_MINOR_REV_MASK 0xf 93 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 94 #define SSC_VERSION_PART_NUM_MASK 0xfff 95 96 /* SSC debug configuration registers */ 97 #define SSC_DBGCFG_SET 0x14 98 #define SSC_DBGCFG_CLR 0x18 99 100 #define SPIDEN_INT_CLR_SHIFT 6 101 #define SPIDEN_SEL_SET_SHIFT 7 102 103 #ifndef __ASSEMBLY__ 104 105 /* SSC_VERSION related accessors */ 106 107 /* Returns the part number of the platform */ 108 #define GET_SSC_VERSION_PART_NUM(val) \ 109 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 110 SSC_VERSION_PART_NUM_MASK) 111 112 /* Returns the configuration number of the platform */ 113 #define GET_SSC_VERSION_CONFIG(val) \ 114 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 115 SSC_VERSION_CONFIG_MASK) 116 117 #endif /* __ASSEMBLY__ */ 118 119 /************************************************************************* 120 * Required platform porting definitions common to all 121 * ARM Compute SubSystems (CSS) 122 ************************************************************************/ 123 124 /* 125 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 126 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 127 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 128 * an SCP_BL2/SCP_BL2U image. 129 */ 130 #if CSS_LOAD_SCP_IMAGES 131 132 #if ARM_BL31_IN_DRAM 133 #error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config" 134 #endif 135 136 /* 137 * Load address of SCP_BL2 in CSS platform ports 138 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1 139 * rw data. Once SCP_BL2 is transferred to the SCP, it is discarded and BL31 140 * is loaded over the top. 141 */ 142 #define SCP_BL2_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE) 143 #define SCP_BL2_LIMIT BL1_RW_BASE 144 145 #define SCP_BL2U_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE) 146 #define SCP_BL2U_LIMIT BL1_RW_BASE 147 #endif /* CSS_LOAD_SCP_IMAGES */ 148 149 /* Load address of Non-Secure Image for CSS platform ports */ 150 #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 151 152 /* TZC related constants */ 153 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 154 155 /* Trusted mailbox base address common to all CSS */ 156 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 157 158 /* 159 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 160 * command 161 */ 162 #define CSS_CLUSTER_PWR_STATE_ON 0 163 #define CSS_CLUSTER_PWR_STATE_OFF 3 164 165 #define CSS_CPU_PWR_STATE_ON 1 166 #define CSS_CPU_PWR_STATE_OFF 0 167 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 168 169 #endif /* __CSS_DEF_H__ */ 170