fix(cpus): workaround for Neoverse V2 erratum 2779510

Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of C

fix(cpus): workaround for Neoverse V2 erratum 2779510

Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of CPUACTLR3_EL1 which might have a small impact on
power and negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80

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fix(cpus): workaround for Neoverse V2 erratum 2719105

Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.

The erratum is avoided by setting CP

fix(cpus): workaround for Neoverse V2 erratum 2719105

Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.

The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba

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fix(cpus): workaround for Neoverse V2 erratum 2331132

Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b

fix(cpus): workaround for Neoverse V2 erratum 2331132

Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register
which will place the data prefetcher in the most conservative mode
instead of disabling it.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1

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fix(cpus): workaround for Cortex-X3 erratum 2742421

Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56

fix(cpus): workaround for Cortex-X3 erratum 2742421

Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b

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feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.co

feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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feat(cpus): add support for Gelas CPU

This patch adds the necessary CPU library code to support the Gelas CPU

Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <j

feat(cpus): add support for Gelas CPU

This patch adds the necessary CPU library code to support the Gelas CPU

Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge "chore: update to use Arm word across TF-A" into integration

chore: update to use Arm word across TF-A

Align entire TF-A to use Arm in copyright header.

Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.co

chore: update to use Arm word across TF-A

Align entire TF-A to use Arm in copyright header.

Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpus): make revision procedure call optional

For runtime errata, we should avoid generating calls to
`cpu_get_rev_var` unless its necessary. Make the path that generates
this call parameterized

feat(cpus): make revision procedure call optional

For runtime errata, we should avoid generating calls to
`cpu_get_rev_var` unless its necessary. Make the path that generates
this call parameterized, and cache the result in a temporary register to
allow future calls that go down the alternate path to retrieve the cache
CPU revision.

Change-Id: I9882ede76568fbd9a7ccd4caa74eff0c66a7b20e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "ar/errata_refactor" into integration

* changes:
fix(cpus): workaround for Neoverse N2 erratum 2779511
fix(errata-abi): added Neoverse N2 to Errata ABI list
fix(cpus):

Merge changes from topic "ar/errata_refactor" into integration

* changes:
fix(cpus): workaround for Neoverse N2 erratum 2779511
fix(errata-abi): added Neoverse N2 to Errata ABI list
fix(cpus): workaround for Neoverse N2 erratum 2743014
fix(docs): updated certain Neoverse N2 erratum status in docs
refactor(cpus): convert Neoverse N2 to use CPU helpers
refactor(cpus): convert Neoverse N2 to framework
refactor(cpus): reorder Neoverse N2 errata by ascending order

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refactor(cpus): convert Neoverse V1 to use CPU helpers

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idb4b47982278cda93a7c0f0a49dfceb75b8d88e4

fix(cpus): workaround for Neoverse N2 erratum 2779511

Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CP

fix(cpus): workaround for Neoverse N2 erratum 2779511

Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CPUACTLR3_EL1

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iaa0e30de8473ecb1df1fcca3a45904aac2e419b3

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fix(cpus): workaround for Neoverse N2 erratum 2743014

Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1

fix(cpus): workaround for Neoverse N2 erratum 2743014

Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie7e1be5dea9d1f74738f9fed0fb58bfd41763192

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refactor(cpus): convert the Cortex-A76 to use the errata framework

Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Build

refactor(cpus): convert the Cortex-A76 to use the errata framework

Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.

Change-Id: I126f09de44b16e8bbb7e32477b880b4650eef23b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(cpus): convert the Cortex-A510 to use cpu helpers

Change-Id: I6d26092525c2d5255a741515071ee7ed873aa52d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

feat(cpus): add errata framework helpers

Adding an helper macro for bit field insert(bic) instruction
to group all the operations related to it.

Change-Id: Idfd06c7f38faf52090f62b458d2d96c2682f63fe

feat(cpus): add errata framework helpers

Adding an helper macro for bit field insert(bic) instruction
to group all the operations related to it.

Change-Id: Idfd06c7f38faf52090f62b458d2d96c2682f63fe
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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chore: rename hayes to a520

Rename Cortex-hayes to Cortes-A520

Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

chore: rename hunter to a720

Rename cortex_hunter to cortex_a720

Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

chore: rename hunter_elp to cortex-x4

Rename hunter_elp to cortex-x4

Change-Id: I78c8c009d7bee14b4793dc1d950ed81273216831
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(cpus): add support for hermes cpu

Adding basic CPU library code to support the Hermes CPU.

Change-Id: I61946033fe5fafb56ceb2d14d4c796d85b30457e
Signed-off-by: Govindraj Raja <govindraj.raja@ar

feat(cpus): add support for hermes cpu

Adding basic CPU library code to support the Hermes CPU.

Change-Id: I61946033fe5fafb56ceb2d14d4c796d85b30457e
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpus): add more errata framework helpers

Figuring out the naming format of errata is annoying, so add a shorthand
for the custom checker functions. Also add some more semantic macros
instead of

feat(cpus): add more errata framework helpers

Figuring out the naming format of errata is annoying, so add a shorthand
for the custom checker functions. Also add some more semantic macros
instead of passing around constants.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibdcf72146738026df4ebd047bfb30790fd4a1053

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Merge "chore: rename Makalu to Cortex-A715" into integration

chore: rename Makalu to Cortex-A715

Change-Id: I017c955cb643e2befb6b01e1b5a07c22172b08b9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

feat(cpus): wrappers to propagate AArch32 errata info

AArch32 is not being ported to the errata framework. However, the
runtime errata list is needed at runtime for the upcoming errata ABI.
Add wrap

feat(cpus): wrappers to propagate AArch32 errata info

AArch32 is not being ported to the errata framework. However, the
runtime errata list is needed at runtime for the upcoming errata ABI.
Add wrappers to populate this information and make it accessible in the
same way as AArch64.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I084720f34d6ed4e00e94b09babd3c90a5393298a

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feat(cpus): add a way to automatically report errata

Using the errata framework per-cpu data structure, errata can all be
reported automatically through a single standard errata reporter which
can r

feat(cpus): add a way to automatically report errata

Using the errata framework per-cpu data structure, errata can all be
reported automatically through a single standard errata reporter which
can replace the cpu-specific ones.

This reporter can also enforce the ordering requirement of errata.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I7d2d5ac5bcb9d21aed0d560d7d23919a323ffdab

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