1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 30 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 31workaround_reset_end cortex_a720, ERRATUM(2940794) 32 33check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) 34 35workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 36#if IMAGE_BL31 37 /* 38 * The Cortex A720 generic vectors are overridden to apply errata 39 * mitigation on exception entry from lower ELs. 40 */ 41 override_vector_table wa_cve_vbar_cortex_a720 42#endif /* IMAGE_BL31 */ 43workaround_reset_end cortex_a720, CVE(2022, 23960) 44 45check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 46 47cpu_reset_func_start cortex_a720 48 /* Disable speculative loads */ 49 msr SSBS, xzr 50cpu_reset_func_end cortex_a720 51 52 /* ---------------------------------------------------- 53 * HW will do the cache maintenance while powering down 54 * ---------------------------------------------------- 55 */ 56func cortex_a720_core_pwr_dwn 57 /* --------------------------------------------------- 58 * Enable CPU power down bit in power control register 59 * --------------------------------------------------- 60 */ 61 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 62 63 isb 64 ret 65endfunc cortex_a720_core_pwr_dwn 66 67errata_report_shim cortex_a720 68 69 /* --------------------------------------------- 70 * This function provides Cortex A720-specific 71 * register information for crash reporting. 72 * It needs to return with x6 pointing to 73 * a list of register names in ascii and 74 * x8 - x15 having values of registers to be 75 * reported. 76 * --------------------------------------------- 77 */ 78.section .rodata.cortex_a720_regs, "aS" 79cortex_a720_regs: /* The ascii list of register names to be reported */ 80 .asciz "cpuectlr_el1", "" 81 82func cortex_a720_cpu_reg_dump 83 adr x6, cortex_a720_regs 84 mrs x8, CORTEX_A720_CPUECTLR_EL1 85 ret 86endfunc cortex_a720_cpu_reg_dump 87 88declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 89 cortex_a720_reset_func, \ 90 cortex_a720_core_pwr_dwn 91