1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a715.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818 30 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 31workaround_reset_end cortex_a715, ERRATUM(2331818) 32 33check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0) 34 35workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187 36 /* GCR_EL1 is only present with FEAT_MTE2. */ 37 mrs x1, ID_AA64PFR1_EL1 38 ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 39 cmp x0, #MTE_IMPLEMENTED_ELX 40 bne #1f 41 sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT 42 431: 44 /* Mitigation upon ERETAA and ERETAB. */ 45 mov x0, #2 46 msr CORTEX_A715_CPUPSELR_EL3, x0 47 isb 48 ldr x0, =0xd69f0bff 49 msr CORTEX_A715_CPUPOR_EL3, x0 50 ldr x0, =0xfffffbff 51 msr CORTEX_A715_CPUPMR_EL3, x0 52 mov x1, #0 53 orr x1, x1, #(1<<0) 54 orr x1, x1, #(3<<4) 55 orr x1, x1, #(0xf<<6) 56 orr x1, x1, #(1<<13) 57 orr x1, x1, #(1<<53) 58 msr CORTEX_A715_CPUPCR_EL3, x1 59workaround_reset_end cortex_a715, ERRATUM(2344187) 60 61check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0) 62 63workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 64 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) 65workaround_reset_end cortex_a715, ERRATUM(2420947) 66 67check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0) 68 69workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 70 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) 71workaround_reset_end cortex_a715, ERRATUM(2429384) 72 73check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0) 74 75workaround_runtime_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034 76 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26) 77workaround_runtime_end cortex_a715, ERRATUM(2561034), NO_ISB 78 79check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0) 80 81workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 82#if IMAGE_BL31 83 /* 84 * The Cortex-A715 generic vectors are overridden to apply errata 85 * mitigation on exception entry from lower ELs. 86 */ 87 override_vector_table wa_cve_vbar_cortex_a715 88#endif /* IMAGE_BL31 */ 89workaround_reset_end cortex_a715, CVE(2022, 23960) 90 91check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 92 93cpu_reset_func_start cortex_a715 94 /* Disable speculative loads */ 95 msr SSBS, xzr 96cpu_reset_func_end cortex_a715 97 98 /* ---------------------------------------------------- 99 * HW will do the cache maintenance while powering down 100 * ---------------------------------------------------- 101 */ 102func cortex_a715_core_pwr_dwn 103 /* --------------------------------------------------- 104 * Enable CPU power down bit in power control register 105 * --------------------------------------------------- 106 */ 107 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 108 orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 109 msr CORTEX_A715_CPUPWRCTLR_EL1, x0 110 isb 111 ret 112endfunc cortex_a715_core_pwr_dwn 113 114errata_report_shim cortex_a715 115 116 /* --------------------------------------------- 117 * This function provides Cortex-A715 specific 118 * register information for crash reporting. 119 * It needs to return with x6 pointing to 120 * a list of register names in ascii and 121 * x8 - x15 having values of registers to be 122 * reported. 123 * --------------------------------------------- 124 */ 125.section .rodata.cortex_a715_regs, "aS" 126cortex_a715_regs: /* The ascii list of register names to be reported */ 127 .asciz "cpuectlr_el1", "" 128 129func cortex_a715_cpu_reg_dump 130 adr x6, cortex_a715_regs 131 mrs x8, CORTEX_A715_CPUECTLR_EL1 132 ret 133endfunc cortex_a715_cpu_reg_dump 134 135declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ 136 cortex_a715_reset_func, \ 137 cortex_a715_core_pwr_dwn 138