| af26d7d6 | 10-Jan-2022 |
Tamas Ban <tamas.ban@arm.com> |
feat(drivers/arm/mhu): add MHU driver
The Arm Message Handling Unit (MHU) is a mailbox controller used to
communicate with other processing element(s). Adding a driver to
enable the communication:
-
feat(drivers/arm/mhu): add MHU driver
The Arm Message Handling Unit (MHU) is a mailbox controller used to
communicate with other processing element(s). Adding a driver to
enable the communication:
- Adding generic MHU driver interface,
- Adding MHU_v2_x driver.
Driver supports:
- Discovering available MHU channels,
- Sending / receiving words over MHU channels,
- Signaling happens over a dedicated channel.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: I41a5b968f6b8319cdbdf7907d70bd8837839862e
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| efceb6be | 06-May-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Iaf21883b,I523c5d57,I57164923 into integration
* changes:
fix(ufs): read and write attribute based on spec
fix(ufs): disables controller if enabled
refactor(ufs): adds a function
Merge changes Iaf21883b,I523c5d57,I57164923 into integration
* changes:
fix(ufs): read and write attribute based on spec
fix(ufs): disables controller if enabled
refactor(ufs): adds a function for fdeviceinit
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| 52a314af | 04-Feb-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
feat(smmu): configure SMMU Root interface
This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions
feat(smmu): configure SMMU Root interface
This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions originated from a non-secure or secure device upstream
to an SMMU. It re-uses the boot time GPT base address and configuration
programmed on the PE.
The root register file offset is platform dependent and has to be
supplied on a model command line.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f889be6b7afc2afb4d1d147c5c1c3ea68f32e07
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| b3f03b20 | 21-Mar-2022 |
anans <anans@google.com> |
fix(ufs): disables controller if enabled
ufs controller needs to be disabled if already enabled, without
this we noticed a crash at linkstartup during reinit
Signed-off-by: anans <anans@google.com>
fix(ufs): disables controller if enabled
ufs controller needs to be disabled if already enabled, without
this we noticed a crash at linkstartup during reinit
Signed-off-by: anans <anans@google.com>
Change-Id: I523c5d57c1d34f6404a6368ee3f364fbffd2e542
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| 50593e69 | 21-Mar-2022 |
anans <anans@google.com> |
refactor(ufs): adds a function for fdeviceinit
time taken for device init varies based on different devices,
instead of waiting for 200ms - we can poll on fdevice init
until it gets cleared, similar
refactor(ufs): adds a function for fdeviceinit
time taken for device init varies based on different devices,
instead of waiting for 200ms - we can poll on fdevice init
until it gets cleared, similar to what linux does
Change-Id: I571649231732fde0cd6d5be89b6f14fe905fcaff
Signed-off-by: anans <anans@google.com>
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| 6a1c17c7 | 26-Jan-2022 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs
The following SMIDs are disabled by default.
* GICD: MBIST REQ error and GICD FMU ClkGate override
* PPI: MBIST REQ error and PPI FMU ClkGate overr
feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs
The following SMIDs are disabled by default.
* GICD: MBIST REQ error and GICD FMU ClkGate override
* PPI: MBIST REQ error and PPI FMU ClkGate override
* ITS: MBIST REQ error and ITS FMU ClkGate override
This patch explicitly enables them during the FMU init sequence.
Change-Id: I573e64786e3318d4cbcd07d0a1caf25f8e6e9200
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 3f0094c1 | 25-Jan-2022 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(gic600ae_fmu): disable SMID for unavailable blocks
This patch updates the gic600_fmu_init function to disable all safety
mechanisms for a block ID that is not present on the platform. All
safet
feat(gic600ae_fmu): disable SMID for unavailable blocks
This patch updates the gic600_fmu_init function to disable all safety
mechanisms for a block ID that is not present on the platform. All
safety mechanisms for GIC-600AE are enabled by default and should be
disabled for blocks that are not present on the platform to avoid
false positive RAS errors.
Change-Id: I52dc3bee9a8b49fd2e51d7ed851fdc803a48e6e3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 308dce40 | 24-Jan-2022 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(gic600ae_fmu): introduce support for RAS error handling
The GIC-600AE uses a range of RAS features for all RAMs, which include
SECDED, ECC, and Scrub, software and bus error reporting. The GIC
feat(gic600ae_fmu): introduce support for RAS error handling
The GIC-600AE uses a range of RAS features for all RAMs, which include
SECDED, ECC, and Scrub, software and bus error reporting. The GIC makes
all necessary information available to software through Armv8.2 RAS
architecture compliant register space.
This patch introduces support to probe the FMU_ERRGSR register to find
the right error record. Once the correct record is identified, the
"handler" function queries the FMU_ERR<m>STATUS register to further
identify the block ID, safety mechanism and the architecturally defined
primary error code. The description of the error is displayed on the
console to simplify debug.
Change-Id: I7e543664b74457afee2da250549f4c3d9beb1a03
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 9755fd2e | 17-Jan-2021 |
Biwen Li <biwen.li@nxp.com> |
feat(nxp-gic): add some macros definition for gicv3
Add macros as follows,
- GICD_ISENABLER_1
- GICD_ISENABLER_3
- GICD_ICENABLER_1
- GICD_ICENABLER_3
Signed-off-by: Biwen Li <biwen
feat(nxp-gic): add some macros definition for gicv3
Add macros as follows,
- GICD_ISENABLER_1
- GICD_ISENABLER_3
- GICD_ICENABLER_1
- GICD_ICENABLER_3
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ia522ab4bc496d9a47613a49829b65db96e2b1279
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| d60364d4 | 18-Feb-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp-crypto): add chassis 3 support
Add Chassis 3 support for CAAM driver.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ied26dd3881489a03017a45966888a61a0813492c |
| df02aeee | 05-Jan-2021 |
Biwen Li <biwen.li@nxp.com> |
feat(nxp-dcfg): add Chassis 3 support
Add support for Chassis 3.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I85cf68d4f1db81bf344e34dce13799
feat(nxp-dcfg): add Chassis 3 support
Add support for Chassis 3.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I85cf68d4f1db81bf344e34dce13799ae173aa23a
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| 5278ec3f | 18-Jan-2022 |
Yann Gautier <yann.gautier@st.com> |
feat(st-pmic): add pmic_voltages_init() function
This new function pmic_voltages_init() is used to set the minimum value
for STM32MP13 VDDCPU and VDDCORE regulators. This value is retrieved
from dev
feat(st-pmic): add pmic_voltages_init() function
This new function pmic_voltages_init() is used to set the minimum value
for STM32MP13 VDDCPU and VDDCORE regulators. This value is retrieved
from device tree.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ibbe237cb5dccc1fddf92e07ffd3955048ff82075
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| 9be88e75 | 11-Mar-2020 |
Gabriel Fernandez <gabriel.fernandez@st.com> |
feat(st-clock): add clock driver for STM32MP13
Add new clock driver for STM32MP13. Split the include file to manage
either STM32MP13 or STM32MP15.
Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e9
feat(st-clock): add clock driver for STM32MP13
Add new clock driver for STM32MP13. Split the include file to manage
either STM32MP13 or STM32MP15.
Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e985
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
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| 92537e17 | 28-Feb-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(measured-boot): add RMM entry to event_log_metadata" into integration |
| f4e3e1e8 | 10-Jan-2022 |
Tamas Ban <tamas.ban@arm.com> |
fix(measured-boot): add RMM entry to event_log_metadata
Platforms which support Realm world cannot boot up
properly if measured boot is enabled at build time.
An assertions occurs due to the missing
fix(measured-boot): add RMM entry to event_log_metadata
Platforms which support Realm world cannot boot up
properly if measured boot is enabled at build time.
An assertions occurs due to the missing RMM entry
in the event_log_metadata array.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I172f10a440797f7c9e1bc79dc72242b40c2521ea
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| fa7fdfab | 18-Nov-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
fix(nxp-crypto): refine code to avoid hang issue for some of toolchain
bitfield structure maybe has strict-aliasing issue for some compiler,
for example the old code has hang issue for yocto 3.4 too
fix(nxp-crypto): refine code to avoid hang issue for some of toolchain
bitfield structure maybe has strict-aliasing issue for some compiler,
for example the old code has hang issue for yocto 3.4 toolchain, so
refine the code to avoid to use bitfield structure.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6b6d7597311240dd6d6b8ca4ce508c69332f9c68
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| 0e38ff2a | 04-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(st): update the security based on new compatible" into integration |
| a7521bd5 | 01-Dec-2021 |
Stephan Gerhold <stephan@gerhold.net> |
feat(gic): allow overriding GICD_PIDR2_GICV2 address
Older Qualcomm SoCs seem to have a custom Qualcomm implementation of
the GICv2 specification. It's mostly compliant but unfortunately it
looks li
feat(gic): allow overriding GICD_PIDR2_GICV2 address
Older Qualcomm SoCs seem to have a custom Qualcomm implementation of
the GICv2 specification. It's mostly compliant but unfortunately it
looks like a mistake was made with the GICD_PIDR registers. PIDR2 is
defined to be at offset 0xFE8, but the Qualcomm implementation has it
at 0xFD8.
It looks like the entire PIDR0-3/4-7 block is swapped compared to the
ARM implementation: PIDR0 starts at 0xFD0 (instead of 0xFE0)
and PIDR4 starts at 0xFE0 (instead of 0xFD0).
Actually this only breaks a single assert in gicv2_main.c that checks
the GIC version: assert((gic_version == ARCH_REV_GICV2) ...
In release mode everything seems to work correctly.
To keep the code generic, allow affected platforms to override the
GICD_PIDR2_GICV2 register address in platform_def.h. Since this header
is typically included very early (e.g. from assert.h), add an #ifndef
so the definitions from platform_def.h takes priority.
Change-Id: I2929a8c1726f8d751bc28796567eb30b81eca2fe
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
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| 812daf91 | 15-Dec-2020 |
Lionel Debieve <lionel.debieve@st.com> |
feat(st): update the security based on new compatible
From the new binding, the RCC become secured based on the new
compatible. This must be done only from the secure OS initialisation.
Signed-off-
feat(st): update the security based on new compatible
From the new binding, the RCC become secured based on the new
compatible. This must be done only from the secure OS initialisation.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I7f0a62f22bfcca638ddaefc9563df00f89f01653
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| 53584e1d | 21-Sep-2021 |
Fabien Dessenne <fabien.dessenne@foss.st.com> |
feat(st-gpio): allow to set a gpio in output mode
Allow to set a gpio in output mode from the device tree.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: Ic483324bc5fe916a6
feat(st-gpio): allow to set a gpio in output mode
Allow to set a gpio in output mode from the device tree.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: Ic483324bc5fe916a60df05f74706bd1da4d08aa5
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| 417196fa | 21-Sep-2021 |
Fabien Dessenne <fabien.dessenne@foss.st.com> |
refactor(st-gpio): code improvements
No functional, change, but some improvements:
- Declare set_gpio() as static (only called locally)
- Handle the type ('open-drain') property independently from t
refactor(st-gpio): code improvements
No functional, change, but some improvements:
- Declare set_gpio() as static (only called locally)
- Handle the type ('open-drain') property independently from the
mode one.
- Replace mmio_clrbits_32() + mmio_setbits_32() with
mmio_clrsetbits_32().
- Add a missing log
- Add missing U() in macro definitions
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: I1a79609609ac8e8001127ebefdb81def573f76fa
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| 072d7532 | 20-May-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
refactor(st-drivers): improve BSEC driver
Rename driver file to BSEC2.
Split header file in IP and feature parts.
Add functions to access BSEC scratch register.
Several corrections and improvements.
refactor(st-drivers): improve BSEC driver
Rename driver file to BSEC2.
Split header file in IP and feature parts.
Add functions to access BSEC scratch register.
Several corrections and improvements.
Probe the driver earlier, especially to check debug features.
Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 591d80c8 | 04-Dec-2019 |
Lionel Debieve <lionel.debieve@st.com> |
refactor(st-clock): update STGEN management
Rework STGEN config function, and move it to stm32mp_clkfunc.c file.
Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6
Signed-off-by: Lionel Debieve <
refactor(st-clock): update STGEN management
Rework STGEN config function, and move it to stm32mp_clkfunc.c file.
Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 2444d231 | 19-Jan-2022 |
Yann Gautier <yann.gautier@st.com> |
refactor(st-clock): use refcnt instead of secure status
Rework the internal functions __stm32mp1_clk_enable/disable to check for
reference count instead of secure status for a clock.
Some functions
refactor(st-clock): use refcnt instead of secure status
Rework the internal functions __stm32mp1_clk_enable/disable to check for
reference count instead of secure status for a clock.
Some functions now unused can be removed.
Change-Id: Ie4359110d7144229f85c961dcd5a019222c3fd25
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 9adce87e | 01-Dec-2021 |
Sughosh Ganu <sughosh.ganu@linaro.org> |
feat(fwu): add a function to pass metadata structure to platforms
Add a helper function to pass the metadata structure to the
platforms. Platforms can then read the metadata structure and pass the
b
feat(fwu): add a function to pass metadata structure to platforms
Add a helper function to pass the metadata structure to the
platforms. Platforms can then read the metadata structure and pass the
boot index value, i.e. the bank(partition) from which the firmware
images were booted, to the Update Agent.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I571179b9baa0fbc4d0f08d7a6e3b50c0c7165c5c
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