1 /* 2 * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <common/debug.h> 11 #include <drivers/console.h> 12 #include <drivers/generic_delay_timer.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_mmu_helpers.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 #include <plat/common/platform.h> 17 18 #include <msm8916_mmap.h> 19 #include <platform_def.h> 20 #include <uartdm_console.h> 21 22 static const mmap_region_t msm8916_mmap[] = { 23 MAP_REGION_FLAT(PCNOC_BASE, PCNOC_SIZE, 24 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), 25 MAP_REGION_FLAT(APCS_BASE, APCS_SIZE, 26 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), 27 {}, 28 }; 29 30 static struct { 31 entry_point_info_t bl32; 32 entry_point_info_t bl33; 33 } image_ep_info = { 34 /* BL32 entry point */ 35 SET_STATIC_PARAM_HEAD(bl32, PARAM_EP, VERSION_1, 36 entry_point_info_t, SECURE), 37 .bl32.pc = BL32_BASE, 38 39 /* BL33 entry point */ 40 SET_STATIC_PARAM_HEAD(bl33, PARAM_EP, VERSION_1, 41 entry_point_info_t, NON_SECURE), 42 .bl33.pc = PRELOADED_BL33_BASE, 43 .bl33.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), 44 }; 45 46 static console_t console; 47 48 unsigned int plat_get_syscnt_freq2(void) 49 { 50 return PLAT_SYSCNT_FREQ; 51 } 52 53 #define CLK_ENABLE BIT_32(0) 54 #define CLK_OFF BIT_32(31) 55 56 #define GPIO_BLSP_UART2_TX 4 57 #define GPIO_BLSP_UART2_RX 5 58 #define GPIO_CFG_FUNC_BLSP_UART2 (U(0x2) << 2) 59 #define GPIO_CFG_DRV_STRENGTH_16MA (U(0x7) << 6) 60 61 #define GCC_BLSP1_AHB_CBCR (GCC_BASE + 0x01008) 62 #define GCC_BLSP1_UART2_APPS_CBCR (GCC_BASE + 0x0302c) 63 #define GCC_APCS_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x45004) 64 #define BLSP1_AHB_CLK_ENA BIT_32(10) 65 66 /* 67 * The previous boot stage seems to disable most of the UART setup before exit 68 * so it must be enabled here again before the UART console can be used. 69 */ 70 static void msm8916_enable_blsp_uart2(void) 71 { 72 /* Route GPIOs to BLSP UART2 */ 73 mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_TX), 74 GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA); 75 mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_RX), 76 GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA); 77 78 /* Enable AHB clock */ 79 mmio_setbits_32(GCC_APCS_CLOCK_BRANCH_ENA_VOTE, BLSP1_AHB_CLK_ENA); 80 while (mmio_read_32(GCC_BLSP1_AHB_CBCR) & CLK_OFF) 81 ; 82 83 /* Enable BLSP UART2 clock */ 84 mmio_setbits_32(GCC_BLSP1_UART2_APPS_CBCR, CLK_ENABLE); 85 while (mmio_read_32(GCC_BLSP1_UART2_APPS_CBCR) & CLK_OFF) 86 ; 87 } 88 89 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 90 u_register_t arg2, u_register_t arg3) 91 { 92 /* Initialize the debug console as early as possible */ 93 msm8916_enable_blsp_uart2(); 94 console_uartdm_register(&console, BLSP_UART2_BASE); 95 } 96 97 void bl31_plat_arch_setup(void) 98 { 99 mmap_add_region(BL31_BASE, BL31_BASE, BL31_END - BL31_BASE, 100 MT_RW_DATA | MT_SECURE); 101 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 102 BL_CODE_END - BL_CODE_BASE, 103 MT_CODE | MT_SECURE); 104 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 105 BL_RO_DATA_END - BL_RO_DATA_BASE, 106 MT_RO_DATA | MT_SECURE); 107 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 108 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 109 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER); 110 111 mmap_add(msm8916_mmap); 112 init_xlat_tables(); 113 enable_mmu_el3(0); 114 } 115 116 void bl31_platform_setup(void) 117 { 118 generic_delay_timer_init(); 119 } 120 121 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 122 { 123 switch (type) { 124 case SECURE: 125 return &image_ep_info.bl32; 126 case NON_SECURE: 127 return &image_ep_info.bl33; 128 default: 129 assert(sec_state_is_valid(type)); 130 return NULL; 131 } 132 } 133