1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef RDASPEN_DEFS_DTSI 8#define RDASPEN_DEFS_DTSI 9 10#include <platform_def.h> 11 12#define CPU(cluster_num, cluster_core_num, cpu_num, mpid) \ 13 CPU##cpu_num:cpu@mpid## { \ 14 device_type = "cpu"; \ 15 compatible = "arm,cortex-a720ae"; \ 16 reg = <0x0 0x##mpid>; \ 17 enable-method = "psci"; \ 18 i-cache-size = <0x10000>; \ 19 i-cache-line-size = <0x40>; \ 20 i-cache-sets = <0x100>; \ 21 d-cache-size = <0x10000>; \ 22 d-cache-line-size = <0x40>; \ 23 d-cache-sets = <0x100>; \ 24 next-level-cache = <&CL##cluster_num##_L2_##cluster_core_num>; \ 25 CL##cluster_num##_L2_##cluster_core_num: l2-cache##cpu_num { \ 26 compatible = "cache"; \ 27 cache-unified; \ 28 cache-level = <0x02>; \ 29 /* 512KB */ \ 30 cache-size = <0x80000>; \ 31 /* 64B */ \ 32 cache-line-size = <0x40>; \ 33 /* 8-way set */ \ 34 cache-sets = <0x400>; \ 35 next-level-cache = <&CL##cluster_num##_L3>; \ 36 }; \ 37 }; 38 39#define CORE(cluster_core_num, cpu_num) \ 40 core##cluster_core_num { \ 41 cpu = <&CPU##cpu_num>; \ 42 }; 43 44#define CLUSTER_L3_CACHE(cluster_num) \ 45 CL##cluster_num##_L3: l3-cache##cluster_num## { \ 46 compatible = "arm,dsu-l3-cache", "cache"; \ 47 cache-level = <0x03>; \ 48 /* 4MB */ \ 49 cache-size = <0x400000>; \ 50 /* 64B */ \ 51 cache-line-size = <0x40>; \ 52 /* 16-way set */ \ 53 cache-sets = <0x1000>; \ 54 }; 55 56#define CLUSTER_DSU_PMU(cluster_num, cpu_list, interrupt_map) \ 57 dsu-pmu-##cluster_num { \ 58 compatible = "arm,dsu-pmu"; \ 59 cpus = ##cpu_list; \ 60 interrupts = ##interrupt_map; \ 61 }; 62 63#define CLUSTER_0_DSU_PMU_INTERRUPT_MAP <GIC_SPI 216 IRQ_TYPE_EDGE_RISING> 64#define CLUSTER_1_DSU_PMU_INTERRUPT_MAP <GIC_SPI 217 IRQ_TYPE_EDGE_RISING> 65#define CLUSTER_2_DSU_PMU_INTERRUPT_MAP <GIC_SPI 218 IRQ_TYPE_EDGE_RISING> 66#define CLUSTER_3_DSU_PMU_INTERRUPT_MAP <GIC_SPI 219 IRQ_TYPE_EDGE_RISING> 67 68#if (PLATFORM_CLUSTER_0_CORE_COUNT == 1) 69#define CLUSTER_0_CPU_LIST \ 70 CORE(0, 0) 71#define CLUSTER_0_CPUS \ 72 CPU(0, 0, 0, 0) 73#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0> 74#elif (PLATFORM_CLUSTER_0_CORE_COUNT == 2) 75#define CLUSTER_0_CPU_LIST \ 76 CORE(0, 0) \ 77 CORE(1, 1) 78#define CLUSTER_0_CPUS \ 79 CPU(0, 0, 0, 0) \ 80 CPU(0, 1, 1, 100) 81#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1> 82#elif (PLATFORM_CLUSTER_0_CORE_COUNT == 3) 83#define CLUSTER_0_CPU_LIST \ 84 CORE(0, 0) \ 85 CORE(1, 1) \ 86 CORE(2, 2) 87#define CLUSTER_0_CPUS \ 88 CPU(0, 0, 0, 0) \ 89 CPU(0, 1, 1, 100) \ 90 CPU(0, 2, 2, 200) 91#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2> 92#elif (PLATFORM_CLUSTER_0_CORE_COUNT == 4) 93#define CLUSTER_0_CPU_LIST \ 94 CORE(0, 0) \ 95 CORE(1, 1) \ 96 CORE(2, 2) \ 97 CORE(3, 3) 98#define CLUSTER_0_CPUS \ 99 CPU(0, 0, 0, 0) \ 100 CPU(0, 1, 1, 100) \ 101 CPU(0, 2, 2, 200) \ 102 CPU(0, 3, 3, 300) 103#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3> 104#endif 105 106#if (PLATFORM_CLUSTER_1_CORE_COUNT == 1) 107#define CLUSTER_1_CPU_LIST \ 108 CORE(0, 4) 109#define CLUSTER_1_CPUS \ 110 CPU(1, 0, 4, 10000) 111#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4> 112#elif (PLATFORM_CLUSTER_1_CORE_COUNT == 2) 113#define CLUSTER_1_CPU_LIST \ 114 CORE(0, 4) \ 115 CORE(1, 5) 116#define CLUSTER_1_CPUS \ 117 CPU(1, 0, 4, 10000) \ 118 CPU(1, 1, 5, 10100) 119#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>, <&CPU5> 120#elif (PLATFORM_CLUSTER_1_CORE_COUNT == 3) 121#define CLUSTER_1_CPU_LIST \ 122 CORE(0, 4) \ 123 CORE(1, 5) \ 124 CORE(2, 6) 125#define CLUSTER_1_CPUS \ 126 CPU(1, 0, 4, 10000) \ 127 CPU(1, 1, 5, 10100) \ 128 CPU(1, 2, 6, 10200) 129#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>, <&CPU5>, <&CPU6> 130#elif (PLATFORM_CLUSTER_1_CORE_COUNT == 4) 131#define CLUSTER_1_CPU_LIST \ 132 CORE(0, 4) \ 133 CORE(1, 5) \ 134 CORE(2, 6) \ 135 CORE(3, 7) 136#define CLUSTER_1_CPUS \ 137 CPU(1, 0, 4, 10000) \ 138 CPU(1, 1, 5, 10100) \ 139 CPU(1, 2, 6, 10200) \ 140 CPU(1, 3, 7, 10300) 141#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7> 142#endif 143 144#if (PLATFORM_CLUSTER_2_CORE_COUNT == 1) 145#define CLUSTER_2_CPU_LIST \ 146 CORE(0, 8) 147#define CLUSTER_2_CPUS \ 148 CPU(2, 0, 8, 20000) 149#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8> 150#elif (PLATFORM_CLUSTER_2_CORE_COUNT == 2) 151#define CLUSTER_2_CPU_LIST \ 152 CORE(0, 8) \ 153 CORE(1, 9) 154#define CLUSTER_2_CPUS \ 155 CPU(2, 0, 8, 20000) \ 156 CPU(2, 1, 9, 20100) 157#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>, <&CPU9> 158#elif (PLATFORM_CLUSTER_2_CORE_COUNT == 3) 159#define CLUSTER_2_CPU_LIST \ 160 CORE(0, 8) \ 161 CORE(1, 9) \ 162 CORE(2, 10) 163#define CLUSTER_2_CPUS \ 164 CPU(2, 0, 8, 20000) \ 165 CPU(2, 1, 9, 20100) \ 166 CPU(2, 2, 10, 20200) 167#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>, <&CPU9>, <&CPU10> 168#elif (PLATFORM_CLUSTER_2_CORE_COUNT == 4) 169#define CLUSTER_2_CPU_LIST \ 170 CORE(0, 8) \ 171 CORE(1, 9) \ 172 CORE(2, 10) \ 173 CORE(3, 11) 174#define CLUSTER_2_CPUS \ 175 CPU(2, 0, 8, 20000) \ 176 CPU(2, 1, 9, 20100) \ 177 CPU(2, 2, 10, 20200) \ 178 CPU(2, 3, 11, 20300) 179#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11> 180#endif 181 182#if (PLATFORM_CLUSTER_3_CORE_COUNT == 1) 183#define CLUSTER_3_CPU_LIST \ 184 CORE(0, 12) 185#define CLUSTER_3_CPUS \ 186 CPU(3, 0, 12, 30000) 187#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12> 188#elif (PLATFORM_CLUSTER_3_CORE_COUNT == 2) 189#define CLUSTER_3_CPU_LIST \ 190 CORE(0, 12) \ 191 CORE(1, 13) 192#define CLUSTER_3_CPUS \ 193 CPU(3, 0, 12, 30000) \ 194 CPU(3, 1, 13, 30100) 195#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>, <&CPU13> 196#elif (PLATFORM_CLUSTER_3_CORE_COUNT == 3) 197#define CLUSTER_3_CPU_LIST \ 198 CORE(0, 12) \ 199 CORE(1, 13) \ 200 CORE(2, 14) 201#define CLUSTER_3_CPUS \ 202 CPU(3, 0, 12, 30000) \ 203 CPU(3, 1, 13, 30100) \ 204 CPU(3, 2, 14, 30200) 205#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>, <&CPU13>, <&CPU14> 206#elif (PLATFORM_CLUSTER_3_CORE_COUNT == 4) 207#define CLUSTER_3_CPU_LIST \ 208 CORE(0, 12) \ 209 CORE(1, 13) \ 210 CORE(2, 14) \ 211 CORE(3, 15) 212#define CLUSTER_3_CPUS \ 213 CPU(3, 0, 12, 30000) \ 214 CPU(3, 1, 13, 30100) \ 215 CPU(3, 2, 14, 30200) \ 216 CPU(3, 3, 15, 30300) 217#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>, <&CPU13>, <&CPU14>, <&CPU15> 218#endif 219 220#define CLUSTER_0_CPU_MAP \ 221 cluster0 { \ 222 CLUSTER_0_CPU_LIST \ 223 }; 224 225#define CLUSTER_0_DSU_PMU \ 226 CLUSTER_DSU_PMU(0, \ 227 CLUSTER_0_DSU_PMU_CPU_LIST, \ 228 CLUSTER_0_DSU_PMU_INTERRUPT_MAP) 229 230#if (PLATFORM_CLUSTER_1_CORE_COUNT >= 1) 231#define CLUSTER_1_CPU_MAP \ 232 cluster1 { \ 233 CLUSTER_1_CPU_LIST \ 234 }; 235 236#define CLUSTER_1_DSU_PMU \ 237 CLUSTER_DSU_PMU(1, \ 238 CLUSTER_1_DSU_PMU_CPU_LIST, \ 239 CLUSTER_1_DSU_PMU_INTERRUPT_MAP) 240#endif 241 242#if (PLATFORM_CLUSTER_2_CORE_COUNT >= 1) 243#define CLUSTER_2_CPU_MAP \ 244 cluster2 { \ 245 CLUSTER_2_CPU_LIST \ 246 }; 247 248#define CLUSTER_2_DSU_PMU \ 249 CLUSTER_DSU_PMU(2, \ 250 CLUSTER_2_DSU_PMU_CPU_LIST, \ 251 CLUSTER_2_DSU_PMU_INTERRUPT_MAP) 252#endif 253 254#if (PLATFORM_CLUSTER_3_CORE_COUNT >= 1) 255#define CLUSTER_3_CPU_MAP \ 256 cluster3 { \ 257 CLUSTER_3_CPU_LIST \ 258 }; 259 260#define CLUSTER_3_DSU_PMU \ 261 CLUSTER_DSU_PMU(3, \ 262 CLUSTER_3_DSU_PMU_CPU_LIST, \ 263 CLUSTER_3_DSU_PMU_INTERRUPT_MAP) 264#endif 265 266/* Max 4 clusters */ 267#if (PLAT_ARM_CLUSTER_COUNT == 1) 268#define CPU_MAP \ 269 cpu-map { \ 270 CLUSTER_0_CPU_MAP \ 271 }; 272 273#define CPUS \ 274 CLUSTER_0_CPUS 275 276#define DSU_PMU \ 277 CLUSTER_0_DSU_PMU 278 279#define L3_CACHE \ 280 CLUSTER_L3_CACHE(0) 281 282#elif (PLAT_ARM_CLUSTER_COUNT == 2) 283#define CPU_MAP \ 284 cpu-map { \ 285 CLUSTER_0_CPU_MAP \ 286 CLUSTER_1_CPU_MAP \ 287 }; 288 289#define CPUS \ 290 CLUSTER_0_CPUS \ 291 CLUSTER_1_CPUS 292 293#define DSU_PMU \ 294 CLUSTER_0_DSU_PMU \ 295 CLUSTER_1_DSU_PMU 296 297#define L3_CACHE \ 298 CLUSTER_L3_CACHE(0) \ 299 CLUSTER_L3_CACHE(1) 300 301#elif (PLAT_ARM_CLUSTER_COUNT == 3) 302#define CPU_MAP \ 303 cpu-map { \ 304 CLUSTER_0_CPU_MAP \ 305 CLUSTER_1_CPU_MAP \ 306 CLUSTER_2_CPU_MAP \ 307 }; 308 309#define CPUS \ 310 CLUSTER_0_CPUS \ 311 CLUSTER_1_CPUS \ 312 CLUSTER_2_CPUS 313 314#define DSU_PMU \ 315 CLUSTER_0_DSU_PMU \ 316 CLUSTER_1_DSU_PMU \ 317 CLUSTER_2_DSU_PMU 318 319#define L3_CACHE \ 320 CLUSTER_L3_CACHE(0) \ 321 CLUSTER_L3_CACHE(1) \ 322 CLUSTER_L3_CACHE(2) 323 324#elif (PLAT_ARM_CLUSTER_COUNT == 4) 325#define CPU_MAP \ 326 cpu-map { \ 327 CLUSTER_0_CPU_MAP \ 328 CLUSTER_1_CPU_MAP \ 329 CLUSTER_2_CPU_MAP \ 330 CLUSTER_3_CPU_MAP \ 331 }; 332 333#define CPUS \ 334 CLUSTER_0_CPUS \ 335 CLUSTER_1_CPUS \ 336 CLUSTER_2_CPUS \ 337 CLUSTER_3_CPUS 338 339#define DSU_PMU \ 340 CLUSTER_0_DSU_PMU \ 341 CLUSTER_1_DSU_PMU \ 342 CLUSTER_2_DSU_PMU \ 343 CLUSTER_3_DSU_PMU 344 345#define L3_CACHE \ 346 CLUSTER_L3_CACHE(0) \ 347 CLUSTER_L3_CACHE(1) \ 348 CLUSTER_L3_CACHE(2) \ 349 CLUSTER_L3_CACHE(3) 350 351#endif /* PLAT_ARM_CLUSTER_COUNT */ 352 353#endif /* RDASPEN_DEFS_DTSI */ 354