feat(tc): add device tree binding for TC4

Since TC3 and TC4 share most components in the hardware design, they can
reuse the device tree binding. For this reason, this patch extracts the
common modu

feat(tc): add device tree binding for TC4

Since TC3 and TC4 share most components in the hardware design, they can
reuse the device tree binding. For this reason, this patch extracts the
common modules from tc3.dts and put into the file tc3-4-based.dtsi.

As a result, a new created tc4.dts file includes tc3-4-based.dtsi for
support DT binding for the TC4 platform.

Change-Id: Ib7497162cb131d94a722aeaa14a1a37fb0095829
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config fil

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1
feat(stm32mp2-fdts): add fw-config file
feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1
feat(stm32mp2): enable DDR sub-system clock
feat(stm32mp2): add fixed regulators support
feat(stm32mp2): print board info
feat(stm32mp2): display CPU info
feat(stm32mp2): get chip ID
feat(stm32mp2): add BL2 boot first steps
feat(stm32mp2): add defines for the PWR peripheral
feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1
feat(stm32mp2-fdts): add sdmmc pins definition
feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file
feat(stm32mp2-fdts): add io_policies
feat(stm32mp2-fdts): remove pins-are-numbered

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feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1

Add the Firmware Config DT file for STM32MP257F-EV1 board.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I895ef919b1f388b

feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1

Add the Firmware Config DT file for STM32MP257F-EV1 board.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I895ef919b1f388be1e8d25490f25b1e7195984f8

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feat(stm32mp2-fdts): add fw-config file

This is a generic file to be use on all STM32MP2 boards, as what is
done for STM32MP15.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4ae0cf0

feat(stm32mp2-fdts): add fw-config file

This is a generic file to be use on all STM32MP2 boards, as what is
done for STM32MP15.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4ae0cf0b7d21b1a2072b7ff5e6b98837d603c860

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feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1

Add dedicated RCC file to define clock tree and include it in
STM32MP257F-EV1 board DT file.

Signed-off-by: Yann Gautier <yann.gautier@st.com

feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1

Add dedicated RCC file to define clock tree and include it in
STM32MP257F-EV1 board DT file.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I259075f34d02534063c95fb571aec6ada480ce5f

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feat(stm32mp2): display CPU info

Print information about CPU type, package and revision.
SoC revision ID of MP2 family are defined with the OTP 102.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.

feat(stm32mp2): display CPU info

Print information about CPU type, package and revision.
SoC revision ID of MP2 family are defined with the OTP 102.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I14a95c8a7cb9b06ce32c2e592ae69a1741067e8d

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feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1

Add sdmmc1 node to support SD-cards on STM32MP257F-EV1 board, and
sdmmc2 node for eMMC.

Signed-off-by: Yann Gautier <yann.gautie

feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1

Add sdmmc1 node to support SD-cards on STM32MP257F-EV1 board, and
sdmmc2 node for eMMC.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I375e35aa6a96719a69df976500915be51c395b00

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feat(stm32mp2-fdts): add sdmmc pins definition

Add the pins nodes for SD-card or eMMC. Those pins are used on
STM32MP257F-EV1 board.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I96

feat(stm32mp2-fdts): add sdmmc pins definition

Add the pins nodes for SD-card or eMMC. Those pins are used on
STM32MP257F-EV1 board.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I96fe8210502b073bc222a70453bee1863a257c7b

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feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file

Add the sdmmc1 & sdmmc2 nodes in stm32mp251.dtsi file, to support
eMMC or SD-cards.
To avoid increasing DT size if SD-card or eMMC boot is not sel

feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file

Add the sdmmc1 & sdmmc2 nodes in stm32mp251.dtsi file, to support
eMMC or SD-cards.
To avoid increasing DT size if SD-card or eMMC boot is not selected,
the nodes are removed from DT thanks to stm32mp25-bl2.dtsi overlay.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2ed841442b7dddf0c441ae3b3d2462ef535f9951

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feat(stm32mp2-fdts): add io_policies

This will be required for FCONF management on STM32MP2.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If651a9aa36cdf415f570b2392daa08c198d629d2

feat(stm32mp2-fdts): remove pins-are-numbered

Remove the deprecated property "pins-are-numbered" from pinctrl and
pinctrl_z nodes of stm32mp25 soc to conform with the upstream series
of the link bel

feat(stm32mp2-fdts): remove pins-are-numbered

Remove the deprecated property "pins-are-numbered" from pinctrl and
pinctrl_z nodes of stm32mp25 soc to conform with the upstream series
of the link below.

Link: https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=69786

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I1ed98c94c5003bc9903229957cb072da4211238f

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feat(arm): generate tbbr c file CoT dt2c

Integrate the cot-dt2c tool into build process
for TBBR configuration

Change-Id: I42ccbc96c5c8fd21266200e427306a80236a78aa
Signed-off-by: Xialin Liu <Xialin

feat(arm): generate tbbr c file CoT dt2c

Integrate the cot-dt2c tool into build process
for TBBR configuration

Change-Id: I42ccbc96c5c8fd21266200e427306a80236a78aa
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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refactor(st): align the NV counter naming

align the nv counter naming for stm32mp1-cot-descriptor.dtsi file

Change-Id: I8c41c5e323e8bf867e08b4590dfb42e86204ab65
Signed-off-by: Xialin Liu <Xialin.Li

refactor(st): align the NV counter naming

align the nv counter naming for stm32mp1-cot-descriptor.dtsi file

Change-Id: I8c41c5e323e8bf867e08b4590dfb42e86204ab65
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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refactor(fvp): align the NV counter naming

Align the naming of nv_counter to nv_ctr in the DTBs
so that they match with the static C files. Update the
binding documentation accordingly. This renamin

refactor(fvp): align the NV counter naming

Align the naming of nv_counter to nv_ctr in the DTBs
so that they match with the static C files. Update the
binding documentation accordingly. This renaming is beneficial
for the upcoming conversion tool that will convert CoT DT files
to C files.

Change-Id: If65d51ad9fc6445b1ae9937f1691becf8742cf01
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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fix(tc): correct CPU PMU binding

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.

Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signe

fix(tc): correct CPU PMU binding

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.

Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add device tree binding for SPE

Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface

feat(tc): add device tree binding for SPE

Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface.

Change-Id: Ic7a9d9ce927edbce02c7c09470a009dc56247240
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add PPI partitions in DT binding

Define ppi-partitions for little, middle, and big cpu groups. PPI
affinity is expressed as a single "ppi-partitions" node, containing a
set of sub-nodes fo

feat(tc): add PPI partitions in DT binding

Define ppi-partitions for little, middle, and big cpu groups. PPI
affinity is expressed as a single "ppi-partitions" node, containing a
set of sub-nodes for each microarchitecture type, each with the
property 'affinity' which should be a list of phandles to CPU nodes.

PPI paritions are useful to affine specific PPI with set of CPUs
so that the drivers of micro-architecture specific nodes which uses
PPI can be divided based on CPU list e.g. SPE-PMU, CPU-PMU etc.

Change-Id: If7d47f71387ac982d2d992a0ce2de1652d564bd6
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): change GIC DT property 'interrupt-cells' to 4

Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is
a phandle to a node describing a set of CPUs this interrupt is affine

feat(tc): change GIC DT property 'interrupt-cells' to 4

Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is
a phandle to a node describing a set of CPUs this interrupt is affine
to.

If an interrupt is a PPI, and the node pointed in the 4th cell must be a
subnode of the "ppi-partitions" in the GIC node. For interrupt types
other than PPI, this cell must be zero. This is a preparison for
sequential changes for interrupt partitions, as the first step, it sets
all zeros for the interrupt affinity.

Change-Id: I66490a86a27aad5db6b1a42c2d8e0d042eee46a9
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add NI-Tower PMU node for TC3

Enable NI-Tower PMU on TC3.

Change-Id: I8a4d4e31e84ab33f95bc8b7661e873cf97561b79
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Ya

feat(tc): add NI-Tower PMU node for TC3

Enable NI-Tower PMU on TC3.

Change-Id: I8a4d4e31e84ab33f95bc8b7661e873cf97561b79
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add DSU PMU node for tc3

Add DT binding for Arm DSU PMU node.

Change-Id: Iadfb5d3bb3f69c7a771516180d1c165e60eef51d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Le

feat(tc): add DSU PMU node for tc3

Add DT binding for Arm DSU PMU node.

Change-Id: Iadfb5d3bb3f69c7a771516180d1c165e60eef51d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "ip_smmu" into integration

* changes:
feat(tc): bind SMMU-600 with the DPU on TC3 FPGA
feat(tc): bind SMMU-700 with DPU on TC3
refactor(tc): append binding for SMMU-700

Merge changes from topic "st_clk_update" into integration

* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct

Merge changes from topic "st_clk_update" into integration

* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct
feat(stm32mp1-fdts): remove RTC clock configuration
refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock
refactor(st-clock): driver size optimization
refactor(st-clock): remove BL32 support on STM32MP13
feat(st-clock): don't gate/ungate an oscillator if it is not wired
feat(dt-bindings): add missing SPIx bus clocks
feat(stm32mp1-fdts): remove PLL1 settings
feat(st-clock): update with new bindings
feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1
feat(dt-bindings): new RCC DT bindings
feat(stm32mp1): always boot at 650MHz
refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13
fix(st-clock): display proper PLL number for STM32MP13
fix(st-clock): do not reconfigure LSE
feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation
refactor(st-clock): remove unused clk function in API
refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config
feat(st-clock): add function to restore generic timer rate

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Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure acces

Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure access to pmu counters on TC3

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Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB suppo

Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB support
feat(dt-bindings): introduce Dualroot CoT DTB

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feat(stm32mp1-fdts): remove RTC clock configuration

RTC clock configuration is done now in OPTEE.
Note: The RTC clock source can only be configured once.
TF-A, configuring the RTC clock source will

feat(stm32mp1-fdts): remove RTC clock configuration

RTC clock configuration is done now in OPTEE.
Note: The RTC clock source can only be configured once.
TF-A, configuring the RTC clock source will have no effect in OPTEE.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I111ba96b27d0de0c45086ba8ef947dd2e6785672

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