fix(st-clock): add ck_bus_risaf4 clock for STM32MP2

Add management of the ck_bus_risaf4 clock.
The RISAF4 clock is missing, which causes a panic if it is enabled.
The DDR clock is set to critical as

fix(st-clock): add ck_bus_risaf4 clock for STM32MP2

Add management of the ck_bus_risaf4 clock.
The RISAF4 clock is missing, which causes a panic if it is enabled.
The DDR clock is set to critical as it is mandatory to keep the DDR
clock active.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6ac2aff07484bfc22210ee9d3e46a97d1735f34b

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Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra viol

Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra violation 12.1
fix(gicv3): match function definition and declaration
fix(gicv3): typecast operands to match data type

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Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declar

Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declare unused parameters as void

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Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee s

Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee support
feat(imx95): support trusty os
feat(imx95): implement a semaphore for GIC quiescing
feat(imx95): add initial support for i.MX95
feat(imx9): add necessary ele api call support
feat(imx9): add imx9 common code base
refactor(imx): drop the __dead2 attribute
fix(imx): add static attribute for platform specific gic struct
feat(gic): change gic_cpuif_enable/disable to weak
feat(scmi): add i.MX9 SCMI vendor CPU protocol
feat(scmi): add base protocol agent API
feat(scmi): update version to 3.0
build(changelog): update for imx94/95 support

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Merge "fix(dcc): typecast operands to match data type" into integration

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Icd480587b74c0e0a818498b680666ed43e94fef8
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body w

fix(gicv3): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body within the curly
braces.

Change-Id: I657780b0e322a0aff990390a8dfc1af56dfd5c1d
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpect

fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpected behavior
due to operator precedence and which improves the readibility and
maintainability.

Change-Id: I8d09f136faae2869fc1ef2d6eb46de035b7e6a1e
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): match function definition and declaration

This corrects the MISRA violation C2012-8.3:
change the type/qualifer of function parameter as per the functional
decleration. unction declerati

fix(gicv3): match function definition and declaration

This corrects the MISRA violation C2012-8.3:
change the type/qualifer of function parameter as per the functional
decleration. unction decleration and definition should be match to
avoid conflicts.

Change-Id: Ic6cff6719a38dffe78e4756d3bb7cf32512c5344
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a di

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Id802961c24a57eea7dd928e2278d015a8747a4c5
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(ti): specify allowable rcv_addr in mailbox

The ti_sci_transport_recv function had an overly restrictive check
where we enforced the rcv_addr to be always at the start of the
RX_START region in s

fix(ti): specify allowable rcv_addr in mailbox

The ti_sci_transport_recv function had an overly restrictive check
where we enforced the rcv_addr to be always at the start of the
RX_START region in shared memory. This started failing unnecessarily
when messages started being received at a location other than the
beginning.
However, the sender might send the messages at any location within
the share memory region if it does some sort of buffer management.
In such a case, TFA needs to just make sure the message being read
is well within the allocated shared memory region. Not necessarily
at the start.

Fixes: 9347ff4561e445d4 ("feat(ti): add support for TI mailbox driver")
Change-Id: I32cf0f5e4b9fedf49e40ace0bef06b7fc4c016f6
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(gic): change gic_cpuif_enable/disable to weak

For some platform like NXP i.MX94/95, the gic cpu interface
enable & disable need some special handling except the generic
gic_cpuif_enable/disable

feat(gic): change gic_cpuif_enable/disable to weak

For some platform like NXP i.MX94/95, the gic cpu interface
enable & disable need some special handling except the generic
gic_cpuif_enable/disable API. To allow these platform to reuse
the generic gic driver support, need to mark these two APIs as weak
to allow platforms to provide platform specific implementation.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I742fcb60bef20b051363f1fa86c6254e2f463129

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feat(scmi): add i.MX9 SCMI vendor CPU protocol

Add i.MX9 SCMI vendor specific CPU protocol

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.c

feat(scmi): add i.MX9 SCMI vendor CPU protocol

Add i.MX9 SCMI vendor specific CPU protocol

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Icc81bf9f4a32c08e4a3c358b1cf561ca4345a431

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feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec61

feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec6160bd794f48e3c41718ecce0ec88a

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fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correc

fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correctly.

Added polling for the ICS bit after enabling ICE when
setting the SDCLK rate. Introduced delay to ensure
proper clock stabilization.

Corrected SD_HOST_CLK to data driven from the clock manager
as sdmclk.

eMMC operates in legacy mode, which has a maximum
supported clock rate of 26 MHz. Updated the clock
setting to 25 MHz to meet this requirement.

Change-Id: I4ac2b9b69b5dec2c8166d06c736d9c2c549607de
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref

Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver

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Merge "fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor" into integration

fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor

When compile using arm gcc compiler with versions 12 above,
the cadence SD/eMMC driver will failed with ADMA error. When
sendi

fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor

When compile using arm gcc compiler with versions 12 above,
the cadence SD/eMMC driver will failed with ADMA error. When
sending MMC command. The memory is not aligned correctly
when using different version of gcc.

The descriptor memory must be aligned to 4 byte boundary
with 2 least significant bits set to 0 in 32-bit ADMA
addressing mode and aligned to 8 byte boundary with
3 least significant bits set to 0 in 64-bit ADMA
addresing mode.

Since 8 byte boundary is common to both 4 byte and
8 byte boundary hence aligning the descriptor
memory with 8 byte boundary.

Change-Id: Ie56d2aef22b4e4ef0fa516b9cda53b33d6316cb7
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(console): create unique variable name

This corrects the MISRA violation C2012-5.7:
A tag name shall be a unique identifier.
Renamed the variable to ensure uniqueness.

Change-Id: I96e61caa8c6c7f

fix(console): create unique variable name

This corrects the MISRA violation C2012-5.7:
A tag name shall be a unique identifier.
Renamed the variable to ensure uniqueness.

Change-Id: I96e61caa8c6c7ff64759363afd24fc224d449f86
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes

refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes all GICR frames are
contiguous. This is the original method.

b) via gicv3_rdistif_probe() - called from platform code and requires
gicr_base == 0. It relaxes the requirement for frames to be
contiguous, like in a multichip configuration, and defers the
discovery to core bringup. This was introduced later.

Configurations possible with option a) are also possible with option b)
with only slightly different behaviour. USE_GIC_DRIVER=3 inherited
option b) from plat_gicv3_base.c and as such option a) is unusable.
However, it is unclear from code how this should be used. Clarify this
by requiring platforms initialise with gic_set_gicr_frames() and
adding relevant comments.

Also rename plat_arm_override_gicr_frames() to gic_set_gicr_frames() as
this is not plat arm specific and a part of the generic GIC driver.

Change-Id: I61d77211f8e65dc54cf9904069b500d26a06b5a5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration

* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encr

Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration

* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encryption
feat(stm32mp2): add some platform helpers
feat(st-drivers): add RISAF driver
feat(fdts): add RISAF nodes for STM32MP25
feat(stm32mp2-fdts): add memory firewall node
feat(stm32mp2-fdts): add firewall nodes in fw-config
feat(stm32mp2): add RIF dt-binding defines
feat(stm32mp1-fdts): add MCE support for STM32MP13 DK board
feat(stm32mp1): prepare DDR secure area encryption for STM32MP13
feat(stm32mp1): enable MCE driver for STM32MP13
feat(st-drivers): add Memory Cipher Engine driver
feat(dt-bindings): add MCE DT bindings for STM32MP13
fix(st-crypto): improve RNG health test configuration
feat(st): add RNG minor version
feat(st-crypto): add multi instance and error management in RNG driver
feat(stm32mp2): add HASH and RNG compilation
feat(stm32mp25-fdts): add RNG node

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Merge "feat(gic): make IRQ groups optional" into integration

fix(arm-drivers): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement

fix(arm-drivers): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body within the curly
braces.

Change-Id: I0e2ef3c2210816d1da09671157f23d42e493e356
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(arm-drivers): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Chan

fix(arm-drivers): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I10c42f7b1ec5264a19feb7d666c2661bfdb45975
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(t

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.

The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2

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