1 /* 2 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #ifndef __ASSEMBLER__ 11 #include <stdlib.h> 12 #endif /*__ASSEMBLER__*/ 13 14 #include <arch.h> 15 16 #include "rcar_def.h" 17 18 /******************************************************************************* 19 * Platform binary types for linking 20 ******************************************************************************/ 21 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 22 #define PLATFORM_LINKER_ARCH aarch64 23 24 /******************************************************************************* 25 * Generic platform constants 26 ******************************************************************************/ 27 28 /* Size of cacheable stacks */ 29 #define PLATFORM_STACK_SIZE 0x800U 30 31 /* 32 * R-Car S4 Cortex-A55 33 * L1:I/32KB per core, D/32KB per core, L2:0B L3:256KB per cluster 34 */ 35 #if RCAR_LSI == RCAR_V4M 36 #define PLATFORM_CLUSTER_COUNT 1 37 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 38 #elif RCAR_LSI == RCAR_V4H 39 #define PLATFORM_CLUSTER_COUNT 2 40 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 41 #else /* S4 and V3U */ 42 #define PLATFORM_CLUSTER_COUNT 4 43 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 44 #endif 45 46 #if PLATFORM_CLUSTER_COUNT > 0 47 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 48 #else 49 #error "At least one CPU cluster has to be defined" 50 #endif 51 52 #if PLATFORM_CLUSTER_COUNT > 1 53 #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 54 #else 55 #define PLATFORM_CLUSTER1_CORE_COUNT 0 56 #endif 57 #if PLATFORM_CLUSTER_COUNT > 2 58 #define PLATFORM_CLUSTER2_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 59 #else 60 #define PLATFORM_CLUSTER2_CORE_COUNT 0 61 #endif 62 #if PLATFORM_CLUSTER_COUNT > 3 63 #define PLATFORM_CLUSTER3_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 64 #else 65 #define PLATFORM_CLUSTER3_CORE_COUNT 0 66 #endif 67 #if PLATFORM_CLUSTER_COUNT > 4 68 #error "Maximum supported cluster number is 4" 69 #endif 70 71 #define PLATFORM_CORE_COUNT \ 72 (PLATFORM_CLUSTER3_CORE_COUNT + PLATFORM_CLUSTER2_CORE_COUNT + \ 73 PLATFORM_CLUSTER1_CORE_COUNT + PLATFORM_CLUSTER0_CORE_COUNT) 74 75 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 76 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 77 PLATFORM_CLUSTER_COUNT + 1) 78 79 #define PLAT_MAX_RET_STATE 1 80 #define PLAT_MAX_OFF_STATE 2 81 82 /* 83 ****************************************************************************** 84 * BL31 specific defines. 85 ****************************************************************************** 86 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 87 * current BL3-1 debug size plus a little space for growth. 88 */ 89 #define BL31_BASE RCAR_TRUSTED_SRAM_BASE 90 #define BL31_LIMIT \ 91 (RCAR_TRUSTED_SRAM_BASE + RCAR_TRUSTED_SRAM_SIZE) 92 93 94 /******************************************************************************* 95 * Platform specific page table and MMU setup constants 96 ******************************************************************************/ 97 #define MAX_XLAT_TABLES 8 98 99 #define PLAT_PHY_ADDR_SPACE_SIZE BIT(32) 100 #define PLAT_VIRT_ADDR_SPACE_SIZE BIT(32) 101 102 #define MAX_MMAP_REGIONS (RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS) 103 104 /******************************************************************************* 105 * Declarations and constants to access the mailboxes safely. Each mailbox is 106 * aligned on the biggest cache line size in the platform. This is known only 107 * to the platform as it might have a combination of integrated and external 108 * caches. Such alignment ensures that two mailboxes do not sit on the same cache 109 * line at any cache level. They could belong to different cpus/clusters & 110 * get written while being protected by different locks causing corruption of 111 * a valid mailbox address. 112 ******************************************************************************/ 113 #define CACHE_WRITEBACK_SHIFT 6 114 #define CACHE_WRITEBACK_GRANULE BIT(CACHE_WRITEBACK_SHIFT) 115 116 /* 117 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 118 * terminology. On a GICv2 system or mode, the lists will be merged and treated 119 * as Group 0 interrupts. 120 * 121 * PLAT_ARM_G0_IRQ_PROPS(grp) is not defined, because there are no Group 0 IRQs. 122 */ 123 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 124 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_NS_PRIORITY, (grp), \ 125 GIC_INTR_CFG_LEVEL), \ 126 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_NS_PRIORITY, (grp), \ 127 GIC_INTR_CFG_EDGE), \ 128 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_NS_PRIORITY, (grp), \ 129 GIC_INTR_CFG_EDGE), \ 130 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_NS_PRIORITY, (grp), \ 131 GIC_INTR_CFG_EDGE), \ 132 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_NS_PRIORITY, (grp), \ 133 GIC_INTR_CFG_EDGE), \ 134 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_NS_PRIORITY, (grp), \ 135 GIC_INTR_CFG_EDGE), \ 136 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_NS_PRIORITY, (grp), \ 137 GIC_INTR_CFG_EDGE), \ 138 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_NS_PRIORITY, (grp), \ 139 GIC_INTR_CFG_EDGE), \ 140 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_NS_PRIORITY, (grp), \ 141 GIC_INTR_CFG_EDGE) 142 143 #endif /* PLATFORM_DEF_H */ 144