feat(rcar): deduplicate SCIF console_rcar_register

The console_rcar_register assembler macro is functionally identical
between Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by

feat(rcar): deduplicate SCIF console_rcar_register

The console_rcar_register assembler macro is functionally identical
between Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ib498832dbed9063efdb9979e89e53d119303d9df

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feat(rcar): deduplicate PWRC timer

The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mai

feat(rcar): deduplicate PWRC timer

The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Id50a730ea58faedaa24380fd3171be171ecd7269

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feat(rcar): deduplicate PWRC SRAM trampoline

The PWRC SRAM trampoline code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <mar

feat(rcar): deduplicate PWRC SRAM trampoline

The PWRC SRAM trampoline code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I24209ac0277fa12898bbeea69d93a8f057e76ed4

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feat(build): pass cflags to the linker when LTO is enabled

Usually, both compiling and linking happen by calling the top level
gcc/clang binary. Also, both compilers quite specifically tell us to
pa

feat(build): pass cflags to the linker when LTO is enabled

Usually, both compiling and linking happen by calling the top level
gcc/clang binary. Also, both compilers quite specifically tell us to
pass the same flags to the compilation and linking stages when we enable
LTO. This is crucial for things like the undefined behaviour sanitiser.
Anecdotally, in working on this, there have been a fair few errors that
the compiler has only been able to catch due to warning flags being
passed to the linker and building with LTO.

This patch puts the contents of TF_CFLAGS into TF_LDFLAGS when LTO is
enabled. This is easier said than done, however, as we support building
with clang and linking with gcc (or vice versa), so CFLAGS that are
discovered for one will not work for the other. This patch works around
this by splitting all flags into a per-compiler variable. Then CFLAGS
and LDFLAGS get the contents of the correct one.

Some notable side effects: CPPFLAGS and TF_CFLAGS_$(ARCH) become empty
and are removed, although expanding them is kept as platforms set them.
Some flags become duplicate and are removed form TF_LDFLAGS (eg -O1).

The errata (--fix) flags are kept as-is but moved to cpu-ops.mk for
consistency. This is because they currently don't work with LTO and will
be addressed in a later patch.

Finally, ERROR_DEPRECATED's flags are also identical on all compilers so
don't maintain a difference.

Change-Id: I3630729ee5f474c09d4722cd0ede6845e1725d95
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(scmi): change error code output for wrong ids

This changes the error code output in the power and clock domain for
a non-existing device and clock id from SCMI_INVALID_PARAMETER to
SCMI_NOT_FOUN

fix(scmi): change error code output for wrong ids

This changes the error code output in the power and clock domain for
a non-existing device and clock id from SCMI_INVALID_PARAMETER to
SCMI_NOT_FOUND in accordance to the SCMI specification

Change-Id: Ica2a549635a8a52393bed38a5e35bd63a873a3d9
Signed-off-by: Scaria Kochidanadu <s-kochidanadu@ti.com>

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fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359

fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359378574b913b11d466c89389a2606
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
co

feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.

Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>

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feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02

feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02557ba7569a536cece37e4c1fe98
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(guid-partition): platform hook to log corrupted GPT

Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information

feat(guid-partition): platform hook to log corrupted GPT

Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information

Change-Id: Ie1af7eb6d97ec76f3f6d1cffad292782bdedda21
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "feat(mbedtls): update mbedtls to version 3.6.4" into integration

feat(mbedtls): update mbedtls to version 3.6.4

In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locatio

feat(mbedtls): update mbedtls to version 3.6.4

In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locations of some helper functions. This is currently an open
issue for mbedtls: https://github.com/Mbed-TLS/mbedtls/issues/10376

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I57c9c14aabe75a51c74dcf2a33faf59f95ce2386

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refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(gicv3): avoid incrementing global gicr_frames pointer

commit 75170704c9119a4947 (refactor(gicv3): clarify redistributor base
address usage with USE_GIC_DRIVER=3) introduced changes to walk the
r

fix(gicv3): avoid incrementing global gicr_frames pointer

commit 75170704c9119a4947 (refactor(gicv3): clarify redistributor base
address usage with USE_GIC_DRIVER=3) introduced changes to walk the
redistributor frames by incrementing the global `gicr_frames` pointer.
This leaves the pointer advanced after the first miss, so subsequent
CPUs do not start from the beginning of the array. Such behaviour is
incorrect in the presence of CPU hotplug or out-of-order CPU_ON
operations, where each CPU must be able to probe the full set of
redistributor frames independently.

Fix this by using a local iterator instead of modifying the global
`gicr_frames` pointer, preserving the array state for all CPUs.

While here, fix a typo in a comment and replace the `do…while`
loop with a safer `while` loop to avoid probing the zero terminator in
case a platform erroneously passes an empty array.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I6d6f73fb172c48f8e50b29ec2232648be3a6a6a0

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Merge changes from topic "ti-am62lxx-boot-notif" into integration

* changes:
feat(ti): am62lx init: boot notif and version msg
feat(ti): add support for boot notification msg
feat(ti): add mmu

Merge changes from topic "ti-am62lxx-boot-notif" into integration

* changes:
feat(ti): am62lx init: boot notif and version msg
feat(ti): add support for boot notification msg
feat(ti): add mmu regions for am62l soc
feat(ti): build generic timer

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build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, an

build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, and platform integration logic to link with lib as a
static library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibEventLog is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I723f493033c178759a45ea04118e7cc295dc2438
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(ti): add support for boot notification msg

Add support for boot notification message[1] from the system-firmware
which indicates it's ready to start TI SCI communication with other
entities in

feat(ti): add support for boot notification msg

Add support for boot notification message[1] from the system-firmware
which indicates it's ready to start TI SCI communication with other
entities in the system.

[1] https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html#tisci-msg-boot-notification

Change-Id: I5fab25dd460824f03df623b23e656bf3252db59c
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+re

fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Icdb5188cba97be5dfccb240f773288a54662e977

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Merge changes from topic "console_stm32" into integration

* changes:
fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush
fix(st-uart): aarch32: remove unnecessary timeout

Merge changes from topic "console_stm32" into integration

* changes:
fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush
fix(st-uart): aarch32: remove unnecessary timeout waiting in putc
fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush
fix(st-uart): aarch64: unwait for UART ISR register TC bit in putc function

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fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.

Change-Id: I

fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.

Change-Id: I94b6238e3f8a94bc4a1fabaf8d45d3b66d42e834
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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fix(st-uart): aarch32: remove unnecessary timeout waiting in putc

The UART is configured with FIFO enabled, therefore putting a
character in the TDR register and wait for the transmission flag
compl

fix(st-uart): aarch32: remove unnecessary timeout waiting in putc

The UART is configured with FIFO enabled, therefore putting a
character in the TDR register and wait for the transmission flag
complete is enough.

Change-Id: I5e254df89f2652e300ea5bedf9269d420895bdbf
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.
Fix the retur

fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.
Fix the return value that should be void in flush related functions
description.

Change-Id: Idbeecc3ca36b6ce506c9489b4f611bbe345121a3
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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fix(st-uart): aarch64: unwait for UART ISR register TC bit in putc function

The loop over the UART_ISR_TC flag was needed before the UART FIFO was
enabled. This allowed to make sure each character w

fix(st-uart): aarch64: unwait for UART ISR register TC bit in putc function

The loop over the UART_ISR_TC flag was needed before the UART FIFO was
enabled. This allowed to make sure each character written in TDR was
outputed.
This behavior is no more needed. Once a character is in the FIFO the
UART will empty it when it is clocked.

Change-Id: I914c7f75a451bedbcc9287d8ed9178db47b4eab4
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU p

feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU power driver, Gen4 (H)SCIF driver, and function to get canary for
stack protector. Unlike Gen3, the Gen4 uses only TFA BL31 during boot.

Change-Id: Ic0eb8638a85757f997f29fc524c118c3e5d5135a
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Jing Dan <jing.dan.nx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Masashi Ozaki <masashi.ozaki.te@renesas.com>
Signed-off-by: Taichiro Yokoyama <taichiro.yokoyama.ns@hitachi.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Tsukasa Kawaguchi <tsukasa.kawaguchi.aw@hitachi.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Vincent Bryce <vincent.bryce@cogentembedded.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
---
NOTE: This patch is squashed and cleaned up from large stack of patches
from multiple authors. SoB line from each author is included here,
the author of this commit is set to myself although that is most
certainly not accurate.

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Merge "fix(ti): specify allowable rcv_addr in mailbox" into integration

Merge "fix(st-clock): add ck_bus_risaf4 clock for STM32MP2" into integration