feat(nxp-clk): enable the XBAR clock

Enable the XBAR clock, which is the primary system clock.

Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.proc

feat(nxp-clk): enable the XBAR clock

Enable the XBAR clock, which is the primary system clock.

Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add dependencies for the XBAR clock

Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.

Change-Id: Ib9cf82c0e40b76863637

feat(nxp-clk): add dependencies for the XBAR clock

Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.

Change-Id: Ib9cf82c0e40b76863637ed7602c3a09411d17615
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procop

feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add DFS module enablement

Implement enable and set_module_rate callbacks for DFS modules.

Change-Id: Ic9d6034ac04adbabd8fc782aea94ce252439f136
Signed-off-by: Ghennadi Procopciuc <ghe

feat(nxp-clk): add DFS module enablement

Implement enable and set_module_rate callbacks for DFS modules.

Change-Id: Ic9d6034ac04adbabd8fc782aea94ce252439f136
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(nxp-clk): organize early clocks in groups

This reduces the length of the s32cc_init_early_clks function and offers
space for more early clocks to be added.

Change-Id: I0d11b97779433a6b15cd

refactor(nxp-clk): organize early clocks in groups

This reduces the length of the s32cc_init_early_clks function and offers
space for more early clocks to be added.

Change-Id: I0d11b97779433a6b15cd76c36aefbb7b92381067
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "enable_a53_clk" into integration

* changes:
feat(nxp-clk): enable the A53 clock
feat(nxp-clk): add ARM PLL ODIV enablement
feat(nxp-clk): add ARM PLL enablement
fea

Merge changes from topic "enable_a53_clk" into integration

* changes:
feat(nxp-clk): enable the A53 clock
feat(nxp-clk): add ARM PLL ODIV enablement
feat(nxp-clk): add ARM PLL enablement
feat(nxp-clk): set rate for clock muxes

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Merge "fix(nxp-sfp): shift gpio register offsets by 2" into integration

feat(nxp-clk): enable the A53 clock

Enable the A53 clock at 1GHz, the maximum frequency on S32G2 SoCs.

Change-Id: Ife96792faf8f3f46965bdcf4df75fcca5e39dc6e
Signed-off-by: Ghennadi Procopciuc <ghenn

feat(nxp-clk): enable the A53 clock

Enable the A53 clock at 1GHz, the maximum frequency on S32G2 SoCs.

Change-Id: Ife96792faf8f3f46965bdcf4df75fcca5e39dc6e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add ARM PLL ODIV enablement

Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.

Change-Id: I39115cb2

feat(nxp-clk): add ARM PLL ODIV enablement

Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.

Change-Id: I39115cb2cb754cee87d7b6b4aa7502c3f1ef37ce
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add ARM PLL enablement

Add the low-level implementation to enable the ARM PLL oscillator, which
is disabled by default when booting the SoC. It will be used by PLL
diviers, for which

feat(nxp-clk): add ARM PLL enablement

Add the low-level implementation to enable the ARM PLL oscillator, which
is disabled by default when booting the SoC. It will be used by PLL
diviers, for which support will be added later.

Change-Id: I964fa7374ea9a08c695009176eade01003c1d6c2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for clock muxes

The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.

Change-Id: I5fda8fffa0

feat(nxp-clk): set rate for clock muxes

The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.

Change-Id: I5fda8fffa0f46a4be96deac4d6a5a880c9f86ccf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c39640

feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <g

feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for PLL objects

Add implementation for ARM PLL rate set mechanism.

Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopci

feat(nxp-clk): set rate for PLL objects

Add implementation for ARM PLL rate set mechanism.

Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes

Set the parent for ARM PLL and MC_CGM muxes as part of the early clocks
enablement.

Change-Id: If88186caad520c3f7bb1fb602de526d940037a1c
Signe

feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes

Set the parent for ARM PLL and MC_CGM muxes as part of the early clocks
enablement.

Change-Id: If88186caad520c3f7bb1fb602de526d940037a1c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add MC_CGM clock objects

The MC_CGM1 clock objects will participate in A53 clocking.

Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi

feat(nxp-clk): add MC_CGM clock objects

The MC_CGM1 clock objects will participate in A53 clocking.

Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add set_parent callback

On S32CC SoCs, the set_parent operation will be used on clock modules
that are mux instances in order to establish the clock source. This will
be used for PLLs

feat(nxp-clk): add set_parent callback

On S32CC SoCs, the set_parent operation will be used on clock modules
that are mux instances in order to establish the clock source. This will
be used for PLLs and MC_CGM muxes.

Change-Id: I7228d379500ea790459b858da8fc0bdcbed4fd62
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for ARM PLL

Add all the clock objects needed to describe the ARM PLL, which can be
powered by either FXOSC or FIRC oscillators.

Change-Id: I2585ed38178ca1d5c5485adb

feat(nxp-clk): add clock objects for ARM PLL

Add all the clock objects needed to describe the ARM PLL, which can be
powered by either FXOSC or FIRC oscillators.

Change-Id: I2585ed38178ca1d5c5485adb38af1b3b8d94f1f6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add FXOSC clock enablement

Add the low-level implementation to enable the FXOSC oscillator, which
is disabled by default when booting the SoC. It will be used by PLLs,
for which suppo

feat(nxp-clk): add FXOSC clock enablement

Add the low-level implementation to enable the FXOSC oscillator, which
is disabled by default when booting the SoC. It will be used by PLLs,
for which support will be added later.

Change-Id: Ie784e4e29b8b4453b39d37594c311af940bebf92
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and L

feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and Linflex clocks. For now, it will only contain the
frequency set for FXOSC. More clock management will be added in the next
commits.

Change-Id: Ie85465884de02f5082185f91749f190f40249c2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): implement set_rate for oscillators

The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this

feat(nxp-clk): implement set_rate for oscillators

The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this capability.

Change-Id: I82d1545c63b3e15497c1c002ff9ec0d7bf990aa0
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add oscillator clock objects

The oscillator clock objects will be used to describe the FIRC, FXOSC,
and SIRC clocks, all of which are oscillators on S32CC SoCs.

Change-Id: Icf235cc9b

feat(nxp-clk): add oscillator clock objects

The oscillator clock objects will be used to describe the FIRC, FXOSC,
and SIRC clocks, all of which are oscillators on S32CC SoCs.

Change-Id: Icf235cc9b8f1d95d2c0051ce9a7655fd120289b8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add minimal set of S32CC clock ids

The clock IDs are organized into categories, which are determined based
on the first 2 MSB bits for each ID. Currently, there are two big
categories

feat(nxp-clk): add minimal set of S32CC clock ids

The clock IDs are organized into categories, which are determined based
on the first 2 MSB bits for each ID. Currently, there are two big
categories: hardware and software-defined clocks.

The first category refers to clock IDs understood by the S32CC PLL muxes
and MC_CGM module muxes and is immutable. The last category of the
clocks includes software-defined IDs for clocks to allow an easy
representation of the hierarchy.

Change-Id: Idc079feb3ca5f92d8bf337ef09efad006e267088
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-drivers): add clock skeleton for s32cc

The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b2

feat(nxp-drivers): add clock skeleton for s32cc

The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b212b67cf494a033c62fbfdcbe9b1a879
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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