Merge changes Ie8453359,Icd58a49c into integration

* changes:
docs: deprecate SPM_MM build option
docs: deprecate NS_TIMER_SWITCH build option

docs: deprecate SPM_MM build option

Following the ML post [1] deprecating the SPM-MM build option.

[1] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/Z6GAD7OG

docs: deprecate SPM_MM build option

Following the ML post [1] deprecating the SPM-MM build option.

[1] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/Z6GAD7OGKNDPNKECJ63HQZ4XEYUJXTNM/

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie845335989a6b11382ebe2f32962f534ad1bf8c6

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docs: deprecate NS_TIMER_SWITCH build option

Patch [1] deprecated NS_TIMER_SWITCH build option.
Mark it as such in documentation.

Fix build options deprecation/removal section indentation.

[1] htt

docs: deprecate NS_TIMER_SWITCH build option

Patch [1] deprecated NS_TIMER_SWITCH build option.
Mark it as such in documentation.

Fix build options deprecation/removal section indentation.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/42085

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icd58a49cfe8cc1cfd08bd1fb87d605c614b2fcc3

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docs: deprecate Arm RD1AE platform

RD1AE (Kronos) is now deprecated in TF-A v2.14. Emit a build-time
warning in platform.mk of that platform to make the status explicit.
Update docs/plat/index.rst t

docs: deprecate Arm RD1AE platform

RD1AE (Kronos) is now deprecated in TF-A v2.14. Emit a build-time
warning in platform.mk of that platform to make the status explicit.
Update docs/plat/index.rst to list RD1AE with deleted version set to
TBD.
Drop from the deprecated table platforms that were already deleted in
v2.13 (TC2, fvp_r, SGI-575, RD-N1-Edge, RD-V1, RD-V1-MC).

Change-Id: Ia334a1901fbf303e876e85c8075e2ac7e3fa0d67
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(docs): update context management's threat model" into integration

Merge "docs: add Architectural Feature Support reference" into integration

Merge "fix(security): add clrbhb support" into integration

docs: add Architectural Feature Support reference

Introduce a central document to track the status of Arm architectural
features in TF-A.

This aims to provide a single reference point to check whet

docs: add Architectural Feature Support reference

Introduce a central document to track the status of Arm architectural
features in TF-A.

This aims to provide a single reference point to check whether a given
feature is:
- explicitly supported in TF-A (OK)
- transparent from EL3 (no changes required) (NA)
- Analyzed but decided not to implemened (NO)
- Implementation in progress (WIP)
- not yet analyzed.

This reduces the current reliance on grepping the code, browsing JIRA,
or cross-referencing the Arm ARM to answer feature status queries.

The content is aligned with Arm’s yearly architectural feature updates
(see [Architecture Feature Descriptions](https://developer.arm.com/documentation/109697/latest/)).

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I32cc07268fc641180837a42a973308dab0824236

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Merge "docs: add dependabot patches for LTS" into integration

Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): suppo

Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): support BL32 (OP-TEE)

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Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): remove CVE_2022_23960 Cortex-X4
fix(security): remove CVE_2022_23960 Neoverse V3
fix(security): rem

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): remove CVE_2022_23960 Cortex-X4
fix(security): remove CVE_2022_23960 Neoverse V3
fix(security): remove CVE_2022_23960 Cortex-A720

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Merge "refactor(docs): deduplicate PSCI documentation" into integration

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.

Ref- https://developer.arm.com/documentation/102898/0108/

Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): remove CVE_2022_23960 Neoverse V3

Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https

fix(security): remove CVE_2022_23960 Neoverse V3

Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/107734/0002/The-Neoverse--V3--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 to avoid accidental enabling of this
workaround and using loop workaround.

This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670

Change-Id: I13b27c04c3da5ec80fa79422b4ef4fee64738caa
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): remove CVE_2022_23960 Cortex-A720

Cortex-A720 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https

fix(security): remove CVE_2022_23960 Cortex-A720

Cortex-A720 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/102530/0002/The-Cortex-A720--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 for Cortex-A720 to avoid accidental
enabling of this workaround and using loop workaround.

This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670

Change-Id: I3c68b5f5d85ede37a6a039369de8ed2aa9205395
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(docs): deduplicate PSCI documentation

It is already described in the porting guide and context management
sections so it's largely redundant. It also hasn't been updated for a
while despite

refactor(docs): deduplicate PSCI documentation

It is already described in the porting guide and context management
sections so it's largely redundant. It also hasn't been updated for a
while despite lots going on around PSCI so it's clearly not read often.
The only part that isn't is that for describing a new secure dispatcher,
which belongs in the porting guide.

Change-Id: Icdc53e19565f0785bc8a112e5eb49df1b365c66c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs(build): update GCC toolchain requirement to 14.3.Rel1" into integration

docs(rdaspen): bl32 and GPT support

Added optional BL32 support for the RDaspen platform to enable
Trusted OS integration when required.

Updated documentation to clarify that if BL32 is not set, BL

docs(rdaspen): bl32 and GPT support

Added optional BL32 support for the RDaspen platform to enable
Trusted OS integration when required.

Updated documentation to clarify that if BL32 is not set, BL33 will
load directly after BL31.

Revised the ARM_GPT_SUPPORT description to note that it must be
enabled when the FIP image resides in a GPT partition on Secure Flash.

Change-Id: I79905efd026994290d0bc6c07cdf1f5a903c9194
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platfor

Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platform hook for shared NV ctr

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docs(maintainers): update QTI platform maintainers

Add myself to the list of QTI platform maintainers.

Change-Id: I779f457cf075bf42acb62b75223912d7b4f1e95b
Signed-off-by: Sumit Garg <sumit.garg@oss

docs(maintainers): update QTI platform maintainers

Add myself to the list of QTI platform maintainers.

Change-Id: I779f457cf075bf42acb62b75223912d7b4f1e95b
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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docs(qti): add RB3Gen2 platform documentation

Add documentation for RB3Gen2 platform listing down step to build, flash
and boot up the platform with TF-A BL2 and BL31 support.

Change-Id: I361fec8fb

docs(qti): add RB3Gen2 platform documentation

Add documentation for RB3Gen2 platform listing down step to build, flash
and boot up the platform with TF-A BL2 and BL31 support.

Change-Id: I361fec8fb7a98b92fed3b1000f6f0c6f510c4887
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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docs(qti): move documentation under docs/plat/qti/

Move documentation under docs/plat/qti/ to become a consolidated place
for QTI platforms documentation.

Change-Id: Ief6f1f811de504761f00ce1acbd608

docs(qti): move documentation under docs/plat/qti/

Move documentation under docs/plat/qti/ to become a consolidated place
for QTI platforms documentation.

Change-Id: Ief6f1f811de504761f00ce1acbd608663eee344f
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): introduce SoC codename as Kodiak

Qualcomm has recently started using SoC codenames for upstream support
with Linux kernel being the first adoptor. Using SoC codenames for
upstream pro

refactor(qti): introduce SoC codename as Kodiak

Qualcomm has recently started using SoC codenames for upstream support
with Linux kernel being the first adoptor. Using SoC codenames for
upstream projects removes the need to follow different product names
like for kodiak which is also known as sc7280, qcm6490 etc.

Let's follow this practice of using SoC codenames for TF-A project too
beginning with Kodiak. While doing that let's refactor SoC and board
specific files where the existing support for sc7280 has been renamed to
sc7280_chrome to reflect it's usage.

Change-Id: I236fadf8ae9550f94deb05ebfed17e2ddbd69509
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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Merge "fix(cpufeat): don't overwrite PAuth keys with an erroneous cache clean" into integration

docs(build): update GCC toolchain requirement to 14.3.Rel1

Update documentation to reflect the use of GCC version 14.3.Rel1,
the latest production release available at:
https://developer.arm.com/dow

docs(build): update GCC toolchain requirement to 14.3.Rel1

Update documentation to reflect the use of GCC version 14.3.Rel1,
the latest production release available at:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I4387ccf519593b804d3e8541e8aaf9723a2aedeb

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