Merge "docs(build): update GCC toolchain requirement to 14.2.Rel1" into integration

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of in

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of initialising the context for the waking core (the warmboot
entrypoint for both). This is convenient because the calling core can
write the context while in coherency and the waking core will only need
the context after its entered coherency. This avoids any cache
maintenance and makes communication simple.

However, this has 3 main problems:
a) asymmetric feature support is problematic - the calling core has no
way of knowing the feature set of the waking core. If the two
diverge, the architectural feature discovery via ID registers breaks
down. We've thus far "fixed" this on a case by case basis which
doesn't scale and introduces redundancy.

b) powerdown abandon (pabandon) introduces a contradiction - the calling
core has to initialise the context for when the core wakes up, but
should the core not powerdown it needs its old context intact. The only
way to work around this is by keeping two copies of context which
incurs a runtime and memory overhead.

c) cm_prepare_el3_exit[_ns]() doesn't have access to the entrypoint but needs
it to make initialisation decisions. We can infer some of this from
registers that have already been written but this is awkwardly
limiting for what we can do. This also necessitates the split from
the context initialisation.

We can solve all three by a making a core be in full ownership of its
own context. The calling core then only writes entrypoint information
and nothing else. The waking core then initialises its own context as it
sees fit with full knowledge of the whole picture.

The only tricky bit is cache coherency - the waking core has to be able
to coherently observe its new entrypoint. Calling cores will write to
the shared region with coherent caches on. If we make sure to read the
context only after the waking core has entered coherency, then we can
avoid cache operations and let hardware handle everything.

We can skip the spsr check for FEAT_TCR2 as it doesn't make a
difference. We can also skip enabling it twice from generic code.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I86e7fe8b698191fc3b469e5ced1fd010f8754b0e

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Merge changes from topic "nrd1_deprecation" into integration

* changes:
docs(changelog): remove RD-E1-Edge platform's scope
docs(maintainers): add RD-V3 variants to maintained paths
feat(neove

Merge changes from topic "nrd1_deprecation" into integration

* changes:
docs(changelog): remove RD-E1-Edge platform's scope
docs(maintainers): add RD-V3 variants to maintained paths
feat(neoverse_rd): deprecate and remove RD-V1 platform variants
feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants
feat(neoverse_rd): deprecate and remove SGI-575 platform

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Merge changes Ie33671b0,I1543aa6d into integration

* changes:
docs(fvp): clarify what `FVP` means
fix(fvp): allow PSCI 0.2 in the device tree

docs(rmmd): document the EL3-RMM IDE KM Interface

This patch documents the EL3-RMM IDE KM interface.

Four IDE Key management smc calls have been added:
- RMM_IDE_KEY_PROG()
- RMM_IDE_KEY_SET_GO()

docs(rmmd): document the EL3-RMM IDE KM Interface

This patch documents the EL3-RMM IDE KM interface.

Four IDE Key management smc calls have been added:
- RMM_IDE_KEY_PROG()
- RMM_IDE_KEY_SET_GO()
- RMM_IDE_KEY_SET_STOP()
- RMM_IDE_KM_PULL_RESPONSE()

Change-Id: Iea357ec16a2bee88573266c7a5c9fb36025f15f1
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "lto-by-default" into integration

* changes:
fix(libc): make sure __init functions are garbage collected
fix(platforms): remove platform_core_pos_helper()

docs(maintainers): add RD-V3 variants to maintained paths

add the path for RD-V3 and variants to the maintained paths under
Neoverse reference design platforms.

Signed-off-by: Rohit Mathew <rohit.m

docs(maintainers): add RD-V3 variants to maintained paths

add the path for RD-V3 and variants to the maintained paths under
Neoverse reference design platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib9323143bedf49304ed6f07b20dc39b8821464c5

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feat(neoverse_rd): deprecate and remove RD-V1 platform variants

deprecate and remove support for RD-V1 and RD-V1-MC platform variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id:

feat(neoverse_rd): deprecate and remove RD-V1 platform variants

deprecate and remove support for RD-V1 and RD-V1-MC platform variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ifab7b95e00615806986e316e0bde7788dc8af04f

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feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants

deprecate and remove support for RD-N1-Edge and RD-N1-Edgex2 platform
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.co

feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants

deprecate and remove support for RD-N1-Edge and RD-N1-Edgex2 platform
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I59dce73b70014b3416d89b0d024d7204356b1b77

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feat(neoverse_rd): deprecate and remove SGI-575 platform

deprecate and remove support for SGI-575 platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iffee2fa8f4faa463c4b4df5911

feat(neoverse_rd): deprecate and remove SGI-575 platform

deprecate and remove support for SGI-575 platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iffee2fa8f4faa463c4b4df591182f72a461c880b

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fix(xlat): remove xlat_mpu

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this library. Support for it never went out of
"experimental" so it does not appea

fix(xlat): remove xlat_mpu

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this library. Support for it never went out of
"experimental" so it does not appear to be finished.

Change-Id: I76499b92ca4368651330f17dc80803991158cc36
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(libc): make sure __init functions are garbage collected

RECLAIM_INIT_CODE is useful to remove code that is only necessary during
boot. However, these functions are generally called once and as s

fix(libc): make sure __init functions are garbage collected

RECLAIM_INIT_CODE is useful to remove code that is only necessary during
boot. However, these functions are generally called once and as such
prime candidates for inlining. When building with LTO, the compiler is
pretty good at inlining every single one, making this option pointless.

So tell the compiler to not inline these functions. This ensures they
are kept separate and they can be garbage collected later. This is
expected to cost a little bit of speed due to the extra branching.

Change-Id: Ie83a9ec8db03cb42139742fc6d728d12ce8549d3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs: list removal of fvp_r" into integration

Merge changes I2d140b32,Id59ae926,I31c71551 into integration

* changes:
feat(mt8189): add GPIO support
feat(mt8189): initialize platform for MT8189
refactor(mediatek): move headers to common f

Merge changes I2d140b32,Id59ae926,I31c71551 into integration

* changes:
feat(mt8189): add GPIO support
feat(mt8189): initialize platform for MT8189
refactor(mediatek): move headers to common folder

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docs(build): update GCC toolchain requirement to 14.2.Rel1

Update documentation to reflect the use of GCC version 14.2.Rel1,
the latest production release available at:
https://developer.arm.com/dow

docs(build): update GCC toolchain requirement to 14.2.Rel1

Update documentation to reflect the use of GCC version 14.2.Rel1,
the latest production release available at:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads

TF-A is built in CI using x86_64 Linux-hosted cross toolchains:
---------------------------------------------------------------
* AArch32 bare-metal target (arm-none-eabi)
* AArch64 bare-metal target (aarch64-none-elf)

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I4cd2c16fa9daac1ce518d2280169e92562e3766d

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docs: list removal of fvp_r

Commit 2cadf21bc removed fvp_r but did not list it as such. Do that.

Change-Id: I84e83196add3d0f912fd503cd253bc5496647dd6
Signed-off-by: Boyan Karatotev <boyan.karatotev

docs: list removal of fvp_r

Commit 2cadf21bc removed fvp_r but did not list it as such. Do that.

Change-Id: I84e83196add3d0f912fd503cd253bc5496647dd6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(plat): remove fvp_r" into integration

fix(plat): remove fvp_r

The platform has not been maintained for some years and is generally
broken. Remove it to avoid confusion.

Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88
Signed-off-by

fix(plat): remove fvp_r

The platform has not been maintained for some years and is generally
broken. Remove it to avoid confusion.

Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs: add playbook for new releases" into integration

feat(mt8189): initialize platform for MT8189

- Add basic platform setup.
- Add MT8189 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.

Change-Id: Id59a

feat(mt8189): initialize platform for MT8189

- Add basic platform setup.
- Add MT8189 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.

Change-Id: Id59ae9265983defb46e27befabfd5c30b2b4a5a6
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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docs: add playbook for new releases

Change-Id: I76a2a84b176791e16372dab8bf565e48223a6756
Signed-off-by: Chris Palmer <palmer@google.com>

docs(prerequisites): update mbedtls to v3.6.3

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I62bc0fd6e40a38143ad3118a2e8e8d63c728a675

docs(fvp): clarify what `FVP` means

An FVP, as a general Arm product, is a simulation of any kind of system.
This includes all such models from FVP_TC4, FVP_RD_V3, to FVP_Base and
others. On the oth

docs(fvp): clarify what `FVP` means

An FVP, as a general Arm product, is a simulation of any kind of system.
This includes all such models from FVP_TC4, FVP_RD_V3, to FVP_Base and
others. On the other hand, an FVP as a TF-A platform means systems that
are compatible with FVP_Base. This, however, is an implicit assumption
and the term "FVP" causes ambiguity when used by TF-A developers and
interpreted by outsiders.

This patch makes this assumption explicit with a brief explanation of
the ambiguity and by specifically stating which FVPs are supported by
our fvp platform. For clarity, non-base models are removed from the list
as they have their own separate platform ports and dedicated
documentation.

Change-Id: Ie33671b09d951de0c6120061b2f4a084fd7e510a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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docs: clarify multiple UUID support in ffa manifest

If a partition supports multiple UUID, the UUID property in the list
of partition properties in the FF-A manifest must be a list or array.
Update

docs: clarify multiple UUID support in ffa manifest

If a partition supports multiple UUID, the UUID property in the list
of partition properties in the FF-A manifest must be a list or array.
Update the document to clarify the same.

Change-Id: Id13fe8dbf57a00e5cd186158270b716a4a9aedf7
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

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