| 5283962e | 31-Jan-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Add ARMv8.3-PAuth registers to CPU context
ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indire
Add ARMv8.3-PAuth registers to CPU context
ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indirect branch, or as a load.
This feature is supported only in AArch64 state.
This feature is mandatory in ARMv8.3 implementations.
This feature adds several registers to EL1. A new option called
CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save
them during Non-secure <-> Secure world switches. This option must be
enabled if the hardware has the registers or the values will be leaked
during world switches.
To prevent leaks, this patch also disables pointer authentication in the
Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will
be trapped in EL3.
Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 39718ea5 | 27-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1834 from thloh85-intel/s10_bl31
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform |
| 5c6aa01a | 25-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| 5cc8c7ba | 25-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 1220197 for Cortex-A76
Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to t
Add workaround for errata 1220197 for Cortex-A76
Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.
Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| 508d7110 | 21-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address t
Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.
Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| 98551591 | 25-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 790748 for Cortex-A75
Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.
Change-Id: Ifdd19dbcdb71bb0
Add workaround for errata 790748 for Cortex-A75
Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.
Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| 5f5d1ed7 | 20-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection l
Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| e6cab15d | 21-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 855423 of Cortex-A73
Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.
Change-Id: I67fb62c0b
Add workaround for errata 855423 of Cortex-A73
Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.
Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| 1cf55aba | 26-Feb-2019 |
Tien Hock, Loh <tien.hock.loh@intel.com> |
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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|
| ab3d2247 | 22-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1836 from Yann-lms/docs_and_m4
Update documentation for STM32MP1 and add Cortex-M4 support |
| 5ba32a76 | 21-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1828 from uarif1/master
Introduce Versatile Express FVP platform to arm-trusted-firmware. |
| 774b4a81 | 20-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
docs: stm32mp1: add links to documentation
A link to st.com page describing STM32MP1 is added.
Add the information about Cortex-M4 embedded in STM32MP1.
Correct typo for u-boot command.
Change-Id:
docs: stm32mp1: add links to documentation
A link to st.com page describing STM32MP1 is added.
Add the information about Cortex-M4 embedded in STM32MP1.
Correct typo for u-boot command.
Change-Id: Ie900f6ee59461c5e7ad8a8b06854abaf41fca3ce
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| c8a6af66 | 20-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1832 from jts-arm/docs
docs: Document romlib design |
| 5dbc783a | 05-Feb-2019 |
Usama Arif <usama.arif@arm.com> |
Documentation for Versatile Express Fixed Virtual Platforms
This documentation contains information about the boot sequence,
code location and build procedure for fvp_ve platform.
Change-Id: I33990
Documentation for Versatile Express Fixed Virtual Platforms
This documentation contains information about the boot sequence,
code location and build procedure for fvp_ve platform.
Change-Id: I339903f663cc625cfabc75ed8e4accb8b2c3917c
Signed-off-by: Usama Arif <usama.arif@arm.com>
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|
| e36950bd | 30-Jan-2019 |
Sathees Balya <sathees.balya@arm.com> |
docs: Document romlib design
Change-Id: I2b75be16f452a8ab7c2445ccd519fb057a135812
Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com>
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.co
docs: Document romlib design
Change-Id: I2b75be16f452a8ab7c2445ccd519fb057a135812
Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com>
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| d71446c3 | 19-Feb-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
docs: Update documentation about ARMv8.2-TTCNP
Commit 2559b2c8256f ("xlat v2: Dynamically detect need for CnP bit")
modified the code to convert the compile-time check for ARMv8.2-TTCNP to
a runtime
docs: Update documentation about ARMv8.2-TTCNP
Commit 2559b2c8256f ("xlat v2: Dynamically detect need for CnP bit")
modified the code to convert the compile-time check for ARMv8.2-TTCNP to
a runtime check, but forgot to update the documentation associated to it.
Change-Id: I6d33a4de389d976dbdcce65d8fdf138959530669
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| 8f457dac | 13-Feb-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
docs: Update note about plat/arm in Porting Guide
Platforms are not allowed to use any file inside include/plat/arm or
plat/arm to prevent dependencies between Arm platforms and non-Arm
platforms.
docs: Update note about plat/arm in Porting Guide
Platforms are not allowed to use any file inside include/plat/arm or
plat/arm to prevent dependencies between Arm platforms and non-Arm
platforms.
Change-Id: I6dc336ab71134c8d2758761fac0e4716e2d7e6ff
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| 288abd63 | 12-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1818 from pbeesley-arm/doc-links
doc: Fix broken external links |
| dd4e9a7d | 08-Feb-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Fix broken external links
Using Sphinx linkcheck on the TF-A docs revealed some broken
or permanently-redirected links. These have been updated where
possible.
Change-Id: Ie1fead47972ede333197
doc: Fix broken external links
Using Sphinx linkcheck on the TF-A docs revealed some broken
or permanently-redirected links. These have been updated where
possible.
Change-Id: Ie1fead47972ede3331973759b50ee466264bd2ee
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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|
| f3cacada | 08-Feb-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Doc: Remove useless escape characters
Just like has been done in the porting guide a couple of patches
earlier, kill all escaped underscore characters in all documents.
Change-Id: I7fb5b80641284976
Doc: Remove useless escape characters
Just like has been done in the porting guide a couple of patches
earlier, kill all escaped underscore characters in all documents.
Change-Id: I7fb5b806412849761d9221a6ce3cbd95ec43d611
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 337e2f1f | 08-Feb-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Miscellaneous doc fixes/enhancements
Change-Id: I915303cea787d9fb188428b98ac6cfc610cc4470
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> |
| 9aa6b637 | 08-Feb-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Porting Guide: Fix some broken links
Fix links to SCC and FreeBSD. Direct links do not need any special
formatting.
Change-Id: I00f7343d029a30ec02dfaa0ef393b3197260cab9
Signed-off-by: Sandrine Bail
Porting Guide: Fix some broken links
Fix links to SCC and FreeBSD. Direct links do not need any special
formatting.
Change-Id: I00f7343d029a30ec02dfaa0ef393b3197260cab9
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| ab4a90cd | 08-Feb-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Porting Guide: Remove useless escape characters
Replace all occurences of escaped underscore characters by plain ones.
This makes the text version of the porting guide easier to read and
grep into.
Porting Guide: Remove useless escape characters
Replace all occurences of escaped underscore characters by plain ones.
This makes the text version of the porting guide easier to read and
grep into.
Change-Id: I7bf3b292b686be4c6d847a467b6708ac16544c90
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 30490b15 | 06-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1785 from vwadekar/tf2.0-tegra-downstream-rebase-1.25.19
Tf2.0 tegra downstream rebase 1.25.19 |
| a474d3d7 | 03-Jan-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
docs: add Tegra186 information to nvidia-tegra.rst
This patch adds information about the Tegra186 platforms to the
docs.
Change-Id: I69525c60a0126030dc15505ec7f02ccf8250be6f
Signed-off-by: Varun Wa
docs: add Tegra186 information to nvidia-tegra.rst
This patch adds information about the Tegra186 platforms to the
docs.
Change-Id: I69525c60a0126030dc15505ec7f02ccf8250be6f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|