1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_def.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <debug.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <platform.h> 17 #include <ras.h> 18 19 /* 20 * Placeholder variables for copying the arguments that have been passed to 21 * BL31 from BL2. 22 */ 23 static entry_point_info_t bl32_image_ep_info; 24 static entry_point_info_t bl33_image_ep_info; 25 26 /* 27 * Check that BL31_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page 28 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 29 */ 30 CASSERT(BL31_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 31 32 /* Weak definitions may be overridden in specific ARM standard platform */ 33 #pragma weak bl31_early_platform_setup2 34 #pragma weak bl31_platform_setup 35 #pragma weak bl31_plat_arch_setup 36 #pragma weak bl31_plat_get_next_image_ep_info 37 38 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 39 BL31_BASE, \ 40 BL31_END - BL31_BASE, \ 41 MT_MEMORY | MT_RW | MT_SECURE) 42 43 /******************************************************************************* 44 * Return a pointer to the 'entry_point_info' structure of the next image for the 45 * security state specified. BL33 corresponds to the non-secure image type 46 * while BL32 corresponds to the secure image type. A NULL pointer is returned 47 * if the image does not exist. 48 ******************************************************************************/ 49 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 50 { 51 entry_point_info_t *next_image_info; 52 53 assert(sec_state_is_valid(type)); 54 next_image_info = (type == NON_SECURE) 55 ? &bl33_image_ep_info : &bl32_image_ep_info; 56 /* 57 * None of the images on the ARM development platforms can have 0x0 58 * as the entrypoint 59 */ 60 if (next_image_info->pc) 61 return next_image_info; 62 else 63 return NULL; 64 } 65 66 /******************************************************************************* 67 * Perform any BL31 early platform setup common to ARM standard platforms. 68 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 69 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 70 * done before the MMU is initialized so that the memory layout can be used 71 * while creating page tables. BL2 has flushed this information to memory, so 72 * we are guaranteed to pick up good data. 73 ******************************************************************************/ 74 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 75 uintptr_t hw_config, void *plat_params_from_bl2) 76 { 77 /* Initialize the console to provide early debug support */ 78 arm_console_boot_init(); 79 80 #if RESET_TO_BL31 81 /* There are no parameters from BL2 if BL31 is a reset vector */ 82 assert(from_bl2 == NULL); 83 assert(plat_params_from_bl2 == NULL); 84 85 # ifdef BL32_BASE 86 /* Populate entry point information for BL32 */ 87 SET_PARAM_HEAD(&bl32_image_ep_info, 88 PARAM_EP, 89 VERSION_1, 90 0); 91 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 92 bl32_image_ep_info.pc = BL32_BASE; 93 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 94 # endif /* BL32_BASE */ 95 96 /* Populate entry point information for BL33 */ 97 SET_PARAM_HEAD(&bl33_image_ep_info, 98 PARAM_EP, 99 VERSION_1, 100 0); 101 /* 102 * Tell BL31 where the non-trusted software image 103 * is located and the entry state information 104 */ 105 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 106 107 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 108 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 109 110 # if ARM_LINUX_KERNEL_AS_BL33 111 /* 112 * According to the file ``Documentation/arm64/booting.txt`` of the 113 * Linux kernel tree, Linux expects the physical address of the device 114 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 115 * must be 0. 116 */ 117 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 118 bl33_image_ep_info.args.arg1 = 0U; 119 bl33_image_ep_info.args.arg2 = 0U; 120 bl33_image_ep_info.args.arg3 = 0U; 121 # endif 122 123 #else /* RESET_TO_BL31 */ 124 125 /* 126 * In debug builds, we pass a special value in 'plat_params_from_bl2' 127 * to verify platform parameters from BL2 to BL31. 128 * In release builds, it's not used. 129 */ 130 assert(((unsigned long long)plat_params_from_bl2) == 131 ARM_BL31_PLAT_PARAM_VAL); 132 133 /* 134 * Check params passed from BL2 should not be NULL, 135 */ 136 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 137 assert(params_from_bl2 != NULL); 138 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 139 assert(params_from_bl2->h.version >= VERSION_2); 140 141 bl_params_node_t *bl_params = params_from_bl2->head; 142 143 /* 144 * Copy BL33 and BL32 (if present), entry point information. 145 * They are stored in Secure RAM, in BL2's address space. 146 */ 147 while (bl_params != NULL) { 148 if (bl_params->image_id == BL32_IMAGE_ID) 149 bl32_image_ep_info = *bl_params->ep_info; 150 151 if (bl_params->image_id == BL33_IMAGE_ID) 152 bl33_image_ep_info = *bl_params->ep_info; 153 154 bl_params = bl_params->next_params_info; 155 } 156 157 if (bl33_image_ep_info.pc == 0U) 158 panic(); 159 #endif /* RESET_TO_BL31 */ 160 } 161 162 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 163 u_register_t arg2, u_register_t arg3) 164 { 165 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 166 167 /* 168 * Initialize Interconnect for this cluster during cold boot. 169 * No need for locks as no other CPU is active. 170 */ 171 plat_arm_interconnect_init(); 172 173 /* 174 * Enable Interconnect coherency for the primary CPU's cluster. 175 * Earlier bootloader stages might already do this (e.g. Trusted 176 * Firmware's BL1 does it) but we can't assume so. There is no harm in 177 * executing this code twice anyway. 178 * Platform specific PSCI code will enable coherency for other 179 * clusters. 180 */ 181 plat_arm_interconnect_enter_coherency(); 182 } 183 184 /******************************************************************************* 185 * Perform any BL31 platform setup common to ARM standard platforms 186 ******************************************************************************/ 187 void arm_bl31_platform_setup(void) 188 { 189 /* Initialize the GIC driver, cpu and distributor interfaces */ 190 plat_arm_gic_driver_init(); 191 plat_arm_gic_init(); 192 193 #if RESET_TO_BL31 194 /* 195 * Do initial security configuration to allow DRAM/device access 196 * (if earlier BL has not already done so). 197 */ 198 plat_arm_security_setup(); 199 200 #if defined(PLAT_ARM_MEM_PROT_ADDR) 201 arm_nor_psci_do_dyn_mem_protect(); 202 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 203 204 #endif /* RESET_TO_BL31 */ 205 206 /* Enable and initialize the System level generic timer */ 207 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 208 CNTCR_FCREQ(0U) | CNTCR_EN); 209 210 /* Allow access to the System counter timer module */ 211 arm_configure_sys_timer(); 212 213 /* Initialize power controller before setting up topology */ 214 plat_arm_pwrc_setup(); 215 216 #if RAS_EXTENSION 217 ras_init(); 218 #endif 219 } 220 221 /******************************************************************************* 222 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 223 * standard platforms 224 * Perform BL31 platform setup 225 ******************************************************************************/ 226 void arm_bl31_plat_runtime_setup(void) 227 { 228 #if MULTI_CONSOLE_API 229 console_switch_state(CONSOLE_FLAG_RUNTIME); 230 #else 231 console_uninit(); 232 #endif 233 234 /* Initialize the runtime console */ 235 arm_console_runtime_init(); 236 } 237 238 void bl31_platform_setup(void) 239 { 240 arm_bl31_platform_setup(); 241 } 242 243 void bl31_plat_runtime_setup(void) 244 { 245 arm_bl31_plat_runtime_setup(); 246 } 247 248 /******************************************************************************* 249 * Perform the very early platform specific architectural setup shared between 250 * ARM standard platforms. This only does basic initialization. Later 251 * architectural setup (bl31_arch_setup()) does not do anything platform 252 * specific. 253 ******************************************************************************/ 254 void arm_bl31_plat_arch_setup(void) 255 { 256 const mmap_region_t bl_regions[] = { 257 MAP_BL31_TOTAL, 258 ARM_MAP_BL_RO, 259 #if USE_ROMLIB 260 ARM_MAP_ROMLIB_CODE, 261 ARM_MAP_ROMLIB_DATA, 262 #endif 263 #if USE_COHERENT_MEM 264 ARM_MAP_BL_COHERENT_RAM, 265 #endif 266 {0} 267 }; 268 269 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 270 271 enable_mmu_el3(0); 272 273 arm_setup_romlib(); 274 } 275 276 void bl31_plat_arch_setup(void) 277 { 278 arm_bl31_plat_arch_setup(); 279 } 280