1Trusted Firmware-A Porting Guide 2================================ 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Please note that this document has been updated for the new platform API 16as required by the PSCI v1.0 implementation. Please refer to the 17`Migration Guide`_ for the previous platform API. 18 19Porting Trusted Firmware-A (TF-A) to a new platform involves making some 20mandatory and optional modifications for both the cold and warm boot paths. 21Modifications consist of: 22 23- Implementing a platform-specific function or variable, 24- Setting up the execution context in a certain way, or 25- Defining certain constants (for example #defines). 26 27The platform-specific functions and variables are declared in 28`include/plat/common/platform.h`_. The firmware provides a default implementation 29of variables and functions to fulfill the optional requirements. These 30implementations are all weakly defined; they are provided to ease the porting 31effort. Each platform port can override them with its own implementation if the 32default implementation is inadequate. 33 34Platform ports that want to be aligned with standard Arm platforms (for example 35FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the 36corresponding source files in ``plat/arm/common/``. These provide standard 37implementations for some of the required platform porting functions. However, 38using these functions requires the platform port to implement additional 39Arm standard platform porting functions. These additional functions are not 40documented here. 41 42Some modifications are common to all Boot Loader (BL) stages. Section 2 43discusses these in detail. The subsequent sections discuss the remaining 44modifications for each BL stage in detail. 45 46This document should be read in conjunction with the TF-A `User Guide`_. 47 48Please refer to the `Platform compatibility policy`_ for the policy regarding 49compatibility and deprecation of these porting interfaces. 50 51Common modifications 52-------------------- 53 54This section covers the modifications that should be made by the platform for 55each BL stage to correctly port the firmware stack. They are categorized as 56either mandatory or optional. 57 58Common mandatory modifications 59------------------------------ 60 61A platform port must enable the Memory Management Unit (MMU) as well as the 62instruction and data caches for each BL stage. Setting up the translation 63tables is the responsibility of the platform port because memory maps differ 64across platforms. A memory translation library (see ``lib/xlat_tables/``) is 65provided to help in this setup. 66 67Note that although this library supports non-identity mappings, this is intended 68only for re-mapping peripheral physical addresses and allows platforms with high 69I/O addresses to reduce their virtual address space. All other addresses 70corresponding to code and data must currently use an identity mapping. 71 72Also, the only translation granule size supported in TF-A is 4KB, as various 73parts of the code assume that is the case. It is not possible to switch to 7416 KB or 64 KB granule sizes at the moment. 75 76In Arm standard platforms, each BL stage configures the MMU in the 77platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 78an identity mapping for all addresses. 79 80If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 81block of identity mapped secure memory with Device-nGnRE attributes aligned to 82page boundary (4K) for each BL stage. All sections which allocate coherent 83memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 84section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 85possible for the firmware to place variables in it using the following C code 86directive: 87 88:: 89 90 __section("bakery_lock") 91 92Or alternatively the following assembler code directive: 93 94:: 95 96 .section bakery_lock 97 98The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 99used to allocate any data structures that are accessed both when a CPU is 100executing with its MMU and caches enabled, and when it's running with its MMU 101and caches disabled. Examples are given below. 102 103The following variables, functions and constants must be defined by the platform 104for the firmware to work correctly. 105 106File : platform\_def.h [mandatory] 107~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 108 109Each platform must ensure that a header file of this name is in the system 110include path with the following constants defined. This may require updating the 111list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the Arm development 112platforms, this file is found in ``plat/arm/board/<plat_name>/include/``. 113 114Platform ports may optionally use the file `include/plat/common/common\_def.h`_, 115which provides typical values for some of the constants below. These values are 116likely to be suitable for all platform ports. 117 118Platform ports that want to be aligned with standard Arm platforms (for example 119FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides 120standard values for some of the constants below. However, this requires the 121platform port to define additional platform porting constants in 122``platform_def.h``. These additional constants are not documented here. 123 124- **#define : PLATFORM\_LINKER\_FORMAT** 125 126 Defines the linker format used by the platform, for example 127 ``elf64-littleaarch64``. 128 129- **#define : PLATFORM\_LINKER\_ARCH** 130 131 Defines the processor architecture for the linker by the platform, for 132 example ``aarch64``. 133 134- **#define : PLATFORM\_STACK\_SIZE** 135 136 Defines the normal stack memory available to each CPU. This constant is used 137 by `plat/common/aarch64/platform\_mp\_stack.S`_ and 138 `plat/common/aarch64/platform\_up\_stack.S`_. 139 140- **define : CACHE\_WRITEBACK\_GRANULE** 141 142 Defines the size in bits of the largest cache line across all the cache 143 levels in the platform. 144 145- **#define : FIRMWARE\_WELCOME\_STR** 146 147 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 148 function. 149 150- **#define : PLATFORM\_CORE\_COUNT** 151 152 Defines the total number of CPUs implemented by the platform across all 153 clusters in the system. 154 155- **#define : PLAT\_NUM\_PWR\_DOMAINS** 156 157 Defines the total number of nodes in the power domain topology 158 tree at all the power domain levels used by the platform. 159 This macro is used by the PSCI implementation to allocate 160 data structures to represent power domain topology. 161 162- **#define : PLAT\_MAX\_PWR\_LVL** 163 164 Defines the maximum power domain level that the power management operations 165 should apply to. More often, but not always, the power domain level 166 corresponds to affinity level. This macro allows the PSCI implementation 167 to know the highest power domain level that it should consider for power 168 management operations in the system that the platform implements. For 169 example, the Base AEM FVP implements two clusters with a configurable 170 number of CPUs and it reports the maximum power domain level as 1. 171 172- **#define : PLAT\_MAX\_OFF\_STATE** 173 174 Defines the local power state corresponding to the deepest power down 175 possible at every power domain level in the platform. The local power 176 states for each level may be sparsely allocated between 0 and this value 177 with 0 being reserved for the RUN state. The PSCI implementation uses this 178 value to initialize the local power states of the power domain nodes and 179 to specify the requested power state for a PSCI\_CPU\_OFF call. 180 181- **#define : PLAT\_MAX\_RET\_STATE** 182 183 Defines the local power state corresponding to the deepest retention state 184 possible at every power domain level in the platform. This macro should be 185 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the 186 PSCI implementation to distinguish between retention and power down local 187 power states within PSCI\_CPU\_SUSPEND call. 188 189- **#define : PLAT\_MAX\_PWR\_LVL\_STATES** 190 191 Defines the maximum number of local power states per power domain level 192 that the platform supports. The default value of this macro is 2 since 193 most platforms just support a maximum of two local power states at each 194 power domain level (power-down and retention). If the platform needs to 195 account for more local power states, then it must redefine this macro. 196 197 Currently, this macro is used by the Generic PSCI implementation to size 198 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting. 199 200- **#define : BL1\_RO\_BASE** 201 202 Defines the base address in secure ROM where BL1 originally lives. Must be 203 aligned on a page-size boundary. 204 205- **#define : BL1\_RO\_LIMIT** 206 207 Defines the maximum address in secure ROM that BL1's actual content (i.e. 208 excluding any data section allocated at runtime) can occupy. 209 210- **#define : BL1\_RW\_BASE** 211 212 Defines the base address in secure RAM where BL1's read-write data will live 213 at runtime. Must be aligned on a page-size boundary. 214 215- **#define : BL1\_RW\_LIMIT** 216 217 Defines the maximum address in secure RAM that BL1's read-write data can 218 occupy at runtime. 219 220- **#define : BL2\_BASE** 221 222 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 223 Must be aligned on a page-size boundary. This constant is not applicable 224 when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2\_LIMIT** 227 228 Defines the maximum address in secure RAM that the BL2 image can occupy. 229 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 230 231- **#define : BL2\_RO\_BASE** 232 233 Defines the base address in secure XIP memory where BL2 RO section originally 234 lives. Must be aligned on a page-size boundary. This constant is only needed 235 when BL2_IN_XIP_MEM is set to '1'. 236 237- **#define : BL2\_RO\_LIMIT** 238 239 Defines the maximum address in secure XIP memory that BL2's actual content 240 (i.e. excluding any data section allocated at runtime) can occupy. This 241 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 242 243- **#define : BL2\_RW\_BASE** 244 245 Defines the base address in secure RAM where BL2's read-write data will live 246 at runtime. Must be aligned on a page-size boundary. This constant is only 247 needed when BL2_IN_XIP_MEM is set to '1'. 248 249- **#define : BL2\_RW\_LIMIT** 250 251 Defines the maximum address in secure RAM that BL2's read-write data can 252 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 253 to '1'. 254 255- **#define : BL31\_BASE** 256 257 Defines the base address in secure RAM where BL2 loads the BL31 binary 258 image. Must be aligned on a page-size boundary. 259 260- **#define : BL31\_LIMIT** 261 262 Defines the maximum address in secure RAM that the BL31 image can occupy. 263 264For every image, the platform must define individual identifiers that will be 265used by BL1 or BL2 to load the corresponding image into memory from non-volatile 266storage. For the sake of performance, integer numbers will be used as 267identifiers. The platform will use those identifiers to return the relevant 268information about the image to be loaded (file handler, load address, 269authentication information, etc.). The following image identifiers are 270mandatory: 271 272- **#define : BL2\_IMAGE\_ID** 273 274 BL2 image identifier, used by BL1 to load BL2. 275 276- **#define : BL31\_IMAGE\_ID** 277 278 BL31 image identifier, used by BL2 to load BL31. 279 280- **#define : BL33\_IMAGE\_ID** 281 282 BL33 image identifier, used by BL2 to load BL33. 283 284If Trusted Board Boot is enabled, the following certificate identifiers must 285also be defined: 286 287- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID** 288 289 BL2 content certificate identifier, used by BL1 to load the BL2 content 290 certificate. 291 292- **#define : TRUSTED\_KEY\_CERT\_ID** 293 294 Trusted key certificate identifier, used by BL2 to load the trusted key 295 certificate. 296 297- **#define : SOC\_FW\_KEY\_CERT\_ID** 298 299 BL31 key certificate identifier, used by BL2 to load the BL31 key 300 certificate. 301 302- **#define : SOC\_FW\_CONTENT\_CERT\_ID** 303 304 BL31 content certificate identifier, used by BL2 to load the BL31 content 305 certificate. 306 307- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID** 308 309 BL33 key certificate identifier, used by BL2 to load the BL33 key 310 certificate. 311 312- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID** 313 314 BL33 content certificate identifier, used by BL2 to load the BL33 content 315 certificate. 316 317- **#define : FWU\_CERT\_ID** 318 319 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the 320 FWU content certificate. 321 322- **#define : PLAT\_CRYPTOCELL\_BASE** 323 324 This defines the base address of Arm® TrustZone® CryptoCell and must be 325 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 326 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 327 set. 328 329If the AP Firmware Updater Configuration image, BL2U is used, the following 330must also be defined: 331 332- **#define : BL2U\_BASE** 333 334 Defines the base address in secure memory where BL1 copies the BL2U binary 335 image. Must be aligned on a page-size boundary. 336 337- **#define : BL2U\_LIMIT** 338 339 Defines the maximum address in secure memory that the BL2U image can occupy. 340 341- **#define : BL2U\_IMAGE\_ID** 342 343 BL2U image identifier, used by BL1 to fetch an image descriptor 344 corresponding to BL2U. 345 346If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following 347must also be defined: 348 349- **#define : SCP\_BL2U\_IMAGE\_ID** 350 351 SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor 352 corresponding to SCP\_BL2U. 353 NOTE: TF-A does not provide source code for this image. 354 355If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must 356also be defined: 357 358- **#define : NS\_BL1U\_BASE** 359 360 Defines the base address in non-secure ROM where NS\_BL1U executes. 361 Must be aligned on a page-size boundary. 362 NOTE: TF-A does not provide source code for this image. 363 364- **#define : NS\_BL1U\_IMAGE\_ID** 365 366 NS\_BL1U image identifier, used by BL1 to fetch an image descriptor 367 corresponding to NS\_BL1U. 368 369If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also 370be defined: 371 372- **#define : NS\_BL2U\_BASE** 373 374 Defines the base address in non-secure memory where NS\_BL2U executes. 375 Must be aligned on a page-size boundary. 376 NOTE: TF-A does not provide source code for this image. 377 378- **#define : NS\_BL2U\_IMAGE\_ID** 379 380 NS\_BL2U image identifier, used by BL1 to fetch an image descriptor 381 corresponding to NS\_BL2U. 382 383For the the Firmware update capability of TRUSTED BOARD BOOT, the following 384macros may also be defined: 385 386- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES** 387 388 Total number of images that can be loaded simultaneously. If the platform 389 doesn't specify any value, it defaults to 10. 390 391If a SCP\_BL2 image is supported by the platform, the following constants must 392also be defined: 393 394- **#define : SCP\_BL2\_IMAGE\_ID** 395 396 SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory 397 from platform storage before being transfered to the SCP. 398 399- **#define : SCP\_FW\_KEY\_CERT\_ID** 400 401 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key 402 certificate (mandatory when Trusted Board Boot is enabled). 403 404- **#define : SCP\_FW\_CONTENT\_CERT\_ID** 405 406 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2 407 content certificate (mandatory when Trusted Board Boot is enabled). 408 409If a BL32 image is supported by the platform, the following constants must 410also be defined: 411 412- **#define : BL32\_IMAGE\_ID** 413 414 BL32 image identifier, used by BL2 to load BL32. 415 416- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID** 417 418 BL32 key certificate identifier, used by BL2 to load the BL32 key 419 certificate (mandatory when Trusted Board Boot is enabled). 420 421- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID** 422 423 BL32 content certificate identifier, used by BL2 to load the BL32 content 424 certificate (mandatory when Trusted Board Boot is enabled). 425 426- **#define : BL32\_BASE** 427 428 Defines the base address in secure memory where BL2 loads the BL32 binary 429 image. Must be aligned on a page-size boundary. 430 431- **#define : BL32\_LIMIT** 432 433 Defines the maximum address that the BL32 image can occupy. 434 435If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 436platform, the following constants must also be defined: 437 438- **#define : TSP\_SEC\_MEM\_BASE** 439 440 Defines the base address of the secure memory used by the TSP image on the 441 platform. This must be at the same address or below ``BL32_BASE``. 442 443- **#define : TSP\_SEC\_MEM\_SIZE** 444 445 Defines the size of the secure memory used by the BL32 image on the 446 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate 447 the memory required by the BL32 image, defined by ``BL32_BASE`` and 448 ``BL32_LIMIT``. 449 450- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER** 451 452 Defines the ID of the secure physical generic timer interrupt used by the 453 TSP's interrupt handling code. 454 455If the platform port uses the translation table library code, the following 456constants must also be defined: 457 458- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC** 459 460 Optional flag that can be set per-image to enable the dynamic allocation of 461 regions even when the MMU is enabled. If not defined, only static 462 functionality will be available, if defined and set to 1 it will also 463 include the dynamic functionality. 464 465- **#define : MAX\_XLAT\_TABLES** 466 467 Defines the maximum number of translation tables that are allocated by the 468 translation table library code. To minimize the amount of runtime memory 469 used, choose the smallest value needed to map the required virtual addresses 470 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 471 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 472 as well. 473 474- **#define : MAX\_MMAP\_REGIONS** 475 476 Defines the maximum number of regions that are allocated by the translation 477 table library code. A region consists of physical base address, virtual base 478 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 479 defined in the ``mmap_region_t`` structure. The platform defines the regions 480 that should be mapped. Then, the translation table library will create the 481 corresponding tables and descriptors at runtime. To minimize the amount of 482 runtime memory used, choose the smallest value needed to register the 483 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 484 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 485 the dynamic regions as well. 486 487- **#define : ADDR\_SPACE\_SIZE** 488 489 Defines the total size of the address space in bytes. For example, for a 32 490 bit address space, this value should be ``(1ULL << 32)``. This definition is 491 now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and 492 ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead. 493 494- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE** 495 496 Defines the total size of the virtual address space in bytes. For example, 497 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 498 499- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE** 500 501 Defines the total size of the physical address space in bytes. For example, 502 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 503 504If the platform port uses the IO storage framework, the following constants 505must also be defined: 506 507- **#define : MAX\_IO\_DEVICES** 508 509 Defines the maximum number of registered IO devices. Attempting to register 510 more devices than this value using ``io_register_device()`` will fail with 511 -ENOMEM. 512 513- **#define : MAX\_IO\_HANDLES** 514 515 Defines the maximum number of open IO handles. Attempting to open more IO 516 entities than this value using ``io_open()`` will fail with -ENOMEM. 517 518- **#define : MAX\_IO\_BLOCK\_DEVICES** 519 520 Defines the maximum number of registered IO block devices. Attempting to 521 register more devices this value using ``io_dev_open()`` will fail 522 with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES. 523 With this macro, multiple block devices could be supported at the same 524 time. 525 526If the platform needs to allocate data within the per-cpu data framework in 527BL31, it should define the following macro. Currently this is only required if 528the platform decides not to use the coherent memory section by undefining the 529``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 530required memory within the the per-cpu data to minimize wastage. 531 532- **#define : PLAT\_PCPU\_DATA\_SIZE** 533 534 Defines the memory (in bytes) to be reserved within the per-cpu data 535 structure for use by the platform layer. 536 537The following constants are optional. They should be defined when the platform 538memory layout implies some image overlaying like in Arm standard platforms. 539 540- **#define : BL31\_PROGBITS\_LIMIT** 541 542 Defines the maximum address in secure RAM that the BL31's progbits sections 543 can occupy. 544 545- **#define : TSP\_PROGBITS\_LIMIT** 546 547 Defines the maximum address that the TSP's progbits sections can occupy. 548 549If the platform port uses the PL061 GPIO driver, the following constant may 550optionally be defined: 551 552- **PLAT\_PL061\_MAX\_GPIOS** 553 Maximum number of GPIOs required by the platform. This allows control how 554 much memory is allocated for PL061 GPIO controllers. The default value is 555 556 #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS)) 557 558If the platform port uses the partition driver, the following constant may 559optionally be defined: 560 561- **PLAT\_PARTITION\_MAX\_ENTRIES** 562 Maximum number of partition entries required by the platform. This allows 563 control how much memory is allocated for partition entries. The default 564 value is 128. 565 `For example, define the build flag in platform.mk`_: 566 PLAT\_PARTITION\_MAX\_ENTRIES := 12 567 $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES)) 568 569The following constant is optional. It should be defined to override the default 570behaviour of the ``assert()`` function (for example, to save memory). 571 572- **PLAT\_LOG\_LEVEL\_ASSERT** 573 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 574 ``assert()`` prints the name of the file, the line number and the asserted 575 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 576 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 577 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 578 defined, it defaults to ``LOG_LEVEL``. 579 580If the platform port uses the Activity Monitor Unit, the following constants 581may be defined: 582 583- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK** 584 This mask reflects the set of group counters that should be enabled. The 585 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 586 can be at most 0xffff. If the platform does not define this mask, no group 1 587 counters are enabled. If the platform defines this mask, the following 588 constant needs to also be defined. 589 590- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS** 591 This value is used to allocate an array to save and restore the counters 592 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 593 This value should be equal to the highest bit position set in the 594 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 595 596File : plat\_macros.S [mandatory] 597~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 598 599Each platform must ensure a file of this name is in the system include path with 600the following macro defined. In the Arm development platforms, this file is 601found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 602 603- **Macro : plat\_crash\_print\_regs** 604 605 This macro allows the crash reporting routine to print relevant platform 606 registers in case of an unhandled exception in BL31. This aids in debugging 607 and this macro can be defined to be empty in case register reporting is not 608 desired. 609 610 For instance, GIC or interconnect registers may be helpful for 611 troubleshooting. 612 613Handling Reset 614-------------- 615 616BL1 by default implements the reset vector where execution starts from a cold 617or warm boot. BL31 can be optionally set as a reset vector using the 618``RESET_TO_BL31`` make variable. 619 620For each CPU, the reset vector code is responsible for the following tasks: 621 622#. Distinguishing between a cold boot and a warm boot. 623 624#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 625 the CPU is placed in a platform-specific state until the primary CPU 626 performs the necessary steps to remove it from this state. 627 628#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 629 specific address in the BL31 image in the same processor mode as it was 630 when released from reset. 631 632The following functions need to be implemented by the platform port to enable 633reset vector code to perform the above tasks. 634 635Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0] 636~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 637 638:: 639 640 Argument : void 641 Return : uintptr_t 642 643This function is called with the MMU and caches disabled 644(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 645distinguishing between a warm and cold reset for the current CPU using 646platform-specific means. If it's a warm reset, then it returns the warm 647reset entrypoint point provided to ``plat_setup_psci_ops()`` during 648BL31 initialization. If it's a cold reset then this function must return zero. 649 650This function does not follow the Procedure Call Standard used by the 651Application Binary Interface for the Arm 64-bit architecture. The caller should 652not assume that callee saved registers are preserved across a call to this 653function. 654 655This function fulfills requirement 1 and 3 listed above. 656 657Note that for platforms that support programming the reset address, it is 658expected that a CPU will start executing code directly at the right address, 659both on a cold and warm reset. In this case, there is no need to identify the 660type of reset nor to query the warm reset entrypoint. Therefore, implementing 661this function is not required on such platforms. 662 663Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 664~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 665 666:: 667 668 Argument : void 669 670This function is called with the MMU and data caches disabled. It is responsible 671for placing the executing secondary CPU in a platform-specific state until the 672primary CPU performs the necessary actions to bring it out of that state and 673allow entry into the OS. This function must not return. 674 675In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 676itself off. The primary CPU is responsible for powering up the secondary CPUs 677when normal world software requires them. When booting an EL3 payload instead, 678they stay powered on and are put in a holding pen until their mailbox gets 679populated. 680 681This function fulfills requirement 2 above. 682 683Note that for platforms that can't release secondary CPUs out of reset, only the 684primary CPU will execute the cold boot code. Therefore, implementing this 685function is not required on such platforms. 686 687Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 689 690:: 691 692 Argument : void 693 Return : unsigned int 694 695This function identifies whether the current CPU is the primary CPU or a 696secondary CPU. A return value of zero indicates that the CPU is not the 697primary CPU, while a non-zero return value indicates that the CPU is the 698primary CPU. 699 700Note that for platforms that can't release secondary CPUs out of reset, only the 701primary CPU will execute the cold boot code. Therefore, there is no need to 702distinguish between primary and secondary CPUs and implementing this function is 703not required. 704 705Function : platform\_mem\_init() [mandatory] 706~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 707 708:: 709 710 Argument : void 711 Return : void 712 713This function is called before any access to data is made by the firmware, in 714order to carry out any essential memory initialization. 715 716Function: plat\_get\_rotpk\_info() 717~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 718 719:: 720 721 Argument : void *, void **, unsigned int *, unsigned int * 722 Return : int 723 724This function is mandatory when Trusted Board Boot is enabled. It returns a 725pointer to the ROTPK stored in the platform (or a hash of it) and its length. 726The ROTPK must be encoded in DER format according to the following ASN.1 727structure: 728 729:: 730 731 AlgorithmIdentifier ::= SEQUENCE { 732 algorithm OBJECT IDENTIFIER, 733 parameters ANY DEFINED BY algorithm OPTIONAL 734 } 735 736 SubjectPublicKeyInfo ::= SEQUENCE { 737 algorithm AlgorithmIdentifier, 738 subjectPublicKey BIT STRING 739 } 740 741In case the function returns a hash of the key: 742 743:: 744 745 DigestInfo ::= SEQUENCE { 746 digestAlgorithm AlgorithmIdentifier, 747 digest OCTET STRING 748 } 749 750The function returns 0 on success. Any other value is treated as error by the 751Trusted Board Boot. The function also reports extra information related 752to the ROTPK in the flags parameter: 753 754:: 755 756 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 757 hash. 758 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 759 verification while the platform ROTPK is not deployed. 760 When this flag is set, the function does not need to 761 return a platform ROTPK, and the authentication 762 framework uses the ROTPK in the certificate without 763 verifying it against the platform value. This flag 764 must not be used in a deployed production environment. 765 766Function: plat\_get\_nv\_ctr() 767~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 768 769:: 770 771 Argument : void *, unsigned int * 772 Return : int 773 774This function is mandatory when Trusted Board Boot is enabled. It returns the 775non-volatile counter value stored in the platform in the second argument. The 776cookie in the first argument may be used to select the counter in case the 777platform provides more than one (for example, on platforms that use the default 778TBBR CoT, the cookie will correspond to the OID values defined in 779TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID). 780 781The function returns 0 on success. Any other value means the counter value could 782not be retrieved from the platform. 783 784Function: plat\_set\_nv\_ctr() 785~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 786 787:: 788 789 Argument : void *, unsigned int 790 Return : int 791 792This function is mandatory when Trusted Board Boot is enabled. It sets a new 793counter value in the platform. The cookie in the first argument may be used to 794select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is 795the updated counter value to be written to the NV counter. 796 797The function returns 0 on success. Any other value means the counter value could 798not be updated. 799 800Function: plat\_set\_nv\_ctr2() 801~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 802 803:: 804 805 Argument : void *, const auth_img_desc_t *, unsigned int 806 Return : int 807 808This function is optional when Trusted Board Boot is enabled. If this 809interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 810first argument passed is a cookie and is typically used to 811differentiate between a Non Trusted NV Counter and a Trusted NV 812Counter. The second argument is a pointer to an authentication image 813descriptor and may be used to decide if the counter is allowed to be 814updated or not. The third argument is the updated counter value to 815be written to the NV counter. 816 817The function returns 0 on success. Any other value means the counter value 818either could not be updated or the authentication image descriptor indicates 819that it is not allowed to be updated. 820 821Common mandatory function modifications 822--------------------------------------- 823 824The following functions are mandatory functions which need to be implemented 825by the platform port. 826 827Function : plat\_my\_core\_pos() 828~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 829 830:: 831 832 Argument : void 833 Return : unsigned int 834 835This funtion returns the index of the calling CPU which is used as a 836CPU-specific linear index into blocks of memory (for example while allocating 837per-CPU stacks). This function will be invoked very early in the 838initialization sequence which mandates that this function should be 839implemented in assembly and should not rely on the avalability of a C 840runtime environment. This function can clobber x0 - x8 and must preserve 841x9 - x29. 842 843This function plays a crucial role in the power domain topology framework in 844PSCI and details of this can be found in `Power Domain Topology Design`_. 845 846Function : plat\_core\_pos\_by\_mpidr() 847~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 848 849:: 850 851 Argument : u_register_t 852 Return : int 853 854This function validates the ``MPIDR`` of a CPU and converts it to an index, 855which can be used as a CPU-specific linear index into blocks of memory. In 856case the ``MPIDR`` is invalid, this function returns -1. This function will only 857be invoked by BL31 after the power domain topology is initialized and can 858utilize the C runtime environment. For further details about how TF-A 859represents the power domain topology and how this relates to the linear CPU 860index, please refer `Power Domain Topology Design`_. 861 862Common optional modifications 863----------------------------- 864 865The following are helper functions implemented by the firmware that perform 866common platform-specific tasks. A platform may choose to override these 867definitions. 868 869Function : plat\_set\_my\_stack() 870~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 871 872:: 873 874 Argument : void 875 Return : void 876 877This function sets the current stack pointer to the normal memory stack that 878has been allocated for the current CPU. For BL images that only require a 879stack for the primary CPU, the UP version of the function is used. The size 880of the stack allocated to each CPU is specified by the platform defined 881constant ``PLATFORM_STACK_SIZE``. 882 883Common implementations of this function for the UP and MP BL images are 884provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 885`plat/common/aarch64/platform\_mp\_stack.S`_ 886 887Function : plat\_get\_my\_stack() 888~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 889 890:: 891 892 Argument : void 893 Return : uintptr_t 894 895This function returns the base address of the normal memory stack that 896has been allocated for the current CPU. For BL images that only require a 897stack for the primary CPU, the UP version of the function is used. The size 898of the stack allocated to each CPU is specified by the platform defined 899constant ``PLATFORM_STACK_SIZE``. 900 901Common implementations of this function for the UP and MP BL images are 902provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 903`plat/common/aarch64/platform\_mp\_stack.S`_ 904 905Function : plat\_report\_exception() 906~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 907 908:: 909 910 Argument : unsigned int 911 Return : void 912 913A platform may need to report various information about its status when an 914exception is taken, for example the current exception level, the CPU security 915state (secure/non-secure), the exception type, and so on. This function is 916called in the following circumstances: 917 918- In BL1, whenever an exception is taken. 919- In BL2, whenever an exception is taken. 920 921The default implementation doesn't do anything, to avoid making assumptions 922about the way the platform displays its status information. 923 924For AArch64, this function receives the exception type as its argument. 925Possible values for exceptions types are listed in the 926`include/common/bl\_common.h`_ header file. Note that these constants are not 927related to any architectural exception code; they are just a TF-A convention. 928 929For AArch32, this function receives the exception mode as its argument. 930Possible values for exception modes are listed in the 931`include/lib/aarch32/arch.h`_ header file. 932 933Function : plat\_reset\_handler() 934~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 935 936:: 937 938 Argument : void 939 Return : void 940 941A platform may need to do additional initialization after reset. This function 942allows the platform to do the platform specific intializations. Platform 943specific errata workarounds could also be implemented here. The api should 944preserve the values of callee saved registers x19 to x29. 945 946The default implementation doesn't do anything. If a platform needs to override 947the default implementation, refer to the `Firmware Design`_ for general 948guidelines. 949 950Function : plat\_disable\_acp() 951~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 952 953:: 954 955 Argument : void 956 Return : void 957 958This API allows a platform to disable the Accelerator Coherency Port (if 959present) during a cluster power down sequence. The default weak implementation 960doesn't do anything. Since this API is called during the power down sequence, 961it has restrictions for stack usage and it can use the registers x0 - x17 as 962scratch registers. It should preserve the value in x18 register as it is used 963by the caller to store the return address. 964 965Function : plat\_error\_handler() 966~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 967 968:: 969 970 Argument : int 971 Return : void 972 973This API is called when the generic code encounters an error situation from 974which it cannot continue. It allows the platform to perform error reporting or 975recovery actions (for example, reset the system). This function must not return. 976 977The parameter indicates the type of error using standard codes from ``errno.h``. 978Possible errors reported by the generic code are: 979 980- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 981 Board Boot is enabled) 982- ``-ENOENT``: the requested image or certificate could not be found or an IO 983 error was detected 984- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 985 error is usually an indication of an incorrect array size 986 987The default implementation simply spins. 988 989Function : plat\_panic\_handler() 990~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 991 992:: 993 994 Argument : void 995 Return : void 996 997This API is called when the generic code encounters an unexpected error 998situation from which it cannot recover. This function must not return, 999and must be implemented in assembly because it may be called before the C 1000environment is initialized. 1001 1002Note: The address from where it was called is stored in x30 (Link Register). 1003The default implementation simply spins. 1004 1005Function : plat\_get\_bl\_image\_load\_info() 1006~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1007 1008:: 1009 1010 Argument : void 1011 Return : bl_load_info_t * 1012 1013This function returns pointer to the list of images that the platform has 1014populated to load. This function is currently invoked in BL2 to load the 1015BL3xx images, when LOAD\_IMAGE\_V2 is enabled. 1016 1017Function : plat\_get\_next\_bl\_params() 1018~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1019 1020:: 1021 1022 Argument : void 1023 Return : bl_params_t * 1024 1025This function returns a pointer to the shared memory that the platform has 1026kept aside to pass TF-A related information that next BL image needs. This 1027function is currently invoked in BL2 to pass this information to the next BL 1028image, when LOAD\_IMAGE\_V2 is enabled. 1029 1030Function : plat\_get\_stack\_protector\_canary() 1031~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1032 1033:: 1034 1035 Argument : void 1036 Return : u_register_t 1037 1038This function returns a random value that is used to initialize the canary used 1039when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable 1040value will weaken the protection as the attacker could easily write the right 1041value as part of the attack most of the time. Therefore, it should return a 1042true random number. 1043 1044Note: For the protection to be effective, the global data need to be placed at 1045a lower address than the stack bases. Failure to do so would allow an attacker 1046to overwrite the canary as part of the stack buffer overflow attack. 1047 1048Function : plat\_flush\_next\_bl\_params() 1049~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1050 1051:: 1052 1053 Argument : void 1054 Return : void 1055 1056This function flushes to main memory all the image params that are passed to 1057next image. This function is currently invoked in BL2 to flush this information 1058to the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1059 1060Function : plat\_log\_get\_prefix() 1061~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1062 1063:: 1064 1065 Argument : unsigned int 1066 Return : const char * 1067 1068This function defines the prefix string corresponding to the `log_level` to be 1069prepended to all the log output from TF-A. The `log_level` (argument) will 1070correspond to one of the standard log levels defined in debug.h. The platform 1071can override the common implementation to define a different prefix string for 1072the log output. The implementation should be robust to future changes that 1073increase the number of log levels. 1074 1075Function : plat\_get\_mbedtls\_heap() 1076~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1077 1078:: 1079 1080 Arguments : void **heap_addr, size_t *heap_size 1081 Return : int 1082 1083This function is invoked during Mbed TLS library initialisation to get 1084a heap, by means of a starting address and a size. This heap will then be used 1085internally by the Mbed TLS library. The heap is requested from the current BL 1086stage, i.e. the current BL image inside which Mbed TLS is used. 1087 1088In the default implementation a heap is statically allocated inside every image 1089(i.e. every BL stage) that utilises Mbed TLS. So, in this case, the function 1090simply returns the address and size of this "pre-allocated" heap. However, by 1091overriding the default implementation, platforms have the potential to optimise 1092memory usage. For example, on some Arm platforms, the Mbed TLS heap is shared 1093between BL1 and BL2 stages and, thus, the necessary space is not reserved 1094twice. 1095 1096On success the function should return 0 and a negative error code otherwise. 1097 1098Modifications specific to a Boot Loader stage 1099--------------------------------------------- 1100 1101Boot Loader Stage 1 (BL1) 1102------------------------- 1103 1104BL1 implements the reset vector where execution starts from after a cold or 1105warm boot. For each CPU, BL1 is responsible for the following tasks: 1106 1107#. Handling the reset as described in section 2.2 1108 1109#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1110 only this CPU executes the remaining BL1 code, including loading and passing 1111 control to the BL2 stage. 1112 1113#. Identifying and starting the Firmware Update process (if required). 1114 1115#. Loading the BL2 image from non-volatile storage into secure memory at the 1116 address specified by the platform defined constant ``BL2_BASE``. 1117 1118#. Populating a ``meminfo`` structure with the following information in memory, 1119 accessible by BL2 immediately upon entry. 1120 1121 :: 1122 1123 meminfo.total_base = Base address of secure RAM visible to BL2 1124 meminfo.total_size = Size of secure RAM visible to BL2 1125 meminfo.free_base = Base address of secure RAM available for 1126 allocation to BL2 1127 meminfo.free_size = Size of secure RAM available for allocation to BL2 1128 1129 By default, BL1 places this ``meminfo`` structure at the beginning of the 1130 free memory available for its use. Since BL1 cannot allocate memory 1131 dynamically at the moment, its free memory will be available for BL2's use 1132 as-is. However, this means that BL2 must read the ``meminfo`` structure 1133 before it starts using its free memory (this is discussed in Section 3.2). 1134 1135 It is possible for the platform to decide where it wants to place the 1136 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1137 BL2 by overriding the weak default implementation of 1138 ``bl1_plat_handle_post_image_load`` API. 1139 1140The following functions need to be implemented by the platform port to enable 1141BL1 to perform the above tasks. 1142 1143Function : bl1\_early\_platform\_setup() [mandatory] 1144~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1145 1146:: 1147 1148 Argument : void 1149 Return : void 1150 1151This function executes with the MMU and data caches disabled. It is only called 1152by the primary CPU. 1153 1154On Arm standard platforms, this function: 1155 1156- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1157 1158- Initializes a UART (PL011 console), which enables access to the ``printf`` 1159 family of functions in BL1. 1160 1161- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1162 the CCI slave interface corresponding to the cluster that includes the 1163 primary CPU. 1164 1165Function : bl1\_plat\_arch\_setup() [mandatory] 1166~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1167 1168:: 1169 1170 Argument : void 1171 Return : void 1172 1173This function performs any platform-specific and architectural setup that the 1174platform requires. Platform-specific setup might include configuration of 1175memory controllers and the interconnect. 1176 1177In Arm standard platforms, this function enables the MMU. 1178 1179This function helps fulfill requirement 2 above. 1180 1181Function : bl1\_platform\_setup() [mandatory] 1182~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1183 1184:: 1185 1186 Argument : void 1187 Return : void 1188 1189This function executes with the MMU and data caches enabled. It is responsible 1190for performing any remaining platform-specific setup that can occur after the 1191MMU and data cache have been enabled. 1192 1193if support for multiple boot sources is required, it initializes the boot 1194sequence used by plat\_try\_next\_boot\_source(). 1195 1196In Arm standard platforms, this function initializes the storage abstraction 1197layer used to load the next bootloader image. 1198 1199This function helps fulfill requirement 4 above. 1200 1201Function : bl1\_plat\_sec\_mem\_layout() [mandatory] 1202~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1203 1204:: 1205 1206 Argument : void 1207 Return : meminfo * 1208 1209This function should only be called on the cold boot path. It executes with the 1210MMU and data caches enabled. The pointer returned by this function must point to 1211a ``meminfo`` structure containing the extents and availability of secure RAM for 1212the BL1 stage. 1213 1214:: 1215 1216 meminfo.total_base = Base address of secure RAM visible to BL1 1217 meminfo.total_size = Size of secure RAM visible to BL1 1218 meminfo.free_base = Base address of secure RAM available for allocation 1219 to BL1 1220 meminfo.free_size = Size of secure RAM available for allocation to BL1 1221 1222This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1223populates a similar structure to tell BL2 the extents of memory available for 1224its own use. 1225 1226This function helps fulfill requirements 4 and 5 above. 1227 1228Function : bl1\_plat\_prepare\_exit() [optional] 1229~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1230 1231:: 1232 1233 Argument : entry_point_info_t * 1234 Return : void 1235 1236This function is called prior to exiting BL1 in response to the 1237``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1238platform specific clean up or bookkeeping operations before transferring 1239control to the next image. It receives the address of the ``entry_point_info_t`` 1240structure passed from BL2. This function runs with MMU disabled. 1241 1242Function : bl1\_plat\_set\_ep\_info() [optional] 1243~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1244 1245:: 1246 1247 Argument : unsigned int image_id, entry_point_info_t *ep_info 1248 Return : void 1249 1250This function allows platforms to override ``ep_info`` for the given ``image_id``. 1251 1252The default implementation just returns. 1253 1254Function : bl1\_plat\_get\_next\_image\_id() [optional] 1255~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1256 1257:: 1258 1259 Argument : void 1260 Return : unsigned int 1261 1262This and the following function must be overridden to enable the FWU feature. 1263 1264BL1 calls this function after platform setup to identify the next image to be 1265loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1266with the normal boot sequence, which loads and executes BL2. If the platform 1267returns a different image id, BL1 assumes that Firmware Update is required. 1268 1269The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1270platforms override this function to detect if firmware update is required, and 1271if so, return the first image in the firmware update process. 1272 1273Function : bl1\_plat\_get\_image\_desc() [optional] 1274~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1275 1276:: 1277 1278 Argument : unsigned int image_id 1279 Return : image_desc_t * 1280 1281BL1 calls this function to get the image descriptor information ``image_desc_t`` 1282for the provided ``image_id`` from the platform. 1283 1284The default implementation always returns a common BL2 image descriptor. Arm 1285standard platforms return an image descriptor corresponding to BL2 or one of 1286the firmware update images defined in the Trusted Board Boot Requirements 1287specification. 1288 1289Function : bl1\_plat\_handle\_pre\_image\_load() [optional] 1290~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1291 1292:: 1293 1294 Argument : unsigned int image_id 1295 Return : int 1296 1297This function can be used by the platforms to update/use image information 1298corresponding to ``image_id``. This function is invoked in BL1, both in cold 1299boot and FWU code path, before loading the image. 1300 1301Function : bl1\_plat\_handle\_post\_image\_load() [optional] 1302~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1303 1304:: 1305 1306 Argument : unsigned int image_id 1307 Return : int 1308 1309This function can be used by the platforms to update/use image information 1310corresponding to ``image_id``. This function is invoked in BL1, both in cold 1311boot and FWU code path, after loading and authenticating the image. 1312 1313The default weak implementation of this function calculates the amount of 1314Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1315structure at the beginning of this free memory and populates it. The address 1316of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1317information to BL2. 1318 1319Function : bl1\_plat\_fwu\_done() [optional] 1320~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1321 1322:: 1323 1324 Argument : unsigned int image_id, uintptr_t image_src, 1325 unsigned int image_size 1326 Return : void 1327 1328BL1 calls this function when the FWU process is complete. It must not return. 1329The platform may override this function to take platform specific action, for 1330example to initiate the normal boot flow. 1331 1332The default implementation spins forever. 1333 1334Function : bl1\_plat\_mem\_check() [mandatory] 1335~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1336 1337:: 1338 1339 Argument : uintptr_t mem_base, unsigned int mem_size, 1340 unsigned int flags 1341 Return : int 1342 1343BL1 calls this function while handling FWU related SMCs, more specifically when 1344copying or authenticating an image. Its responsibility is to ensure that the 1345region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1346that this memory corresponds to either a secure or non-secure memory region as 1347indicated by the security state of the ``flags`` argument. 1348 1349This function can safely assume that the value resulting from the addition of 1350``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1351overflow. 1352 1353This function must return 0 on success, a non-null error code otherwise. 1354 1355The default implementation of this function asserts therefore platforms must 1356override it when using the FWU feature. 1357 1358Boot Loader Stage 2 (BL2) 1359------------------------- 1360 1361The BL2 stage is executed only by the primary CPU, which is determined in BL1 1362using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1363``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for: 1364 1365#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform 1366 provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of 1367 the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function. 1368 The platform also defines the address in memory where SCP\_BL2 is loaded 1369 through the optional constant ``SCP_BL2_BASE``. BL2 uses this information 1370 to determine if there is enough memory to load the SCP\_BL2 image. 1371 Subsequent handling of the SCP\_BL2 image is platform-specific and is 1372 implemented in the ``bl2_plat_handle_scp_bl2()`` function. 1373 If ``SCP_BL2_BASE`` is not defined then this step is not performed. 1374 1375#. Loading the BL31 binary image into secure RAM from non-volatile storage. To 1376 load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it 1377 by BL1. This structure allows BL2 to calculate how much secure RAM is 1378 available for its use. The platform also defines the address in secure RAM 1379 where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this 1380 information to determine if there is enough memory to load the BL31 image. 1381 1382#. (Optional) Loading the BL32 binary image (if present) from platform 1383 provided non-volatile storage. To load the BL32 image, BL2 makes use of 1384 the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function. 1385 The platform also defines the address in memory where BL32 is loaded 1386 through the optional constant ``BL32_BASE``. BL2 uses this information 1387 to determine if there is enough memory to load the BL32 image. 1388 If ``BL32_BASE`` is not defined then this and the next step is not performed. 1389 1390#. (Optional) Arranging to pass control to the BL32 image (if present) that 1391 has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info`` 1392 structure in memory provided by the platform with information about how 1393 BL31 should pass control to the BL32 image. 1394 1395#. (Optional) Loading the normal world BL33 binary image (if not loaded by 1396 other means) into non-secure DRAM from platform storage and arranging for 1397 BL31 to pass control to this image. This address is determined using the 1398 ``plat_get_ns_image_entrypoint()`` function described below. 1399 1400#. BL2 populates an ``entry_point_info`` structure in memory provided by the 1401 platform with information about how BL31 should pass control to the 1402 other BL images. 1403 1404The following functions must be implemented by the platform port to enable BL2 1405to perform the above tasks. 1406 1407Function : bl2\_early\_platform\_setup() [mandatory] 1408~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1409 1410:: 1411 1412 Argument : meminfo * 1413 Return : void 1414 1415This function executes with the MMU and data caches disabled. It is only called 1416by the primary CPU. The arguments to this function is the address of the 1417``meminfo`` structure populated by BL1. 1418 1419The platform may copy the contents of the ``meminfo`` structure into a private 1420variable as the original memory may be subsequently overwritten by BL2. The 1421copied structure is made available to all BL2 code through the 1422``bl2_plat_sec_mem_layout()`` function. 1423 1424On Arm standard platforms, this function also: 1425 1426- Initializes a UART (PL011 console), which enables access to the ``printf`` 1427 family of functions in BL2. 1428 1429- Initializes the storage abstraction layer used to load further bootloader 1430 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1431 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1432 1433Function : bl2\_plat\_arch\_setup() [mandatory] 1434~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1435 1436:: 1437 1438 Argument : void 1439 Return : void 1440 1441This function executes with the MMU and data caches disabled. It is only called 1442by the primary CPU. 1443 1444The purpose of this function is to perform any architectural initialization 1445that varies across platforms. 1446 1447On Arm standard platforms, this function enables the MMU. 1448 1449Function : bl2\_platform\_setup() [mandatory] 1450~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1451 1452:: 1453 1454 Argument : void 1455 Return : void 1456 1457This function may execute with the MMU and data caches enabled if the platform 1458port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1459called by the primary CPU. 1460 1461The purpose of this function is to perform any platform initialization 1462specific to BL2. 1463 1464In Arm standard platforms, this function performs security setup, including 1465configuration of the TrustZone controller to allow non-secure masters access 1466to most of DRAM. Part of DRAM is reserved for secure world use. 1467 1468Function : bl2\_plat\_sec\_mem\_layout() [mandatory] 1469~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1470 1471:: 1472 1473 Argument : void 1474 Return : meminfo * 1475 1476This function should only be called on the cold boot path. It may execute with 1477the MMU and data caches enabled if the platform port does the necessary 1478initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU. 1479 1480The purpose of this function is to return a pointer to a ``meminfo`` structure 1481populated with the extents of secure RAM available for BL2 to use. See 1482``bl2_early_platform_setup()`` above. 1483 1484Following functions are optionally used only when LOAD\_IMAGE\_V2 is enabled. 1485 1486Function : bl2\_plat\_handle\_pre\_image\_load() [optional] 1487~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1488 1489:: 1490 1491 Argument : unsigned int 1492 Return : int 1493 1494This function can be used by the platforms to update/use image information 1495for given ``image_id``. This function is currently invoked in BL2 before 1496loading each image, when LOAD\_IMAGE\_V2 is enabled. 1497 1498Function : bl2\_plat\_handle\_post\_image\_load() [optional] 1499~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1500 1501:: 1502 1503 Argument : unsigned int 1504 Return : int 1505 1506This function can be used by the platforms to update/use image information 1507for given ``image_id``. This function is currently invoked in BL2 after 1508loading each image, when LOAD\_IMAGE\_V2 is enabled. 1509 1510Following functions are required only when LOAD\_IMAGE\_V2 is disabled. 1511 1512Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory] 1513~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1514 1515:: 1516 1517 Argument : meminfo * 1518 Return : void 1519 1520This function is used to get the memory limits where BL2 can load the 1521SCP\_BL2 image. The meminfo provided by this is used by load\_image() to 1522validate whether the SCP\_BL2 image can be loaded within the given 1523memory from the given base. 1524 1525Function : bl2\_plat\_handle\_scp\_bl2() [mandatory] 1526~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1527 1528:: 1529 1530 Argument : image_info * 1531 Return : int 1532 1533This function is called after loading SCP\_BL2 image and it is used to perform 1534any platform-specific actions required to handle the SCP firmware. Typically it 1535transfers the image into SCP memory using a platform-specific protocol and waits 1536until SCP executes it and signals to the Application Processor (AP) for BL2 1537execution to continue. 1538 1539This function returns 0 on success, a negative error code otherwise. 1540 1541Function : bl2\_plat\_get\_bl31\_params() [mandatory] 1542~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1543 1544:: 1545 1546 Argument : void 1547 Return : bl31_params * 1548 1549BL2 platform code needs to return a pointer to a ``bl31_params`` structure it 1550will use for passing information to BL31. The ``bl31_params`` structure carries 1551the following information. 1552- Header describing the version information for interpreting the bl31\_param 1553structure 1554- Information about executing the BL33 image in the ``bl33_ep_info`` field 1555- Information about executing the BL32 image in the ``bl32_ep_info`` field 1556- Information about the type and extents of BL31 image in the 1557``bl31_image_info`` field 1558- Information about the type and extents of BL32 image in the 1559``bl32_image_info`` field 1560- Information about the type and extents of BL33 image in the 1561``bl33_image_info`` field 1562 1563The memory pointed by this structure and its sub-structures should be 1564accessible from BL31 initialisation code. BL31 might choose to copy the 1565necessary content, or maintain the structures until BL33 is initialised. 1566 1567Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory] 1568~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1569 1570:: 1571 1572 Argument : void 1573 Return : entry_point_info * 1574 1575BL2 platform code returns a pointer which is used to populate the entry point 1576information for BL31 entry point. The location pointed by it should be 1577accessible from BL1 while processing the synchronous exception to run to BL31. 1578 1579In Arm standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem 1580structure in BL2 memory. 1581 1582Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory] 1583~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1584 1585:: 1586 1587 Argument : image_info *, entry_point_info * 1588 Return : void 1589 1590In the normal boot flow, this function is called after loading BL31 image and 1591it can be used to overwrite the entry point set by loader and also set the 1592security state and SPSR which represents the entry point system state for BL31. 1593 1594When booting an EL3 payload instead, this function is called after populating 1595its entry point address and can be used for the same purpose for the payload 1596image. It receives a null pointer as its first argument in this case. 1597 1598Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory] 1599~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1600 1601:: 1602 1603 Argument : image_info *, entry_point_info * 1604 Return : void 1605 1606This function is called after loading BL32 image and it can be used to 1607overwrite the entry point set by loader and also set the security state 1608and SPSR which represents the entry point system state for BL32. 1609 1610Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory] 1611~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1612 1613:: 1614 1615 Argument : image_info *, entry_point_info * 1616 Return : void 1617 1618This function is called after loading BL33 image and it can be used to 1619overwrite the entry point set by loader and also set the security state 1620and SPSR which represents the entry point system state for BL33. 1621 1622In the preloaded BL33 alternative boot flow, this function is called after 1623populating its entry point address. It is passed a null pointer as its first 1624argument in this case. 1625 1626Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory] 1627~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1628 1629:: 1630 1631 Argument : meminfo * 1632 Return : void 1633 1634This function is used to get the memory limits where BL2 can load the 1635BL32 image. The meminfo provided by this is used by load\_image() to 1636validate whether the BL32 image can be loaded with in the given 1637memory from the given base. 1638 1639Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory] 1640~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1641 1642:: 1643 1644 Argument : meminfo * 1645 Return : void 1646 1647This function is used to get the memory limits where BL2 can load the 1648BL33 image. The meminfo provided by this is used by load\_image() to 1649validate whether the BL33 image can be loaded with in the given 1650memory from the given base. 1651 1652This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1653build options are used. 1654 1655Function : bl2\_plat\_flush\_bl31\_params() [mandatory] 1656~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1657 1658:: 1659 1660 Argument : void 1661 Return : void 1662 1663Once BL2 has populated all the structures that needs to be read by BL1 1664and BL31 including the bl31\_params structures and its sub-structures, 1665the bl31\_ep\_info structure and any platform specific data. It flushes 1666all these data to the main memory so that it is available when we jump to 1667later Bootloader stages with MMU off 1668 1669Function : plat\_get\_ns\_image\_entrypoint() [mandatory] 1670~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1671 1672:: 1673 1674 Argument : void 1675 Return : uintptr_t 1676 1677As previously described, BL2 is responsible for arranging for control to be 1678passed to a normal world BL image through BL31. This function returns the 1679entrypoint of that image, which BL31 uses to jump to it. 1680 1681BL2 is responsible for loading the normal world BL33 image (e.g. UEFI). 1682 1683This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1684build options are used. 1685 1686Function : bl2\_plat\_preload\_setup [optional] 1687~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1688 1689:: 1690 1691 Argument : void 1692 Return : void 1693 1694This optional function performs any BL2 platform initialization 1695required before image loading, that is not done later in 1696bl2\_platform\_setup(). Specifically, if support for multiple 1697boot sources is required, it initializes the boot sequence used by 1698plat\_try\_next\_boot\_source(). 1699 1700Function : plat\_try\_next\_boot\_source() [optional] 1701~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1702 1703:: 1704 1705 Argument : void 1706 Return : int 1707 1708This optional function passes to the next boot source in the redundancy 1709sequence. 1710 1711This function moves the current boot redundancy source to the next 1712element in the boot sequence. If there are no more boot sources then it 1713must return 0, otherwise it must return 1. The default implementation 1714of this always returns 0. 1715 1716Boot Loader Stage 2 (BL2) at EL3 1717-------------------------------- 1718 1719When the platform has a non-TF-A Boot ROM it is desirable to jump 1720directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1721execute at EL3 instead of executing at EL1. Refer to the `Firmware 1722Design`_ for more information. 1723 1724All mandatory functions of BL2 must be implemented, except the functions 1725bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because 1726their work is done now by bl2\_el3\_early\_platform\_setup and 1727bl2\_el3\_plat\_arch\_setup. These functions should generally implement 1728the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined. 1729 1730 1731Function : bl2\_el3\_early\_platform\_setup() [mandatory] 1732~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1733 1734:: 1735 1736 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1737 Return : void 1738 1739This function executes with the MMU and data caches disabled. It is only called 1740by the primary CPU. This function receives four parameters which can be used 1741by the platform to pass any needed information from the Boot ROM to BL2. 1742 1743On Arm standard platforms, this function does the following: 1744 1745- Initializes a UART (PL011 console), which enables access to the ``printf`` 1746 family of functions in BL2. 1747 1748- Initializes the storage abstraction layer used to load further bootloader 1749 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1750 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1751 1752- Initializes the private variables that define the memory layout used. 1753 1754Function : bl2\_el3\_plat\_arch\_setup() [mandatory] 1755~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1756 1757:: 1758 1759 Argument : void 1760 Return : void 1761 1762This function executes with the MMU and data caches disabled. It is only called 1763by the primary CPU. 1764 1765The purpose of this function is to perform any architectural initialization 1766that varies across platforms. 1767 1768On Arm standard platforms, this function enables the MMU. 1769 1770Function : bl2\_el3\_plat\_prepare\_exit() [optional] 1771~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1772 1773:: 1774 1775 Argument : void 1776 Return : void 1777 1778This function is called prior to exiting BL2 and run the next image. 1779It should be used to perform platform specific clean up or bookkeeping 1780operations before transferring control to the next image. This function 1781runs with MMU disabled. 1782 1783FWU Boot Loader Stage 2 (BL2U) 1784------------------------------ 1785 1786The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1787process and is executed only by the primary CPU. BL1 passes control to BL2U at 1788``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1789 1790#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure 1791 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1. 1792 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U 1793 should be copied from. Subsequent handling of the SCP\_BL2U image is 1794 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1795 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1796 1797#. Any platform specific setup required to perform the FWU process. For 1798 example, Arm standard platforms initialize the TZC controller so that the 1799 normal world can access DDR memory. 1800 1801The following functions must be implemented by the platform port to enable 1802BL2U to perform the tasks mentioned above. 1803 1804Function : bl2u\_early\_platform\_setup() [mandatory] 1805~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1806 1807:: 1808 1809 Argument : meminfo *mem_info, void *plat_info 1810 Return : void 1811 1812This function executes with the MMU and data caches disabled. It is only 1813called by the primary CPU. The arguments to this function is the address 1814of the ``meminfo`` structure and platform specific info provided by BL1. 1815 1816The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1817private storage as the original memory may be subsequently overwritten by BL2U. 1818 1819On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1820to extract SCP\_BL2U image information, which is then copied into a private 1821variable. 1822 1823Function : bl2u\_plat\_arch\_setup() [mandatory] 1824~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1825 1826:: 1827 1828 Argument : void 1829 Return : void 1830 1831This function executes with the MMU and data caches disabled. It is only 1832called by the primary CPU. 1833 1834The purpose of this function is to perform any architectural initialization 1835that varies across platforms, for example enabling the MMU (since the memory 1836map differs across platforms). 1837 1838Function : bl2u\_platform\_setup() [mandatory] 1839~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1840 1841:: 1842 1843 Argument : void 1844 Return : void 1845 1846This function may execute with the MMU and data caches enabled if the platform 1847port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1848called by the primary CPU. 1849 1850The purpose of this function is to perform any platform initialization 1851specific to BL2U. 1852 1853In Arm standard platforms, this function performs security setup, including 1854configuration of the TrustZone controller to allow non-secure masters access 1855to most of DRAM. Part of DRAM is reserved for secure world use. 1856 1857Function : bl2u\_plat\_handle\_scp\_bl2u() [optional] 1858~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1859 1860:: 1861 1862 Argument : void 1863 Return : int 1864 1865This function is used to perform any platform-specific actions required to 1866handle the SCP firmware. Typically it transfers the image into SCP memory using 1867a platform-specific protocol and waits until SCP executes it and signals to the 1868Application Processor (AP) for BL2U execution to continue. 1869 1870This function returns 0 on success, a negative error code otherwise. 1871This function is included if SCP\_BL2U\_BASE is defined. 1872 1873Boot Loader Stage 3-1 (BL31) 1874---------------------------- 1875 1876During cold boot, the BL31 stage is executed only by the primary CPU. This is 1877determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1878control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1879CPUs. BL31 executes at EL3 and is responsible for: 1880 1881#. Re-initializing all architectural and platform state. Although BL1 performs 1882 some of this initialization, BL31 remains resident in EL3 and must ensure 1883 that EL3 architectural and platform state is completely initialized. It 1884 should make no assumptions about the system state when it receives control. 1885 1886#. Passing control to a normal world BL image, pre-loaded at a platform- 1887 specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2 1888 populated in memory to do this. 1889 1890#. Providing runtime firmware services. Currently, BL31 only implements a 1891 subset of the Power State Coordination Interface (PSCI) API as a runtime 1892 service. See Section 3.3 below for details of porting the PSCI 1893 implementation. 1894 1895#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1896 specific address by BL2. BL31 exports a set of apis that allow runtime 1897 services to specify the security state in which the next image should be 1898 executed and run the corresponding image. BL31 uses the ``entry_point_info`` 1899 structure populated by BL2 to do this. 1900 1901If BL31 is a reset vector, It also needs to handle the reset as specified in 1902section 2.2 before the tasks described above. 1903 1904The following functions must be implemented by the platform port to enable BL31 1905to perform the above tasks. 1906 1907Function : bl31\_early\_platform\_setup() [mandatory] 1908~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1909 1910:: 1911 1912 Argument : bl31_params *, void * 1913 Return : void 1914 1915This function executes with the MMU and data caches disabled. It is only called 1916by the primary CPU. The arguments to this function are: 1917 1918- The address of the ``bl31_params`` structure populated by BL2. 1919- An opaque pointer that the platform may use as needed. 1920 1921The platform can copy the contents of the ``bl31_params`` structure and its 1922sub-structures into private variables if the original memory may be 1923subsequently overwritten by BL31 and similarly the ``void *`` pointing 1924to the platform data also needs to be saved. 1925 1926In Arm standard platforms, BL2 passes a pointer to a ``bl31_params`` structure 1927in BL2 memory. BL31 copies the information in this pointer to internal data 1928structures. It also performs the following: 1929 1930- Initialize a UART (PL011 console), which enables access to the ``printf`` 1931 family of functions in BL31. 1932 1933- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1934 CCI slave interface corresponding to the cluster that includes the primary 1935 CPU. 1936 1937Function : bl31\_plat\_arch\_setup() [mandatory] 1938~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1939 1940:: 1941 1942 Argument : void 1943 Return : void 1944 1945This function executes with the MMU and data caches disabled. It is only called 1946by the primary CPU. 1947 1948The purpose of this function is to perform any architectural initialization 1949that varies across platforms. 1950 1951On Arm standard platforms, this function enables the MMU. 1952 1953Function : bl31\_platform\_setup() [mandatory] 1954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1955 1956:: 1957 1958 Argument : void 1959 Return : void 1960 1961This function may execute with the MMU and data caches enabled if the platform 1962port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1963called by the primary CPU. 1964 1965The purpose of this function is to complete platform initialization so that both 1966BL31 runtime services and normal world software can function correctly. 1967 1968On Arm standard platforms, this function does the following: 1969 1970- Initialize the generic interrupt controller. 1971 1972 Depending on the GIC driver selected by the platform, the appropriate GICv2 1973 or GICv3 initialization will be done, which mainly consists of: 1974 1975 - Enable secure interrupts in the GIC CPU interface. 1976 - Disable the legacy interrupt bypass mechanism. 1977 - Configure the priority mask register to allow interrupts of all priorities 1978 to be signaled to the CPU interface. 1979 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1980 - Target all secure SPIs to CPU0. 1981 - Enable these secure interrupts in the GIC distributor. 1982 - Configure all other interrupts as non-secure. 1983 - Enable signaling of secure interrupts in the GIC distributor. 1984 1985- Enable system-level implementation of the generic timer counter through the 1986 memory mapped interface. 1987 1988- Grant access to the system counter timer module 1989 1990- Initialize the power controller device. 1991 1992 In particular, initialise the locks that prevent concurrent accesses to the 1993 power controller device. 1994 1995Function : bl31\_plat\_runtime\_setup() [optional] 1996~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1997 1998:: 1999 2000 Argument : void 2001 Return : void 2002 2003The purpose of this function is allow the platform to perform any BL31 runtime 2004setup just prior to BL31 exit during cold boot. The default weak 2005implementation of this function will invoke ``console_switch_state()`` to switch 2006console output to consoles marked for use in the ``runtime`` state. 2007 2008Function : bl31\_plat\_get\_next\_image\_ep\_info() [mandatory] 2009~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2010 2011:: 2012 2013 Argument : uint32_t 2014 Return : entry_point_info * 2015 2016This function may execute with the MMU and data caches enabled if the platform 2017port does the necessary initializations in ``bl31_plat_arch_setup()``. 2018 2019This function is called by ``bl31_main()`` to retrieve information provided by 2020BL2 for the next image in the security state specified by the argument. BL31 2021uses this information to pass control to that image in the specified security 2022state. This function must return a pointer to the ``entry_point_info`` structure 2023(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2024should return NULL otherwise. 2025 2026Function : bl31_plat_enable_mmu [optional] 2027~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2028 2029:: 2030 2031 Argument : uint32_t 2032 Return : void 2033 2034This function enables the MMU. The boot code calls this function with MMU and 2035caches disabled. This function should program necessary registers to enable 2036translation, and upon return, the MMU on the calling PE must be enabled. 2037 2038The function must honor flags passed in the first argument. These flags are 2039defined by the translation library, and can be found in the file 2040``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2041 2042On DynamIQ systems, this function must not use stack while enabling MMU, which 2043is how the function in xlat table library version 2 is implementated. 2044 2045Function : plat\_get\_syscnt\_freq2() [mandatory] 2046~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2047 2048:: 2049 2050 Argument : void 2051 Return : unsigned int 2052 2053This function is used by the architecture setup code to retrieve the counter 2054frequency for the CPU's generic timer. This value will be programmed into the 2055``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2056of the system counter, which is retrieved from the first entry in the frequency 2057modes table. 2058 2059#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional] 2060~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2061 2062When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2063bytes) aligned to the cache line boundary that should be allocated per-cpu to 2064accommodate all the bakery locks. 2065 2066If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2067calculates the size of the ``bakery_lock`` input section, aligns it to the 2068nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2069and stores the result in a linker symbol. This constant prevents a platform 2070from relying on the linker and provide a more efficient mechanism for 2071accessing per-cpu bakery lock information. 2072 2073If this constant is defined and its value is not equal to the value 2074calculated by the linker then a link time assertion is raised. A compile time 2075assertion is raised if the value of the constant is not aligned to the cache 2076line boundary. 2077 2078SDEI porting requirements 2079~~~~~~~~~~~~~~~~~~~~~~~~~ 2080 2081The SDEI dispatcher requires the platform to provide the following macros 2082and functions, of which some are optional, and some others mandatory. 2083 2084Macros 2085...... 2086 2087Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2088^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2089 2090This macro must be defined to the EL3 exception priority level associated with 2091Normal SDEI events on the platform. This must have a higher value (therefore of 2092lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2093 2094Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2095^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2096 2097This macro must be defined to the EL3 exception priority level associated with 2098Critical SDEI events on the platform. This must have a lower value (therefore of 2099higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2100 2101**Note**: SDEI exception priorities must be the lowest among Secure priorities. 2102Among the SDEI exceptions, Critical SDEI priority must be higher than Normal 2103SDEI priority. 2104 2105Functions 2106......... 2107 2108Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 2109^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2110 2111:: 2112 2113 Argument: uintptr_t 2114 Return: int 2115 2116This function validates the address of client entry points provided for both 2117event registration and *Complete and Resume* SDEI calls. The function takes one 2118argument, which is the address of the handler the SDEI client requested to 2119register. The function must return ``0`` for successful validation, or ``-1`` 2120upon failure. 2121 2122The default implementation always returns ``0``. On Arm platforms, this function 2123is implemented to translate the entry point to physical address, and further to 2124ensure that the address is located in Non-secure DRAM. 2125 2126Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2127^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2128 2129:: 2130 2131 Argument: uint64_t 2132 Argument: unsigned int 2133 Return: void 2134 2135SDEI specification requires that a PE comes out of reset with the events masked. 2136The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 2137the PE. No SDEI events can be dispatched until such time. 2138 2139Should a PE receive an interrupt that was bound to an SDEI event while the 2140events are masked on the PE, the dispatcher implementation invokes the function 2141``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2142interrupt and the interrupt ID are passed as parameters. 2143 2144The default implementation only prints out a warning message. 2145 2146Power State Coordination Interface (in BL31) 2147-------------------------------------------- 2148 2149The TF-A implementation of the PSCI API is based around the concept of a 2150*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2151share some state on which power management operations can be performed as 2152specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2153a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2154*power domains* are arranged in a hierarchical tree structure and each 2155*power domain* can be identified in a system by the cpu index of any CPU that 2156is part of that domain and a *power domain level*. A processing element (for 2157example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2158logical grouping of CPUs that share some state, then level 1 is that group of 2159CPUs (for example, a cluster), and level 2 is a group of clusters (for 2160example, the system). More details on the power domain topology and its 2161organization can be found in `Power Domain Topology Design`_. 2162 2163BL31's platform initialization code exports a pointer to the platform-specific 2164power management operations required for the PSCI implementation to function 2165correctly. This information is populated in the ``plat_psci_ops`` structure. The 2166PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2167power management operations on the power domains. For example, the target 2168CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2169handler (if present) is called for the CPU power domain. 2170 2171The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2172describe composite power states specific to a platform. The PSCI implementation 2173defines a generic representation of the power-state parameter viz which is an 2174array of local power states where each index corresponds to a power domain 2175level. Each entry contains the local power state the power domain at that power 2176level could enter. It depends on the ``validate_power_state()`` handler to 2177convert the power-state parameter (possibly encoding a composite power state) 2178passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2179 2180The following functions form part of platform port of PSCI functionality. 2181 2182Function : plat\_psci\_stat\_accounting\_start() [optional] 2183~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2184 2185:: 2186 2187 Argument : const psci_power_state_t * 2188 Return : void 2189 2190This is an optional hook that platforms can implement for residency statistics 2191accounting before entering a low power state. The ``pwr_domain_state`` field of 2192``state_info`` (first argument) can be inspected if stat accounting is done 2193differently at CPU level versus higher levels. As an example, if the element at 2194index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2195state, special hardware logic may be programmed in order to keep track of the 2196residency statistics. For higher levels (array indices > 0), the residency 2197statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2198default implementation will use PMF to capture timestamps. 2199 2200Function : plat\_psci\_stat\_accounting\_stop() [optional] 2201~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2202 2203:: 2204 2205 Argument : const psci_power_state_t * 2206 Return : void 2207 2208This is an optional hook that platforms can implement for residency statistics 2209accounting after exiting from a low power state. The ``pwr_domain_state`` field 2210of ``state_info`` (first argument) can be inspected if stat accounting is done 2211differently at CPU level versus higher levels. As an example, if the element at 2212index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2213state, special hardware logic may be programmed in order to keep track of the 2214residency statistics. For higher levels (array indices > 0), the residency 2215statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2216default implementation will use PMF to capture timestamps. 2217 2218Function : plat\_psci\_stat\_get\_residency() [optional] 2219~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2220 2221:: 2222 2223 Argument : unsigned int, const psci_power_state_t *, int 2224 Return : u_register_t 2225 2226This is an optional interface that is is invoked after resuming from a low power 2227state and provides the time spent resident in that low power state by the power 2228domain at a particular power domain level. When a CPU wakes up from suspend, 2229all its parent power domain levels are also woken up. The generic PSCI code 2230invokes this function for each parent power domain that is resumed and it 2231identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2232argument) describes the low power state that the power domain has resumed from. 2233The current CPU is the first CPU in the power domain to resume from the low 2234power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2235CPU in the power domain to suspend and may be needed to calculate the residency 2236for that power domain. 2237 2238Function : plat\_get\_target\_pwr\_state() [optional] 2239~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2240 2241:: 2242 2243 Argument : unsigned int, const plat_local_state_t *, unsigned int 2244 Return : plat_local_state_t 2245 2246The PSCI generic code uses this function to let the platform participate in 2247state coordination during a power management operation. The function is passed 2248a pointer to an array of platform specific local power state ``states`` (second 2249argument) which contains the requested power state for each CPU at a particular 2250power domain level ``lvl`` (first argument) within the power domain. The function 2251is expected to traverse this array of upto ``ncpus`` (third argument) and return 2252a coordinated target power state by the comparing all the requested power 2253states. The target power state should not be deeper than any of the requested 2254power states. 2255 2256A weak definition of this API is provided by default wherein it assumes 2257that the platform assigns a local state value in order of increasing depth 2258of the power state i.e. for two power states X & Y, if X < Y 2259then X represents a shallower power state than Y. As a result, the 2260coordinated target local power state for a power domain will be the minimum 2261of the requested local power state values. 2262 2263Function : plat\_get\_power\_domain\_tree\_desc() [mandatory] 2264~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2265 2266:: 2267 2268 Argument : void 2269 Return : const unsigned char * 2270 2271This function returns a pointer to the byte array containing the power domain 2272topology tree description. The format and method to construct this array are 2273described in `Power Domain Topology Design`_. The BL31 PSCI initilization code 2274requires this array to be described by the platform, either statically or 2275dynamically, to initialize the power domain topology tree. In case the array 2276is populated dynamically, then plat\_core\_pos\_by\_mpidr() and 2277plat\_my\_core\_pos() should also be implemented suitably so that the topology 2278tree description matches the CPU indices returned by these APIs. These APIs 2279together form the platform interface for the PSCI topology framework. 2280 2281Function : plat\_setup\_psci\_ops() [mandatory] 2282~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2283 2284:: 2285 2286 Argument : uintptr_t, const plat_psci_ops ** 2287 Return : int 2288 2289This function may execute with the MMU and data caches enabled if the platform 2290port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2291called by the primary CPU. 2292 2293This function is called by PSCI initialization code. Its purpose is to let 2294the platform layer know about the warm boot entrypoint through the 2295``sec_entrypoint`` (first argument) and to export handler routines for 2296platform-specific psci power management actions by populating the passed 2297pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2298 2299A description of each member of this structure is given below. Please refer to 2300the Arm FVP specific implementation of these handlers in 2301`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the 2302platform wants to support, the associated operation or operations in this 2303structure must be provided and implemented (Refer section 4 of 2304`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI 2305function in a platform port, the operation should be removed from this 2306structure instead of providing an empty implementation. 2307 2308plat\_psci\_ops.cpu\_standby() 2309.............................. 2310 2311Perform the platform-specific actions to enter the standby state for a cpu 2312indicated by the passed argument. This provides a fast path for CPU standby 2313wherein overheads of PSCI state management and lock acquistion is avoided. 2314For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2315the suspend state type specified in the ``power-state`` parameter should be 2316STANDBY and the target power domain level specified should be the CPU. The 2317handler should put the CPU into a low power retention state (usually by 2318issuing a wfi instruction) and ensure that it can be woken up from that 2319state by a normal interrupt. The generic code expects the handler to succeed. 2320 2321plat\_psci\_ops.pwr\_domain\_on() 2322................................. 2323 2324Perform the platform specific actions to power on a CPU, specified 2325by the ``MPIDR`` (first argument). The generic code expects the platform to 2326return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure. 2327 2328plat\_psci\_ops.pwr\_domain\_off() 2329.................................. 2330 2331Perform the platform specific actions to prepare to power off the calling CPU 2332and its higher parent power domain levels as indicated by the ``target_state`` 2333(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2334 2335The ``target_state`` encodes the platform coordinated target local power states 2336for the CPU power domain and its parent power domain levels. The handler 2337needs to perform power management operation corresponding to the local state 2338at each power level. 2339 2340For this handler, the local power state for the CPU power domain will be a 2341power down state where as it could be either power down, retention or run state 2342for the higher power domain levels depending on the result of state 2343coordination. The generic code expects the handler to succeed. 2344 2345plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] 2346................................................................. 2347 2348This optional function may be used as a performance optimization to replace 2349or complement pwr_domain_suspend() on some platforms. Its calling semantics 2350are identical to pwr_domain_suspend(), except the PSCI implementation only 2351calls this function when suspending to a power down state, and it guarantees 2352that data caches are enabled. 2353 2354When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2355before calling pwr_domain_suspend(). If the target_state corresponds to a 2356power down state and it is safe to perform some or all of the platform 2357specific actions in that function with data caches enabled, it may be more 2358efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2359= 1, data caches remain enabled throughout, and so there is no advantage to 2360moving platform specific actions to this function. 2361 2362plat\_psci\_ops.pwr\_domain\_suspend() 2363...................................... 2364 2365Perform the platform specific actions to prepare to suspend the calling 2366CPU and its higher parent power domain levels as indicated by the 2367``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2368API implementation. 2369 2370The ``target_state`` has a similar meaning as described in 2371the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2372target local power states for the CPU power domain and its parent 2373power domain levels. The handler needs to perform power management operation 2374corresponding to the local state at each power level. The generic code 2375expects the handler to succeed. 2376 2377The difference between turning a power domain off versus suspending it is that 2378in the former case, the power domain is expected to re-initialize its state 2379when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2380case, the power domain is expected to save enough state so that it can resume 2381execution by restoring this state when its powered on (see 2382``pwr_domain_suspend_finish()``). 2383 2384When suspending a core, the platform can also choose to power off the GICv3 2385Redistributor and ITS through an implementation-defined sequence. To achieve 2386this safely, the ITS context must be saved first. The architectural part is 2387implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2388sequence is implementation defined and it is therefore the responsibility of 2389the platform code to implement the necessary sequence. Then the GIC 2390Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2391Powering off the Redistributor requires the implementation to support it and it 2392is the responsibility of the platform code to execute the right implementation 2393defined sequence. 2394 2395When a system suspend is requested, the platform can also make use of the 2396``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2397it has saved the context of the Redistributors and ITS of all the cores in the 2398system. The context of the Distributor can be large and may require it to be 2399allocated in a special area if it cannot fit in the platform's global static 2400data, for example in DRAM. The Distributor can then be powered down using an 2401implementation-defined sequence. 2402 2403plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi() 2404............................................. 2405 2406This is an optional function and, if implemented, is expected to perform 2407platform specific actions including the ``wfi`` invocation which allows the 2408CPU to powerdown. Since this function is invoked outside the PSCI locks, 2409the actions performed in this hook must be local to the CPU or the platform 2410must ensure that races between multiple CPUs cannot occur. 2411 2412The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2413operation and it encodes the platform coordinated target local power states for 2414the CPU power domain and its parent power domain levels. This function must 2415not return back to the caller. 2416 2417If this function is not implemented by the platform, PSCI generic 2418implementation invokes ``psci_power_down_wfi()`` for power down. 2419 2420plat\_psci\_ops.pwr\_domain\_on\_finish() 2421......................................... 2422 2423This function is called by the PSCI implementation after the calling CPU is 2424powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2425It performs the platform-specific setup required to initialize enough state for 2426this CPU to enter the normal world and also provide secure runtime firmware 2427services. 2428 2429The ``target_state`` (first argument) is the prior state of the power domains 2430immediately before the CPU was turned on. It indicates which power domains 2431above the CPU might require initialization due to having previously been in 2432low power states. The generic code expects the handler to succeed. 2433 2434plat\_psci\_ops.pwr\_domain\_suspend\_finish() 2435.............................................. 2436 2437This function is called by the PSCI implementation after the calling CPU is 2438powered on and released from reset in response to an asynchronous wakeup 2439event, for example a timer interrupt that was programmed by the CPU during the 2440``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2441setup required to restore the saved state for this CPU to resume execution 2442in the normal world and also provide secure runtime firmware services. 2443 2444The ``target_state`` (first argument) has a similar meaning as described in 2445the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2446to succeed. 2447 2448If the Distributor, Redistributors or ITS have been powered off as part of a 2449suspend, their context must be restored in this function in the reverse order 2450to how they were saved during suspend sequence. 2451 2452plat\_psci\_ops.system\_off() 2453............................. 2454 2455This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2456call. It performs the platform-specific system poweroff sequence after 2457notifying the Secure Payload Dispatcher. 2458 2459plat\_psci\_ops.system\_reset() 2460............................... 2461 2462This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2463call. It performs the platform-specific system reset sequence after 2464notifying the Secure Payload Dispatcher. 2465 2466plat\_psci\_ops.validate\_power\_state() 2467........................................ 2468 2469This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2470call to validate the ``power_state`` parameter of the PSCI API and if valid, 2471populate it in ``req_state`` (second argument) array as power domain level 2472specific local states. If the ``power_state`` is invalid, the platform must 2473return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the 2474normal world PSCI client. 2475 2476plat\_psci\_ops.validate\_ns\_entrypoint() 2477.......................................... 2478 2479This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2480``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2481parameter passed by the normal world. If the ``entry_point`` is invalid, 2482the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is 2483propagated back to the normal world PSCI client. 2484 2485plat\_psci\_ops.get\_sys\_suspend\_power\_state() 2486................................................. 2487 2488This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2489call to get the ``req_state`` parameter from platform which encodes the power 2490domain level specific local states to suspend to system affinity level. The 2491``req_state`` will be utilized to do the PSCI state coordination and 2492``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2493enter system suspend. 2494 2495plat\_psci\_ops.get\_pwr\_lvl\_state\_idx() 2496........................................... 2497 2498This is an optional function and, if implemented, is invoked by the PSCI 2499implementation to convert the ``local_state`` (first argument) at a specified 2500``pwr_lvl`` (second argument) to an index between 0 and 2501``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2502supports more than two local power states at each power domain level, that is 2503``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2504local power states. 2505 2506plat\_psci\_ops.translate\_power\_state\_by\_mpidr() 2507.................................................... 2508 2509This is an optional function and, if implemented, verifies the ``power_state`` 2510(second argument) parameter of the PSCI API corresponding to a target power 2511domain. The target power domain is identified by using both ``MPIDR`` (first 2512argument) and the power domain level encoded in ``power_state``. The power domain 2513level specific local states are to be extracted from ``power_state`` and be 2514populated in the ``output_state`` (third argument) array. The functionality 2515is similar to the ``validate_power_state`` function described above and is 2516envisaged to be used in case the validity of ``power_state`` depend on the 2517targeted power domain. If the ``power_state`` is invalid for the targeted power 2518domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this 2519function is not implemented, then the generic implementation relies on 2520``validate_power_state`` function to translate the ``power_state``. 2521 2522This function can also be used in case the platform wants to support local 2523power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY 2524APIs as described in Section 5.18 of `PSCI`_. 2525 2526plat\_psci\_ops.get\_node\_hw\_state() 2527...................................... 2528 2529This is an optional function. If implemented this function is intended to return 2530the power state of a node (identified by the first parameter, the ``MPIDR``) in 2531the power domain topology (identified by the second parameter, ``power_level``), 2532as retrieved from a power controller or equivalent component on the platform. 2533Upon successful completion, the implementation must map and return the final 2534status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2535must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2536appropriate. 2537 2538Implementations are not expected to handle ``power_levels`` greater than 2539``PLAT_MAX_PWR_LVL``. 2540 2541plat\_psci\_ops.system\_reset2() 2542................................ 2543 2544This is an optional function. If implemented this function is 2545called during the ``SYSTEM_RESET2`` call to perform a reset 2546based on the first parameter ``reset_type`` as specified in 2547`PSCI`_. The parameter ``cookie`` can be used to pass additional 2548reset information. If the ``reset_type`` is not supported, the 2549function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2550resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2551and vendor reset can return other PSCI error codes as defined 2552in `PSCI`_. On success this function will not return. 2553 2554plat\_psci\_ops.write\_mem\_protect() 2555.................................... 2556 2557This is an optional function. If implemented it enables or disables the 2558``MEM_PROTECT`` functionality based on the value of ``val``. 2559A non-zero value enables ``MEM_PROTECT`` and a value of zero 2560disables it. Upon encountering failures it must return a negative value 2561and on success it must return 0. 2562 2563plat\_psci\_ops.read\_mem\_protect() 2564..................................... 2565 2566This is an optional function. If implemented it returns the current 2567state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2568failures it must return a negative value and on success it must 2569return 0. 2570 2571plat\_psci\_ops.mem\_protect\_chk() 2572................................... 2573 2574This is an optional function. If implemented it checks if a memory 2575region defined by a base address ``base`` and with a size of ``length`` 2576bytes is protected by ``MEM_PROTECT``. If the region is protected 2577then it must return 0, otherwise it must return a negative number. 2578 2579Interrupt Management framework (in BL31) 2580---------------------------------------- 2581 2582BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2583generated in either security state and targeted to EL1 or EL2 in the non-secure 2584state or EL3/S-EL1 in the secure state. The design of this framework is 2585described in the `IMF Design Guide`_ 2586 2587A platform should export the following APIs to support the IMF. The following 2588text briefly describes each api and its implementation in Arm standard 2589platforms. The API implementation depends upon the type of interrupt controller 2590present in the platform. Arm standard platform layer supports both 2591`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2592and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2593FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2594``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in 2595`User Guide`_ for more details). 2596 2597See also: `Interrupt Controller Abstraction APIs`__. 2598 2599.. __: platform-interrupt-controller-API.rst 2600 2601Function : plat\_interrupt\_type\_to\_line() [mandatory] 2602~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2603 2604:: 2605 2606 Argument : uint32_t, uint32_t 2607 Return : uint32_t 2608 2609The Arm processor signals an interrupt exception either through the IRQ or FIQ 2610interrupt line. The specific line that is signaled depends on how the interrupt 2611controller (IC) reports different interrupt types from an execution context in 2612either security state. The IMF uses this API to determine which interrupt line 2613the platform IC uses to signal each type of interrupt supported by the framework 2614from a given security state. This API must be invoked at EL3. 2615 2616The first parameter will be one of the ``INTR_TYPE_*`` values (see 2617`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2618security state of the originating execution context. The return result is the 2619bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2620FIQ=2. 2621 2622In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2623configured as FIQs and Non-secure interrupts as IRQs from either security 2624state. 2625 2626In the case of Arm standard platforms using GICv3, the interrupt line to be 2627configured depends on the security state of the execution context when the 2628interrupt is signalled and are as follows: 2629 2630- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2631 NS-EL0/1/2 context. 2632- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2633 in the NS-EL0/1/2 context. 2634- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2635 context. 2636 2637Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory] 2638~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2639 2640:: 2641 2642 Argument : void 2643 Return : uint32_t 2644 2645This API returns the type of the highest priority pending interrupt at the 2646platform IC. The IMF uses the interrupt type to retrieve the corresponding 2647handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2648pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2649``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2650 2651In the case of Arm standard platforms using GICv2, the *Highest Priority 2652Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2653the pending interrupt. The type of interrupt depends upon the id value as 2654follows. 2655 2656#. id < 1022 is reported as a S-EL1 interrupt 2657#. id = 1022 is reported as a Non-secure interrupt. 2658#. id = 1023 is reported as an invalid interrupt type. 2659 2660In the case of Arm standard platforms using GICv3, the system register 2661``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2662is read to determine the id of the pending interrupt. The type of interrupt 2663depends upon the id value as follows. 2664 2665#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2666#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2667#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2668#. All other interrupt id's are reported as EL3 interrupt. 2669 2670Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory] 2671~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2672 2673:: 2674 2675 Argument : void 2676 Return : uint32_t 2677 2678This API returns the id of the highest priority pending interrupt at the 2679platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2680pending. 2681 2682In the case of Arm standard platforms using GICv2, the *Highest Priority 2683Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2684pending interrupt. The id that is returned by API depends upon the value of 2685the id read from the interrupt controller as follows. 2686 2687#. id < 1022. id is returned as is. 2688#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2689 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2690 This id is returned by the API. 2691#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2692 2693In the case of Arm standard platforms using GICv3, if the API is invoked from 2694EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2695group 0 Register*, is read to determine the id of the pending interrupt. The id 2696that is returned by API depends upon the value of the id read from the 2697interrupt controller as follows. 2698 2699#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2700#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2701 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2702 Register* is read to determine the id of the group 1 interrupt. This id 2703 is returned by the API as long as it is a valid interrupt id 2704#. If the id is any of the special interrupt identifiers, 2705 ``INTR_ID_UNAVAILABLE`` is returned. 2706 2707When the API invoked from S-EL1 for GICv3 systems, the id read from system 2708register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2709Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else 2710``INTR_ID_UNAVAILABLE`` is returned. 2711 2712Function : plat\_ic\_acknowledge\_interrupt() [mandatory] 2713~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2714 2715:: 2716 2717 Argument : void 2718 Return : uint32_t 2719 2720This API is used by the CPU to indicate to the platform IC that processing of 2721the highest pending interrupt has begun. It should return the raw, unmodified 2722value obtained from the interrupt controller when acknowledging an interrupt. 2723The actual interrupt number shall be extracted from this raw value using the API 2724`plat_ic_get_interrupt_id()`__. 2725 2726.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2727 2728This function in Arm standard platforms using GICv2, reads the *Interrupt 2729Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2730priority pending interrupt from pending to active in the interrupt controller. 2731It returns the value read from the ``GICC_IAR``, unmodified. 2732 2733In the case of Arm standard platforms using GICv3, if the API is invoked 2734from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2735Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2736reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2737group 1*. The read changes the state of the highest pending interrupt from 2738pending to active in the interrupt controller. The value read is returned 2739unmodified. 2740 2741The TSP uses this API to start processing of the secure physical timer 2742interrupt. 2743 2744Function : plat\_ic\_end\_of\_interrupt() [mandatory] 2745~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2746 2747:: 2748 2749 Argument : uint32_t 2750 Return : void 2751 2752This API is used by the CPU to indicate to the platform IC that processing of 2753the interrupt corresponding to the id (passed as the parameter) has 2754finished. The id should be the same as the id returned by the 2755``plat_ic_acknowledge_interrupt()`` API. 2756 2757Arm standard platforms write the id to the *End of Interrupt Register* 2758(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2759system register in case of GICv3 depending on where the API is invoked from, 2760EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2761controller. 2762 2763The TSP uses this API to finish processing of the secure physical timer 2764interrupt. 2765 2766Function : plat\_ic\_get\_interrupt\_type() [mandatory] 2767~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2768 2769:: 2770 2771 Argument : uint32_t 2772 Return : uint32_t 2773 2774This API returns the type of the interrupt id passed as the parameter. 2775``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2776interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2777returned depending upon how the interrupt has been configured by the platform 2778IC. This API must be invoked at EL3. 2779 2780Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2781and Non-secure interrupts as Group1 interrupts. It reads the group value 2782corresponding to the interrupt id from the relevant *Interrupt Group Register* 2783(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2784 2785In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2786Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2787(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2788as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2789 2790Crash Reporting mechanism (in BL31) 2791----------------------------------- 2792 2793NOTE: This section assumes that your platform is enabling the MULTI_CONSOLE_API 2794flag in its platform.mk. Not using this flag is deprecated for new platforms. 2795 2796BL31 implements a crash reporting mechanism which prints the various registers 2797of the CPU to enable quick crash analysis and debugging. By default, the 2798definitions in ``plat/common/aarch64/platform\_helpers.S`` will cause the crash 2799output to be routed over the normal console infrastructure and get printed on 2800consoles configured to output in crash state. ``console_set_scope()`` can be 2801used to control whether a console is used for crash output. 2802 2803In some cases (such as debugging very early crashes that happen before the 2804normal boot console can be set up), platforms may want to control crash output 2805more explicitly. For these, the following functions can be overridden by 2806platform code. They are executed outside of a C environment and without a stack. 2807 2808Function : plat\_crash\_console\_init 2809~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2810 2811:: 2812 2813 Argument : void 2814 Return : int 2815 2816This API is used by the crash reporting mechanism to initialize the crash 2817console. It must only use the general purpose registers x0 through x7 to do the 2818initialization and returns 1 on success. 2819 2820If you are trying to debug crashes before the console driver would normally get 2821registered, you can use this to register a driver from assembly with hardcoded 2822parameters. For example, you could register the 16550 driver like this: 2823 2824:: 2825 2826 .section .data.crash_console /* Reserve space for console structure */ 2827 crash_console: 2828 .zero 6 * 8 /* console_16550_t has 6 8-byte words */ 2829 func plat_crash_console_init 2830 ldr x0, =YOUR_16550_BASE_ADDR 2831 ldr x1, =YOUR_16550_SRCCLK_IN_HZ 2832 ldr x2, =YOUR_16550_TARGET_BAUD_RATE 2833 adrp x3, crash_console 2834 add x3, x3, :lo12:crash_console 2835 b console_16550_register /* tail call, returns 1 on success */ 2836 endfunc plat_crash_console_init 2837 2838If you're trying to debug crashes in BL1, you can call the console_xxx_core_init 2839function exported by some console drivers from here. 2840 2841Function : plat\_crash\_console\_putc 2842~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2843 2844:: 2845 2846 Argument : int 2847 Return : int 2848 2849This API is used by the crash reporting mechanism to print a character on the 2850designated crash console. It must only use general purpose registers x1 and 2851x2 to do its work. The parameter and the return value are in general purpose 2852register x0. 2853 2854If you have registered a normal console driver in ``plat_crash_console_init``, 2855you can keep the default implementation here (which calls ``console_putc()``). 2856 2857If you're trying to debug crashes in BL1, you can call the console_xxx_core_putc 2858function exported by some console drivers from here. 2859 2860Function : plat\_crash\_console\_flush 2861~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2862 2863:: 2864 2865 Argument : void 2866 Return : int 2867 2868This API is used by the crash reporting mechanism to force write of all buffered 2869data on the designated crash console. It should only use general purpose 2870registers x0 through x5 to do its work. The return value is 0 on successful 2871completion; otherwise the return value is -1. 2872 2873If you have registered a normal console driver in ``plat_crash_console_init``, 2874you can keep the default implementation here (which calls ``console_flush()``). 2875 2876If you're trying to debug crashes in BL1, you can call the console_xx_core_flush 2877function exported by some console drivers from here. 2878 2879Extternal Abort handling and RAS Support 2880---------------------------------------- 2881 2882Function : plat_ea_handler 2883~~~~~~~~~~~~~~~~~~~~~~~~~~ 2884 2885:: 2886 2887 Argument : int 2888 Argument : uint64_t 2889 Argument : void * 2890 Argument : void * 2891 Argument : uint64_t 2892 Return : void 2893 2894This function is invoked by the RAS framework for the platform to handle an 2895External Abort received at EL3. The intention of the function is to attempt to 2896resolve the cause of External Abort and return; if that's not possible, to 2897initiate orderly shutdown of the system. 2898 2899The first parameter (``int ea_reason``) indicates the reason for External Abort. 2900Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 2901 2902The second parameter (``uint64_t syndrome``) is the respective syndrome 2903presented to EL3 after having received the External Abort. Depending on the 2904nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 2905can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 2906 2907The third parameter (``void *cookie``) is unused for now. The fourth parameter 2908(``void *handle``) is a pointer to the preempted context. The fifth parameter 2909(``uint64_t flags``) indicates the preempted security state. These parameters 2910are received from the top-level exception handler. 2911 2912If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this 2913function iterates through RAS handlers registered by the platform. If any of the 2914RAS handlers resolve the External Abort, no further action is taken. 2915 2916If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers 2917could resolve the External Abort, the default implementation prints an error 2918message, and panics. 2919 2920Function : plat_handle_uncontainable_ea 2921~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2922 2923:: 2924 2925 Argument : int 2926 Argument : uint64_t 2927 Return : void 2928 2929This function is invoked by the RAS framework when an External Abort of 2930Uncontainable type is received at EL3. Due to the critical nature of 2931Uncontainable errors, the intention of this function is to initiate orderly 2932shutdown of the system, and is not expected to return. 2933 2934This function must be implemented in assembly. 2935 2936The first and second parameters are the same as that of ``plat_ea_handler``. 2937 2938The default implementation of this function calls 2939``report_unhandled_exception``. 2940 2941Function : plat_handle_double_fault 2942~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2943 2944:: 2945 2946 Argument : int 2947 Argument : uint64_t 2948 Return : void 2949 2950This function is invoked by the RAS framework when another External Abort is 2951received at EL3 while one is already being handled. I.e., a call to 2952``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 2953this function is to initiate orderly shutdown of the system, and is not expected 2954recover or return. 2955 2956This function must be implemented in assembly. 2957 2958The first and second parameters are the same as that of ``plat_ea_handler``. 2959 2960The default implementation of this function calls 2961``report_unhandled_exception``. 2962 2963Function : plat_handle_el3_ea 2964~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2965 2966:: 2967 2968 Return : void 2969 2970This function is invoked when an External Abort is received while executing in 2971EL3. Due to its critical nature, the intention of this function is to initiate 2972orderly shutdown of the system, and is not expected recover or return. 2973 2974This function must be implemented in assembly. 2975 2976The default implementation of this function calls 2977``report_unhandled_exception``. 2978 2979Build flags 2980----------- 2981 2982- **ENABLE\_PLAT\_COMPAT** 2983 All the platforms ports conforming to this API specification should define 2984 the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should 2985 be disabled. For more details on compatibility layer, refer 2986 `Migration Guide`_. 2987 2988There are some build flags which can be defined by the platform to control 2989inclusion or exclusion of certain BL stages from the FIP image. These flags 2990need to be defined in the platform makefile which will get included by the 2991build system. 2992 2993- **NEED\_BL33** 2994 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2995 build option should be supplied as a build option. The platform has the 2996 option of excluding the BL33 image in the ``fip`` image by defining this flag 2997 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2998 are used, this flag will be set to ``no`` automatically. 2999 3000C Library 3001--------- 3002 3003To avoid subtle toolchain behavioral dependencies, the header files provided 3004by the compiler are not used. The software is built with the ``-nostdinc`` flag 3005to ensure no headers are included from the toolchain inadvertently. Instead the 3006required headers are included in the TF-A source tree. The library only 3007contains those C library definitions required by the local implementation. If 3008more functionality is required, the needed library functions will need to be 3009added to the local implementation. 3010 3011Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3012been written specifically for TF-A. Fome implementation files have been obtained 3013from `FreeBSD`_, others have been written specifically for TF-A as well. The 3014files can be found in ``include/lib/libc`` and ``lib/libc``. 3015 3016SCC can be found in `http://www.simple-cc.org/`_. A copy of the `FreeBSD`_ 3017sources can be obtained from `http://github.com/freebsd/freebsd`_. 3018 3019Storage abstraction layer 3020------------------------- 3021 3022In order to improve platform independence and portability an storage abstraction 3023layer is used to load data from non-volatile platform storage. 3024 3025Each platform should register devices and their drivers via the Storage layer. 3026These drivers then need to be initialized by bootloader phases as 3027required in their respective ``blx_platform_setup()`` functions. Currently 3028storage access is only required by BL1 and BL2 phases. The ``load_image()`` 3029function uses the storage layer to access non-volatile platform storage. 3030 3031It is mandatory to implement at least one storage driver. For the Arm 3032development platforms the Firmware Image Package (FIP) driver is provided as 3033the default means to load data from storage (see the "Firmware Image Package" 3034section in the `User Guide`_). The storage layer is described in the header file 3035``include/drivers/io/io_storage.h``. The implementation of the common library 3036is in ``drivers/io/io_storage.c`` and the driver files are located in 3037``drivers/io/``. 3038 3039Each IO driver must provide ``io_dev_*`` structures, as described in 3040``drivers/io/io_driver.h``. These are returned via a mandatory registration 3041function that is called on platform initialization. The semi-hosting driver 3042implementation in ``io_semihosting.c`` can be used as an example. 3043 3044The Storage layer provides mechanisms to initialize storage devices before 3045IO operations are called. The basic operations supported by the layer 3046include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3047Drivers do not have to implement all operations, but each platform must 3048provide at least one driver for a device capable of supporting generic 3049operations such as loading a bootloader image. 3050 3051The current implementation only allows for known images to be loaded by the 3052firmware. These images are specified by using their identifiers, as defined in 3053[include/plat/common/platform\_def.h] (or a separate header file included from 3054there). The platform layer (``plat_get_image_source()``) then returns a reference 3055to a device and a driver-specific ``spec`` which will be understood by the driver 3056to allow access to the image data. 3057 3058The layer is designed in such a way that is it possible to chain drivers with 3059other drivers. For example, file-system drivers may be implemented on top of 3060physical block devices, both represented by IO devices with corresponding 3061drivers. In such a case, the file-system "binding" with the block device may 3062be deferred until the file-system device is initialised. 3063 3064The abstraction currently depends on structures being statically allocated 3065by the drivers and callers, as the system does not yet provide a means of 3066dynamically allocating memory. This may also have the affect of limiting the 3067amount of open resources per driver. 3068 3069-------------- 3070 3071*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.* 3072 3073.. _Migration Guide: platform-migration-guide.rst 3074.. _include/plat/common/platform.h: ../include/plat/common/platform.h 3075.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D 3076.. _User Guide: user-guide.rst 3077.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h 3078.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h 3079.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S 3080.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S 3081.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 3082.. _Power Domain Topology Design: psci-pd-tree.rst 3083.. _include/common/bl\_common.h: ../include/common/bl_common.h 3084.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 3085.. _Firmware Design: firmware-design.rst 3086.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 3087.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c 3088.. _Platform compatibility policy: https://github.com/ARM-software/arm-trusted-firmware/docs/platform-compatibility-policy.rst#2platform-compatibility-policy 3089.. _IMF Design Guide: interrupt-framework-design.rst 3090.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 3091.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 3092.. _FreeBSD: http://www.freebsd.org 3093.. _SCC: http://www.simple-cc.org/ 3094