| c00baeec | 27-Nov-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat:xilinx:zynqmp: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Mic
plat:xilinx:zynqmp: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8
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| e5936205 | 27-Nov-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
drivers: dcc: Support JTAG DCC console
The legacy console is gone. Re-add DCC console support based
on the multi-console framework.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilin
drivers: dcc: Support JTAG DCC console
The legacy console is gone. Re-add DCC console support based
on the multi-console framework.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ia8388721093bc1be3af40974530d7c9a9ae5f43e
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| 8078b5c5 | 30-Mar-2021 |
André Przywara <andre.przywara@arm.com> |
Merge changes from topic "allwinner_h616" into integration
* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
all
Merge changes from topic "allwinner_h616" into integration
* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
allwinner: Express memmap more dynamically
allwinner: Move sunxi_cpu_power_off_self() into platforms
allwinner: Move SEPARATE_NOBITS_REGION to platforms
doc: allwinner: Reorder sections, document memory mapping
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| 26123ca3 | 28-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DR
allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| fe90f9ae | 11-Dec-2020 |
Andre Przywara <andre.przywara@arm.com> |
doc: allwinner: Reorder sections, document memory mapping
Update the Allwinner platform documentation.
Reorder the section, to have the build instructions first, followed by
hints about the installa
doc: allwinner: Reorder sections, document memory mapping
Update the Allwinner platform documentation.
Reorder the section, to have the build instructions first, followed by
hints about the installation.
Add some ASCII art about the layout of our virtual memory map, which
uses a non-trivial condensed virtual address space.
Change-Id: Iaaa79b4366012394e15e4c1b26c212b5efb6ed6a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| ad329e50 | 21-Dec-2020 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
plat: imx8mm: Add in BL2 with FIP
Adds bl2 with FIP to the build required for mbed Linux booting where
we do:
BootROM -> SPL -> BL2 -> OPTEE -> u-boot
If NEED_BL2 is specified then BL2 will be bui
plat: imx8mm: Add in BL2 with FIP
Adds bl2 with FIP to the build required for mbed Linux booting where
we do:
BootROM -> SPL -> BL2 -> OPTEE -> u-boot
If NEED_BL2 is specified then BL2 will be built and BL31 will have
its address range modified upwards to accommodate. BL31 must be
loaded from a FIP in this case.
If NEED_BL2 is not specified then the current BL31 boot flow is
unaffected and u-boot SPL will load and execute BL31 directly.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I655343b3b689b1fc57cfbedda4d3dc2fbd549a96
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| 13d25345 | 08-Mar-2021 |
Manish Pandey <manish.pandey2@arm.com> |
doc: update maintainer list for Arm platforms
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I24a1697d0e0ec9289d272f0e96a252894faf12ef |
| 32d440c7 | 09-Mar-2021 |
Manish Pandey <manish.pandey2@arm.com> |
doc: re-format maintainer.rst file rendering
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9fafeb966eeec35527647282b953d88f6aa383be |
| 893716d7 | 03-Mar-2021 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "docs: Add GIC600AE FVP model version information" into integration |
| 051906bb | 01-Mar-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Add GIC600AE FVP model version information
Added GIC600AE FVP model version information.
Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe
docs: Add GIC600AE FVP model version information
Added GIC600AE FVP model version information.
Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 873d4241 | 02-Oct-2020 |
johpow01 <john.powell@arm.com> |
Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3
Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3 firmware.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
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| f1127926 | 15-Feb-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
docs: stm32mp1: correct formatting issues
Add blank lines before lists and code example.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I901646e0be74227af983079d0cbe05c6a217fab6 |
| d30a6615 | 24-Jan-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
doc: Build option to protect GICR frame
Added a build option 'FVP_GICR_REGION_PROTECTION' to make
redistributor frame of fused/unused cores as read only.
Change-Id: Ie85f86e2465b93321a92a888ce8712a
doc: Build option to protect GICR frame
Added a build option 'FVP_GICR_REGION_PROTECTION' to make
redistributor frame of fused/unused cores as read only.
Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 7dfb9911 | 22-Jun-2020 |
Jimmy Brisson <jimmy.brisson@arm.com> |
Add TRNG Firmware Interface service
This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and include
Add TRNG Firmware Interface service
This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and includes an entropy pool implementation to
avoid dropping any entropy requested from the platform.
Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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|
| 477e28de | 02-Feb-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "marvell-armada-docs" into integration
* changes:
docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell fi
Merge changes from topic "marvell-armada-docs" into integration
* changes:
docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image
docs: marvell: Fix description of flash-image.bin image
docs: marvell: Add information into CLOCKSPRESET option how to identify CPU frequency
docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra board
docs: marvell: Move Supported Marvell platforms to PLAT build option
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| 6803d989 | 02-Feb-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integration
* changes:
plat: marvell: armada: a3k: Do not use 'echo -e' in Makefile
docs: marvell: Update info about BOOTDEV=S
Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integration
* changes:
plat: marvell: armada: a3k: Do not use 'echo -e' in Makefile
docs: marvell: Update info about BOOTDEV=SATA
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| 72645d5b | 02-Feb-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integration
* changes:
docs: marvell: Update info about WTMI_IMG option
plat: marvell: armada: a3k: Remove unused variable WTM
Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integration
* changes:
docs: marvell: Update info about WTMI_IMG option
plat: marvell: armada: a3k: Remove unused variable WTMI_SYSINIT_IMG from Makefile
plat: marvell: armada: Show informative build messages and blank lines
plat: marvell: armada: Move definition of mrvl_flash target to common marvell_common.mk file
plat: marvell: armada: a3k: Use $(Q) instead of @
plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image
plat: marvell: armada: a3k: Build UART image files directly in $(BUILD_UART) subdirectory
plat: marvell: armada: a3k: Build intermediate files in $(BUILD_PLAT) directory
plat: marvell: armada: a3k: Correctly set DDR_TOPOLOGY and CLOCKSPRESET for WTMI
plat: marvell: armada: a3k: Allow use of the system Crypto++ library
docs: marvell: Update info about WTP and MV_DDR_PATH parameters
plat: marvell: armada: a3k: Add checks that WTP, MV_DDR_PATH and CRYPTOPP_PATH are correctly defined
docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches
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| ff46a41d | 01-Feb-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image
ESPRESSObin-Ultra TF-A build example was now just a copy+paste o
docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image
ESPRESSObin-Ultra TF-A build example was now just a copy+paste of previous
mentioned example. It produced debug binary with custom log level, which
was not described. So rather replace this duplicate build example by a full
example with all steps how to build production release of Marvell firmware
image for EspressoBin with 1GHz CPU and 1GB DDR4 RAM.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ief1b8bc96a3035ebd8421bd68dca5eb5c8d8fd52
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| f60f1e84 | 01-Feb-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Fix description of flash-image.bin image
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I192acab2a7f42cd80069faeac2d7823a05558dc6 |
| 23abf07c | 01-Feb-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Add information into CLOCKSPRESET option how to identify CPU frequency
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5310c30051703bbf9f377762a00eb6a8188c6fa1 |
| 9c3fffdc | 01-Feb-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra board
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I96c2d9d5bc6c69a1a66a29bf586a23375d63ab5a |
| 24e6e10b | 01-Feb-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Move Supported Marvell platforms to PLAT build option
Reformat list of boards, remove unsupported OcteonTX2 and mention
supported Turris MOX board.
Signed-off-by: Pali Rohár <pali@ke
docs: marvell: Move Supported Marvell platforms to PLAT build option
Reformat list of boards, remove unsupported OcteonTX2 and mention
supported Turris MOX board.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I22cea7f77fd078554c7f0ed4108781626209e563
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| 711a6bb7 | 27-Jan-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Update info about WTMI_IMG option
Default WTMI_IMG value was documented incorrectly. Also WTMI_IMG name may
be misleading as this option does not specify full WTMI image, just a main
docs: marvell: Update info about WTMI_IMG option
Default WTMI_IMG value was documented incorrectly. Also WTMI_IMG name may
be misleading as this option does not specify full WTMI image, just a main
loop (e.g. fuse.bin or custom RTOS image) without hardware initialization
code (DDR, CPU and clocks).
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I3de4a27ce2165b962fa628c992fd8f80151efd7c
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| 33af2937 | 28-Jan-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Update info about BOOTDEV=SATA
Information is taken from the post https://lists.denx.de/pipermail/u-boot/2017-July/299351.html
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id:
docs: marvell: Update info about BOOTDEV=SATA
Information is taken from the post https://lists.denx.de/pipermail/u-boot/2017-July/299351.html
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5f608e135ec56685a3e2b986a52670540d48a4bf
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| 8b920973 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image
This change separates building of flash and UART images, so it is possible
to build only one of these images. Also this
plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image
This change separates building of flash and UART images, so it is possible
to build only one of these images. Also this change allows make to build
them in parallel.
Target mrvl_flash now builds only flash image and mrvl_uart only UART
image. This change reflects it also in the documentation.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ie9ce4538d52188dd26d99dfeeb5ad171a5b818f3
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