1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6/dts-v1/; 7 8#include "stm32mp157.dtsi" 9#include "stm32mp15xc.dtsi" 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxaa-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 14 15/ { 16 model = "STMicroelectronics STM32MP157C eval daughter"; 17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 24 memory@c0000000 { 25 device_type = "memory"; 26 reg = <0xC0000000 0x40000000>; 27 }; 28 29 aliases { 30 serial0 = &uart4; 31 }; 32}; 33 34&bsec { 35 board_id: board_id@ec { 36 reg = <0xec 0x4>; 37 status = "okay"; 38 secure-status = "okay"; 39 }; 40}; 41 42&clk_hse { 43 st,digbypass; 44}; 45 46&cpu0 { 47 cpu-supply = <&vddcore>; 48}; 49 50&cpu1 { 51 cpu-supply = <&vddcore>; 52}; 53 54&cryp1 { 55 status="okay"; 56}; 57 58&i2c4 { 59 pinctrl-names = "default"; 60 pinctrl-0 = <&i2c4_pins_a>; 61 i2c-scl-rising-time-ns = <185>; 62 i2c-scl-falling-time-ns = <20>; 63 clock-frequency = <400000>; 64 status = "okay"; 65 66 pmic: stpmic@33 { 67 compatible = "st,stpmic1"; 68 reg = <0x33>; 69 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 70 interrupt-controller; 71 #interrupt-cells = <2>; 72 status = "okay"; 73 74 regulators { 75 compatible = "st,stpmic1-regulators"; 76 ldo1-supply = <&v3v3>; 77 ldo2-supply = <&v3v3>; 78 ldo3-supply = <&vdd_ddr>; 79 ldo5-supply = <&v3v3>; 80 ldo6-supply = <&v3v3>; 81 pwr_sw1-supply = <&bst_out>; 82 pwr_sw2-supply = <&bst_out>; 83 84 vddcore: buck1 { 85 regulator-name = "vddcore"; 86 regulator-min-microvolt = <1200000>; 87 regulator-max-microvolt = <1350000>; 88 regulator-always-on; 89 regulator-initial-mode = <0>; 90 regulator-over-current-protection; 91 }; 92 93 vdd_ddr: buck2 { 94 regulator-name = "vdd_ddr"; 95 regulator-min-microvolt = <1350000>; 96 regulator-max-microvolt = <1350000>; 97 regulator-always-on; 98 regulator-initial-mode = <0>; 99 regulator-over-current-protection; 100 }; 101 102 vdd: buck3 { 103 regulator-name = "vdd"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 regulator-always-on; 107 st,mask-reset; 108 regulator-initial-mode = <0>; 109 regulator-over-current-protection; 110 }; 111 112 v3v3: buck4 { 113 regulator-name = "v3v3"; 114 regulator-min-microvolt = <3300000>; 115 regulator-max-microvolt = <3300000>; 116 regulator-always-on; 117 regulator-over-current-protection; 118 regulator-initial-mode = <0>; 119 }; 120 121 vdda: ldo1 { 122 regulator-name = "vdda"; 123 regulator-min-microvolt = <2900000>; 124 regulator-max-microvolt = <2900000>; 125 }; 126 127 v2v8: ldo2 { 128 regulator-name = "v2v8"; 129 regulator-min-microvolt = <2800000>; 130 regulator-max-microvolt = <2800000>; 131 }; 132 133 vtt_ddr: ldo3 { 134 regulator-name = "vtt_ddr"; 135 regulator-min-microvolt = <500000>; 136 regulator-max-microvolt = <750000>; 137 regulator-always-on; 138 regulator-over-current-protection; 139 }; 140 141 vdd_usb: ldo4 { 142 regulator-name = "vdd_usb"; 143 }; 144 145 vdd_sd: ldo5 { 146 regulator-name = "vdd_sd"; 147 regulator-min-microvolt = <2900000>; 148 regulator-max-microvolt = <2900000>; 149 regulator-boot-on; 150 }; 151 152 v1v8: ldo6 { 153 regulator-name = "v1v8"; 154 regulator-min-microvolt = <1800000>; 155 regulator-max-microvolt = <1800000>; 156 }; 157 158 vref_ddr: vref_ddr { 159 regulator-name = "vref_ddr"; 160 regulator-always-on; 161 }; 162 163 bst_out: boost { 164 regulator-name = "bst_out"; 165 }; 166 167 vbus_otg: pwr_sw1 { 168 regulator-name = "vbus_otg"; 169 }; 170 171 vbus_sw: pwr_sw2 { 172 regulator-name = "vbus_sw"; 173 regulator-active-discharge = <1>; 174 }; 175 }; 176 177 onkey { 178 compatible = "st,stpmic1-onkey"; 179 power-off-time-sec = <10>; 180 status = "okay"; 181 }; 182 183 watchdog { 184 compatible = "st,stpmic1-wdt"; 185 status = "disabled"; 186 }; 187 }; 188}; 189 190&iwdg2 { 191 timeout-sec = <32>; 192 status = "okay"; 193}; 194 195&pwr_regulators { 196 vdd-supply = <&vdd>; 197 vdd_3v3_usbfs-supply = <&vdd_usb>; 198}; 199 200&rcc { 201 secure-status = "disabled"; 202 st,clksrc = < 203 CLK_MPU_PLL1P 204 CLK_AXI_PLL2P 205 CLK_MCU_PLL3P 206 CLK_PLL12_HSE 207 CLK_PLL3_HSE 208 CLK_PLL4_HSE 209 CLK_RTC_LSE 210 CLK_MCO1_DISABLED 211 CLK_MCO2_DISABLED 212 >; 213 214 st,clkdiv = < 215 1 /*MPU*/ 216 0 /*AXI*/ 217 0 /*MCU*/ 218 1 /*APB1*/ 219 1 /*APB2*/ 220 1 /*APB3*/ 221 1 /*APB4*/ 222 2 /*APB5*/ 223 23 /*RTC*/ 224 0 /*MCO1*/ 225 0 /*MCO2*/ 226 >; 227 228 st,pkcs = < 229 CLK_CKPER_HSE 230 CLK_FMC_ACLK 231 CLK_QSPI_ACLK 232 CLK_ETH_DISABLED 233 CLK_SDMMC12_PLL4P 234 CLK_DSI_DSIPLL 235 CLK_STGEN_HSE 236 CLK_USBPHY_HSE 237 CLK_SPI2S1_PLL3Q 238 CLK_SPI2S23_PLL3Q 239 CLK_SPI45_HSI 240 CLK_SPI6_HSI 241 CLK_I2C46_HSI 242 CLK_SDMMC3_PLL4P 243 CLK_USBO_USBPHY 244 CLK_ADC_CKPER 245 CLK_CEC_LSE 246 CLK_I2C12_HSI 247 CLK_I2C35_HSI 248 CLK_UART1_HSI 249 CLK_UART24_HSI 250 CLK_UART35_HSI 251 CLK_UART6_HSI 252 CLK_UART78_HSI 253 CLK_SPDIF_PLL4P 254 CLK_FDCAN_PLL4R 255 CLK_SAI1_PLL3Q 256 CLK_SAI2_PLL3Q 257 CLK_SAI3_PLL3Q 258 CLK_SAI4_PLL3Q 259 CLK_RNG1_LSI 260 CLK_RNG2_LSI 261 CLK_LPTIM1_PCLK1 262 CLK_LPTIM23_PCLK3 263 CLK_LPTIM45_LSE 264 >; 265 266 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 267 pll1: st,pll@0 { 268 cfg = < 2 80 0 0 0 PQR(1,0,0) >; 269 frac = < 0x800 >; 270 }; 271 272 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 273 pll2: st,pll@1 { 274 cfg = < 2 65 1 0 0 PQR(1,1,1) >; 275 frac = < 0x1400 >; 276 }; 277 278 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 279 pll3: st,pll@2 { 280 cfg = < 1 33 1 16 36 PQR(1,1,1) >; 281 frac = < 0x1a04 >; 282 }; 283 284 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 285 pll4: st,pll@3 { 286 cfg = < 3 98 5 7 7 PQR(1,1,1) >; 287 }; 288}; 289 290&rng1 { 291 status = "okay"; 292}; 293 294&rtc { 295 status = "okay"; 296}; 297 298&sdmmc1 { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 301 disable-wp; 302 st,sig-dir; 303 st,neg-edge; 304 st,use-ckin; 305 bus-width = <4>; 306 vmmc-supply = <&vdd_sd>; 307 sd-uhs-sdr12; 308 sd-uhs-sdr25; 309 sd-uhs-sdr50; 310 sd-uhs-ddr50; 311 status = "okay"; 312}; 313 314&sdmmc2 { 315 pinctrl-names = "default"; 316 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 317 non-removable; 318 no-sd; 319 no-sdio; 320 st,neg-edge; 321 bus-width = <8>; 322 vmmc-supply = <&v3v3>; 323 vqmmc-supply = <&vdd>; 324 mmc-ddr-3_3v; 325 status = "okay"; 326}; 327 328&uart4 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&uart4_pins_a>; 331 status = "okay"; 332}; 333