| 8445253e | 01-Oct-2020 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
morello: Add Morello platform documentation
Morello platform has a SCP which brings the primary Rainier CPU
out of reset which starts executing at BL31.
This patch provides documentation support fo
morello: Add Morello platform documentation
Morello platform has a SCP which brings the primary Rainier CPU
out of reset which starts executing at BL31.
This patch provides documentation support for Morello platform.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2
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| ccf220ad | 02-Oct-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
doc: Update list of supported FVP platforms
Updated the list of supported FVP platform as per latest
FVP platform release.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I45e
doc: Update list of supported FVP platforms
Updated the list of supported FVP platform as per latest
FVP platform release.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I45ef79aff147ed598a3a92ab6f6b277f7f70604a
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|
| 219e45cd | 02-Oct-2020 |
Jan Kiszka <jan.kiszka@siemens.com> |
doc: stm32mp1: Improve OP-TEE related documentation
stm32mp15_optee_defconfig has been dropped from U-Boot as it became
identical to stm32mp15_trusted_defconfig.
Furthermore give a hint how OP-TEE
doc: stm32mp1: Improve OP-TEE related documentation
stm32mp15_optee_defconfig has been dropped from U-Boot as it became
identical to stm32mp15_trusted_defconfig.
Furthermore give a hint how OP-TEE is supposed to be installed.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: Id8f0bd84a87e3a62072dd4405aadddcdd3511213
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| ea14b51b | 21-Sep-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Crypto library: Migrate support to MbedTLS v2.24.0
This patch migrates the mbedcrypto dependency for TF-A
to mbedTLS repo v2.24.0 which is the latest release tag.
The relevant documentation is updat
Crypto library: Migrate support to MbedTLS v2.24.0
This patch migrates the mbedcrypto dependency for TF-A
to mbedTLS repo v2.24.0 which is the latest release tag.
The relevant documentation is updated to reflect the
use of new version.
Change-Id: I116f44242e8c98e856416ea871d11abd3234dac1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| 2173b3e0 | 30-Sep-2020 |
André Przywara <andre.przywara@arm.com> |
Merge changes from topic "fpga_generic" into integration
* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add dev
Merge changes from topic "fpga_generic" into integration
* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add devicetree file
arm_fpga: Remove SPE PMU DT node if SPE is not available
arm_fpga: Adjust GICR size in DT to match number of cores
fdt: Add function to adjust GICv3 redistributor size
drivers: arm: gicv3: Allow detecting number of cores
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| c36aa3cf | 29-Sep-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Workaround for Cortex A77 erratum 1508412" into integration |
| a6c07e0d | 27-Aug-2020 |
Andre Przywara <andre.przywara@arm.com> |
arm_fpga: Add platform documentation
As the Arm Ltd. FPGA port is now working for all existing images, add
some documentation file.
Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6
Signed-off-b
arm_fpga: Add platform documentation
As the Arm Ltd. FPGA port is now working for all existing images, add
some documentation file.
Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| dfd5bfb0 | 22-Sep-2020 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
plat/arm: Add platform support for Morello
This patch adds support for Morello platform.
It is an initial port which includes only BL31 support
as the System Control Processor (SCP) is expected to t
plat/arm: Add platform support for Morello
This patch adds support for Morello platform.
It is an initial port which includes only BL31 support
as the System Control Processor (SCP) is expected to take
the role of primary bootloader.
Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
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| aa3efe3d | 14-Jul-2020 |
laurenw-arm <lauren.wehrmeister@arm.com> |
Workaround for Cortex A77 erratum 1508412
Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based
Workaround for Cortex A77 erratum 1508412
Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.
This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
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| 6ac269d1 | 18-Sep-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Select the Log Level for the Event Log Dump on Measured Boot at build time.
Builds in Debug mode with Measured Boot enabled might run out of trusted
SRAM. This patch allows to change the Log Level a
Select the Log Level for the Event Log Dump on Measured Boot at build time.
Builds in Debug mode with Measured Boot enabled might run out of trusted
SRAM. This patch allows to change the Log Level at which the Measured Boot
driver will dump the event log, so the latter can be accessed even on
Release builds if necessary, saving space on RAM.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I133689e313776cb3f231b774c26cbca4760fa120
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|
| b39dca40 | 16-Sep-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "doc: Recommend using C rather than assembly language" into integration |
| 51ca0917 | 15-Sep-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "doc: Correct CPACR.FPEN usage" into integration |
| 0901d339 | 12-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
doc: add description of "owner" field in SP layout file.
Change-Id: Iedaa83ed546eb2476849a8d53f6e05b847a48b23
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> |
| 093ba62e | 21-Aug-2020 |
Peng Fan <peng.fan@nxp.com> |
doc: Correct CPACR.FPEN usage
To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not
clearing.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dac
doc: Correct CPACR.FPEN usage
To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not
clearing.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dacd0
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|
| 61f0ffc4 | 05-Aug-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Neoverse N1 erratum 1868343
Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the CPUACT
Workaround for Neoverse N1 erratum 1868343
Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.
SDEN can be found here:
https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
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|
| 70b6701b | 07-Sep-2020 |
joanna.farley <joanna.farley@arm.com> |
Merge "doc: Improve contribution guidelines" into integration |
| cd62b834 | 03-Sep-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Add Chris Kay as code owner for CMake Build Definitions." into integration |
| aec40abc | 03-Sep-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add Chris Kay as code owner for CMake Build Definitions.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I69365d4aed1160af41e291f6e4b1dd31cbd12e02 |
| 959a0486 | 02-Sep-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "maintainers: step down as code owner of UniPhier platform" into integration |
| e98d934a | 01-Sep-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Remove Jack Bond-Preston as CMake Build Definitions code owner" into integration |
| 8a737ee4 | 29-Aug-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
maintainers: step down as code owner of UniPhier platform
I am leaving Socionext. Orphan the UniPhier platform until somebody
takes the role.
Change-Id: I54d3da6d49c1ccaaa475431654db578b683db88a
Si
maintainers: step down as code owner of UniPhier platform
I am leaving Socionext. Orphan the UniPhier platform until somebody
takes the role.
Change-Id: I54d3da6d49c1ccaaa475431654db578b683db88a
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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|
| fd1fe2d5 | 28-Aug-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Remove Jack Bond-Preston as CMake Build Definitions code owner
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I542ec3cf1bb929a5656dda6dbad816b69837c646 |
| e87c8231 | 23-Aug-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
doc: Update the cot-binding for nv-counter node
Updated the cot-binding documentation to add 'id'
property for the trusted and non-trusted nv-counters.
Signed-off-by: Manish V Badarkhe <Manish.Bada
doc: Update the cot-binding for nv-counter node
Updated the cot-binding documentation to add 'id'
property for the trusted and non-trusted nv-counters.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If1c628c5b90fe403dd96c7cd0cd04f37288c965c
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| 7969747e | 14-Aug-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
doc: Improve contribution guidelines
- Add some guidance about the type of information a patch author should
provide to facilitate the review (and for future reference).
- Make a number of implic
doc: Improve contribution guidelines
- Add some guidance about the type of information a patch author should
provide to facilitate the review (and for future reference).
- Make a number of implicit expectations explicit:
- Every patch must compile.
- All CI tests must pass.
- Mention that the patch author is expected to add reviewers and explain
how to choose them.
- Explain the patch submission rules in terms of Gerrit labels.
Also do some cosmetic changes, like adding empty lines, shuffling some
paragraphs around.
Change-Id: I6dac486684310b5a35aac7353e10fe5474a81ec5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 768f8331 | 21-Aug-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "doc: Minor formatting improvement in the coding guidelines document" into integration |