| 1d24eb33 | 09-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1774420" into integration |
| 741dd04c | 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1925756
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.
SDEN can be found he
errata: workaround for Neoverse V1 errata 1925756
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52
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| 143b1965 | 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1852267
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1852267
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ide5e0bc09371fbc91c2385ffdff74e604beb2dbe
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| 4789cf66 | 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1774420
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1774420
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123
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| 5e4e13e1 | 02-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "fw-update-2" into integration
* changes:
feat(sw_crc32): add software CRC32 support
refactor(hw_crc32): renamed hw_crc32 to tf_crc32
feat(fwu): avoid booting with an
Merge changes from topic "fw-update-2" into integration
* changes:
feat(sw_crc32): add software CRC32 support
refactor(hw_crc32): renamed hw_crc32 to tf_crc32
feat(fwu): avoid booting with an alternate boot source
docs(fwu): add firmware update documentation
feat(fwu): avoid NV counter upgrade in trial run state
feat(plat/arm): add FWU support in Arm platforms
feat(fwu): initialize FWU driver in BL2
feat(fwu): add FWU driver
feat(fwu): introduce FWU platform-specific functions declarations
docs(fwu_metadata): add FWU metadata build options
feat(fwu_metadata): add FWU metadata header and build options
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| 0f20e50b | 20-Jun-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(fwu): add firmware update documentation
Added firmware update documentation for:
1. PSA firmware update build flag
2. Porting guidelines to set the addresses of FWU metadata image
and update
docs(fwu): add firmware update documentation
Added firmware update documentation for:
1. PSA firmware update build flag
2. Porting guidelines to set the addresses of FWU metadata image
and updated components in I/O policy
Change-Id: Iad3eb68b4be01a0b5850b69a067c60fcb464f54b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| c7e39dcf | 02-Aug-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(ff-a): change manifest messaging method" into integration |
| 34f702d5 | 16-Mar-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(fwu_metadata): add FWU metadata build options
Added the build options used in defining the firmware update metadata
structure.
Change-Id: Idd40ea629e643e775083f283b75c80f6c026b127
Signed-off-b
docs(fwu_metadata): add FWU metadata build options
Added the build options used in defining the firmware update metadata
structure.
Change-Id: Idd40ea629e643e775083f283b75c80f6c026b127
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 6ea1a75d | 29-Jul-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(plat/marvell): move doc platform build options into own subsections" into integration |
| 92024f81 | 20-Jul-2021 |
Pali Rohár <pali@kernel.org> |
refactor(plat/marvell): move doc platform build options into own subsections
Update documentation and group platform specific build options into
their own subsections.
Signed-off-by: Pali Rohár <pa
refactor(plat/marvell): move doc platform build options into own subsections
Update documentation and group platform specific build options into
their own subsections.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I05927d8abf9f811493c49b856f06329220e7d8bb
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| 76cce571 | 25-Jul-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge "docs(maintainers): update imx8 entry" into integration |
| 7b514399 | 23-Jul-2021 |
Peng Fan <peng.fan@nxp.com> |
docs(maintainers): update imx8 entry
Add myself as i.MX8 maintainer.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ib037c24a75d42febd79f2eb1ab3b985356dbfb58 |
| bf3ce993 | 21-Apr-2021 |
Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
feat: adding the diphda platform
This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.
Diphda uses a FIP image located in the flash. The FIP contain
feat: adding the diphda platform
This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.
Diphda uses a FIP image located in the flash. The FIP contains the
following components:
- BL2
- BL31
- BL32
- BL32 SPMC manifest
- BL33
- The TBB certificates
The board boot relies on CoT (chain of trust). The trusted-firmware-a
BL2 is extracted from the FIP and verified by the Secure Enclave
processor. BL2 verification relies on the signature area at the
beginning of the BL2 image. This area is needed by the SecureEnclave
bootloader.
Then, the application processor is released from reset and starts by
executing BL2.
BL2 performs the actions described in the trusted-firmware-a TBB design
document.
Signed-off-by: Rui Miguel Silva <rui.silva@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d
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| bb320dbc | 06-May-2021 |
Maksims Svecovs <maksims.svecovs@arm.com> |
feat(ff-a): change manifest messaging method
Align documentation with changes of messaging method for partition
manifest:
- Bit[0]: support for receiving direct message requests
- Bit[1]
feat(ff-a): change manifest messaging method
Align documentation with changes of messaging method for partition
manifest:
- Bit[0]: support for receiving direct message requests
- Bit[1]: support for sending direct messages
- Bit[2]: support for indirect messaging
- Bit[3]: support for managed exit
Change the optee_sp_manifest to align with the new messaging method
description.
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: I333e82c546c03698c95f0c77293018f8dca5ba9c
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|
| 302b4dfb | 21-Jul-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(plat/versal): add support for SLS mitigation
This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerabili
feat(plat/versal): add support for SLS mitigation
This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerability. Enable this by adding the option HARDEN_SLS_ALL=1,
default this will be disabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0d498d9e96903fcb879993ad491949f6f17769b2
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| e18f4aaf | 20-Jul-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "marvell-a3k-a8k-updates" into integration
* changes:
fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive
refactor(plat/marvell/a3k): Rename *_CFG and *_SIG
Merge changes from topic "marvell-a3k-a8k-updates" into integration
* changes:
fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive
refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables
refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB
refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable
fix(plat/marvell/a3k): Fix check for external dependences
fix(plat/marvell/a8k): Add missing build dependency for BLE target
fix(plat/marvell/a8k): Correctly set include directories for individual targets
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
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| c31c82df | 19-Jul-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1940577" into integration |
| 182ce101 | 07-Oct-2020 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 1940577
Neoverse V1 erratum 1940577 is a Cat B erratum, present in some
revisions of the V1 processor core. The workaround is to insert a
DMB ST before acq
errata: workaround for Neoverse V1 errata 1940577
Neoverse V1 erratum 1940577 is a Cat B erratum, present in some
revisions of the V1 processor core. The workaround is to insert a
DMB ST before acquire atomic instructions without release semantics.
This issue is present in revisions r0p0 - r1p1 but this workaround
only applies to revisions r1p0 - r1p1, there is no workaround for older
versions.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa
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| 8cf5afaf | 19-Jul-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I2b3aa9bd,I3237199b into integration
* changes:
docs: add mt6795 to deprecated list
feat(plat/mediatek/mt8195): add DCM driver |
| 586aafa3 | 19-Jul-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1791573" into integration |
| fc3300a5 | 13-Jul-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
docs: add mt6795 to deprecated list
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2b3aa9bd0c23c360ecee673c68e1b2c92bc6d2be |
| 33e3e925 | 03-May-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
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|
| c7911137 | 16-Jul-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(maintainers): add Julius Werner as Rockchip platform code owner" into integration |
| 8d15e46c | 12-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: update supported FVP models as per release 11.15.14
Change-Id: I65da6ead356e3f4ee47c5a6bf391f65309bafcdd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> |
| c0cb6122 | 08-Jul-2021 |
Julius Werner <jwerner@chromium.org> |
docs(maintainers): add Julius Werner as Rockchip platform code owner
The two existing plat/rockchip code owners seem to be no longer active
in the project and are not responding to reviews. There ha
docs(maintainers): add Julius Werner as Rockchip platform code owner
The two existing plat/rockchip code owners seem to be no longer active
in the project and are not responding to reviews. There have been a
couple of small fixup patches[1][2][3] pending for months that couldn't
be checked in for lack of Code-Owner-Review+1 flag. Add myself to the
code owner list to unblock this bottleneck (I have been deeply involved
in the rk3399 port, at least, so I know most of the code reasonably
well).
[1] https://review.trustedfirmware.org/9616
[2] https://review.trustedfirmware.org/9990
[2] https://review.trustedfirmware.org/10415
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic7b2bb73c35a9bea91ff46ee445a22819d2045d9
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