fix(cpus): workaround for C1-Ultra erratum 3865171

C1-Ultra erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3865171

C1-Ultra erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I8bfe15fdd1d028d43d8730e7d43f72c9f15810d7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3815514

C1-Ultra erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3815514

C1-Ultra erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR5_EL1[13] to 1.
Setting CPUACTLR5_EL1[13] to 1 is expected to result in a small
performance degradation for workloads that use MTE. The
degradation might be approximately 1.6% when using MTE imprecise
mode or 0.9% for MTE precise mode.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I2d6b0ee282010139d8dc406800f2738b39113957
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3705939

C1-Ultra erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3705939

C1-Ultra erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR_EL1[48] to 1,
which disables a RDFFR optimization. Setting this bit has
negligible impact on GB6/SPECint performance, but will have an
impact on SVE RDFFR performance.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I88343236af86a9bb0b0ce644296d5929d7b956d1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3684152

C1-Ultra erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL

fix(cpus): workaround for C1-Ultra erratum 3684152

C1-Ultra erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL1[60:58] to
3'b001, which has a small perf impact.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I3747b2a99785602bd2a3bddac3a69a934e7f4b37
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3651221

C1-Ultra erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by disabling the affec

fix(cpus): workaround for C1-Ultra erratum 3651221

C1-Ultra erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by disabling the affected prefetcher
by setting CPUACTLR6_EL1[41] to 1.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I0498a81a62bbea666b503cdd5a6dbcae7eab0dce
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Ultra erratum 3502731

C1-Ultra erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3502731

C1-Ultra erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR4[23] to 1,
which will disable Memory Renaming optimization.
The performance impact of setting this chicken bit is about
0.82% in GB6.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: Iaf832b66aeed937edbb1e9be29de41b0f2b5d70c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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docs: update Ignored Checkpatch Warnings chapter

The warning about lines over 80 characters has been deprecated in kernel
since 2020 [1]. And the checkpatch script used in TF-A-ci-scripts was
then u

docs: update Ignored Checkpatch Warnings chapter

The warning about lines over 80 characters has been deprecated in kernel
since 2020 [1]. And the checkpatch script used in TF-A-ci-scripts was
then updated in 2021 [2]. Several parts of TF-A still use the 80
character limit, so the Line Length chapter in the file
docs/process/coding-style.rst is kept as-is.

The warning about volatile should not appear if the .checkpatch.conf
is used. Add a sentence about .checkpatch.conf to clarify that.

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bdc48fa11e46f867ea4d75fa59ee87a7f48be144
[2]: https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/11115

Change-Id: Ice83660f90969ef9b9e5f1d5afa2e15c032bfdf1
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which v

fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which verified this feature.

BREAKING CHANGE: platforms can no longer retrieve the host ROTPK from
the RSE as these are no longer provisioned.

Change-Id: I2c852855e53c36e77f639f17f4c181290d95ccff
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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docs(per-cpu): update diagram for NUMA enabled per-cpu layout

Update the per-cpu-numa-enabled diagram to match the current
implementation after recent merges.

Signed-off-by: Sammit Joshi <sammit.jo

docs(per-cpu): update diagram for NUMA enabled per-cpu layout

Update the per-cpu-numa-enabled diagram to match the current
implementation after recent merges.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Change-Id: I1a3ac0c4823c5d6b0b451884801ff9d66fa9a476

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Merge "fix(fvp): fully remove FVP_Foundation" into integration

fix(fvp): fully remove FVP_Foundation

It was removed with patch 4f6c9397b61824b320f7b16b6267d9928dc88998 but
some bits remain. Remove them.

Change-Id: Ia40d97ca81983006e470b061d913d238cf73b6f9
Sign

fix(fvp): fully remove FVP_Foundation

It was removed with patch 4f6c9397b61824b320f7b16b6267d9928dc88998 but
some bits remain. Remove them.

Change-Id: Ia40d97ca81983006e470b061d913d238cf73b6f9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED" into integration

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've gained
lots of quality of life features that allow for better feature
enablement. This patch converts USE_SPINLOCK_CAS to tri-state and adds
it to FEATURE_DETECTION to align with all other features.

Instead of introducing the assembly checking for tri-state, this patch
translates all locking routines to C inline assembly and uses the
standard C helpers. The main benefit is that this gives greater
visibility to the compiler about what the functions are doing and lets
it optimise better. Namely, it is able to allocate registers itself and
inline the functions when LTO is enabled.

An unsuccessful attempt was made to use the instructions directly and
have even flow control in C. This, however, made code very complicated
and less efficient in the tight loops of the spinlock.

The last use of ARM_ARCH_AT_LEAST goes away with this change and so this
macro is removed. It has now been fully superseded by the FEAT_STATE
framework.

This change exposes a limitation - RME_GPT_BITLOCK_BLOCK requires
USE_SPINLOCK_CAS. This patch does not address this in any way but makes
the relationship explicit.

Change-Id: I580081549aceded2dca3e0f4564ee7510a7e56ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(measured-boot): enable dynamic hash provisioning

Introduce dynamic hash provisioning for Measured Boot by removing the
previous static hash-selection path and allowing platforms to supply
algor

feat(measured-boot): enable dynamic hash provisioning

Introduce dynamic hash provisioning for Measured Boot by removing the
previous static hash-selection path and allowing platforms to supply
algorithm metadata at runtime. Add mboot_find_event_log_metadata() as a
common helper for resolving image metadata. Update the Event Log build
logic to use MAX_DIGEST_SIZE and MAX_HASH_COUNT, deprecate legacy
MBOOT_EL_HASH_ALG, and warn when it is used. Adjust MbedTLS
configuration to enable hash algorithms automatically when Measured Boot
is enabled.

Change-Id: I704e1a5005f6caad3d51d868bacc53699b6dd64f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat: add TPM/TCG hashing helper to crypto module

Introduce crypto_mod_tcg_hash(), a helper that maps TPM/TCG algorithm
identifiers to the platform crypto backend. This ensures that Event Log
measur

feat: add TPM/TCG hashing helper to crypto module

Introduce crypto_mod_tcg_hash(), a helper that maps TPM/TCG algorithm
identifiers to the platform crypto backend. This ensures that Event Log
measurements use the same digest implementation as the platform PCR
backend regardless of whether hashing is performed in software,
hardware, or a discrete TPM. Update the measured boot design document,
expose the new API via public headers, and implement the helper in the
common crypto module.

Change-Id: Id4f7f1d0014ab42064c46819965417daef71555b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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docs(security): update CVE-2024-7881 affected CPU revisions

This patch updates the affected versions for the following CPUs -
Cortex-X3 [1], Cortex-X4 [2], Cortex-X925 [3], Neoverse-V2 [4],
Neoverse

docs(security): update CVE-2024-7881 affected CPU revisions

This patch updates the affected versions for the following CPUs -
Cortex-X3 [1], Cortex-X4 [2], Cortex-X925 [3], Neoverse-V2 [4],
Neoverse-V3 [5] and Neoverse-V3AE [6].
Errata IDs for reference in the respective SDENs

Cortex-X3 - 3692984
Cortex-X4 - 3692983
Cortex-X925 - 3692980
Neoverse-V2 - 3696445
Neoverse-V3/V3AE - 3696307

[1] https://developer.arm.com/documentation/SDEN-2055130/latest/
[2] https://developer.arm.com/documentation/SDEN-2432808/latest
[3] https://developer.arm.com/documentation/109180/latest/
[4] https://developer.arm.com/documentation/SDEN-2332927/latest
[5] https://developer.arm.com/documentation/SDEN-2891958/latest/
[6] https://developer.arm.com/documentation/SDEN-2615521/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iad109561a144169fd3805c179a4f8e3bfdd59a65

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docs(maintainers): add Gabriel as clock framework maintainer

Gabriel created this clock framework, first for ST platforms, but it can
be used by others. Adding him as maintainer.

Change-Id: I7af885

docs(maintainers): add Gabriel as clock framework maintainer

Gabriel created this clock framework, first for ST platforms, but it can
be used by others. Adding him as maintainer.

Change-Id: I7af8857def86b8042b9ddd3709f4888df51f6544
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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docs(maintainers): sort frameworks alphabetically

Sort the "Drivers, Libraries and Framework Code" chapter alphabetically.

Change-Id: I7fc84d2c72085851514dcc9aa65825bffc7eba39
Signed-off-by: Yann G

docs(maintainers): sort frameworks alphabetically

Sort the "Drivers, Libraries and Framework Code" chapter alphabetically.

Change-Id: I7fc84d2c72085851514dcc9aa65825bffc7eba39
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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docs(security): update CVE-2024-7881 affected CPUs list

This patch updates the affected CPUs list to include the following
CPUs - C1-Premium, C1-Pro and C1-Ultra.

Signed-off-by: Arvind Ram Prakash

docs(security): update CVE-2024-7881 affected CPUs list

This patch updates the affected CPUs list to include the following
CPUs - C1-Premium, C1-Pro and C1-Ultra.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia2cc39d0f91bab89a911e271cf83c788d71bb85c

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docs(security): add CVE-2024-5660 and CVE-2024-7881 reference links

Add missing hyperlink targets for CVE-2024-5660 and CVE-2024-7881 in
cpu-specific-build-macros.rst to allow cross-referencing thes

docs(security): add CVE-2024-5660 and CVE-2024-7881 reference links

Add missing hyperlink targets for CVE-2024-5660 and CVE-2024-7881 in
cpu-specific-build-macros.rst to allow cross-referencing these CVEs
from documentation.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia3c003d5c359f101f230fbd54845f61117456abb

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Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): wor

Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): workaround for Cortex-A725 erratum 2936490
fix(cpus): workaround for Cortex-A725 erratum 2874943

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Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): u

Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): update feature names and comments
fix(cpufeat): simplify AArch32 feature disablement

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Merge changes from topic "xl/a65-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A65 erratum 1541130
fix(cpus): workaround for Cortex-A65 erratum 1227419
fix(cpus): workar

Merge changes from topic "xl/a65-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A65 erratum 1541130
fix(cpus): workaround for Cortex-A65 erratum 1227419
fix(cpus): workaround for Cortex-A65 erratum 1179935

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fix(cpus): workaround for Cortex-A725 erratum 3456106

Cortex-A725 erratum 3456106 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A725 erratum 3456106

Cortex-A725 erratum 3456106 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by having Speculation Barrier (SB)
instruction after the writes to the PSTATE.SSBS.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I10d1e8cb4da19ba4101a5617245ff75866707d25
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A65 erratum 1541130

Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.

This erratum can be

fix(cpus): workaround for Cortex-A65 erratum 1541130

Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.

This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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