| a2506c31 | 11-Oct-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "revert(cpus): "Revert workaround for A77 erratum 1800714"" into integration |
| 08e2fdbd | 27-Sep-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
revert(cpus): "Revert workaround for A77 erratum 1800714"
Reinstate the workaround introduced in commit
9bbc03a6e0608a949d66d9da6db12a455b452bfb. The cited change to the SDEN
could not be found and
revert(cpus): "Revert workaround for A77 erratum 1800714"
Reinstate the workaround introduced in commit
9bbc03a6e0608a949d66d9da6db12a455b452bfb. The cited change to the SDEN
could not be found and there are no known problems with the workaround.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iec9938f173e7565024aca798f224df339de90806
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| 1bc78557 | 16-Sep-2022 |
Tamas Ban <tamas.ban@arm.com> |
docs: add PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE to porting-guide.rst
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I79761347919a0dfa86a29b5424f1d34fc4ab91cb |
| 50a43b0f | 29-Jun-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(drtm): steps to run DRTM implementation
Documented steps to run DRTM implementation.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I30dd8c1088a54a8906389c2584d922862610
docs(drtm): steps to run DRTM implementation
Documented steps to run DRTM implementation.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I30dd8c1088a54a8906389c2584d922862610dae0
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| b3b227ff | 22-Jun-2022 |
Lucian Paul-Trifu <lucian.paultrifu@gmail.com> |
docs(drtm): add platform APIs for DRTM
Documented platform APIs for DRTM
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Cha
docs(drtm): add platform APIs for DRTM
Documented platform APIs for DRTM
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I22749c26bbe7b3271705dd3db07e8597fce6225b
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| b139f1cf | 15-Aug-2022 |
Mikael Olsson <mikael.olsson@arm.com> |
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.
To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.
The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277
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| bd063a73 | 21-Sep-2022 |
Joel Goddard <joel.goddard@arm.com> |
refactor(cpu): use the updated IP name for Demeter CPU
Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the u
refactor(cpu): use the updated IP name for Demeter CPU
Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the updated IP name.
Signed-off-by: Joel Goddard <joel.goddard@arm.com>
Change-Id: Ia4bf45bf47807c06f4c966861230faea420d088f
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| e8f4ec1a | 03-Oct-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "st_uart_updates" into integration
* changes:
feat(stm32mp1): add early console in SP_min
feat(st): properly manage early console
feat(st-uart): manage STM32MP_RECONFI
Merge changes from topic "st_uart_updates" into integration
* changes:
feat(stm32mp1): add early console in SP_min
feat(st): properly manage early console
feat(st-uart): manage STM32MP_RECONFIGURE_CONSOLE
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
feat(st): add trace for early console
fix(stm32mp1): enable crash console in FIQ handler
feat(st-uart): add initialization with the device tree
refactor(stm32mp1): move DT_UART_COMPAT in include file
feat(stm32mp1): configure the serial boot load address
fix(stm32mp1): update the FIP load address for serial boot
refactor(st): configure baudrate for UART programmer
refactor(st-uart): compute the over sampling dynamically
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|
| 2c16b802 | 30-Sep-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(ras): trap "RAS error record" accesses only for NS" into integration |
| ea7aee20 | 29-Sep-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(rmmd): return X4 output value" into integration |
| 00e8f79c | 27-Sep-2022 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): trap "RAS error record" accesses only for NS
RAS_TRAP_LOWER_EL_ERR_ACCESS was used to prevent access to RAS error
record registers (RAS ERR* & RAS ERX*) from lower EL's in any security
sta
fix(ras): trap "RAS error record" accesses only for NS
RAS_TRAP_LOWER_EL_ERR_ACCESS was used to prevent access to RAS error
record registers (RAS ERR* & RAS ERX*) from lower EL's in any security
state. To give more fine grain control per world basis re-purpose this
macro to RAS_TRAP_NS_ERR_REC_ACCESS, which will enable the trap only
if Error record registers are accessed from NS.
This will also help in future scenarios when RAS handling(in Firmware
first handling paradigm)can be offloaded to a secure partition.
This is first patch in series to refactor RAS framework in TF-A.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifa7f60bc8c82c9960adf029001bc36c443016d5d
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| 8e51ccca | 23-Sep-2022 |
AlexeiFedorov <Alexei.Fedorov@arm.com> |
fix(rmmd): return X4 output value
Return values contained in 'smc_result' structure
are shifted down by one register:
X1 written by RMM is returned to NS in X0 and
X5 is returned in X4.
Signed-off-
fix(rmmd): return X4 output value
Return values contained in 'smc_result' structure
are shifted down by one register:
X1 written by RMM is returned to NS in X0 and
X5 is returned in X4.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I92907ac3ff3bac8554643ae7c198a4a758c38cb3
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| 14ec900a | 27-Sep-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "docs(maintainers): add myself as TC code owner" into integration |
| 8fecda3c | 21-Sep-2022 |
Anders Dellien <anders.dellien@arm.com> |
docs(maintainers): add myself as TC code owner
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic67334bf1a979cb7b7355d0dcca7eb94752c4611 |
| d8d0ea9a | 26-Sep-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs(fwu): update firmware update design" into integration |
| 156709dd | 13-Sep-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
This flag will be used in BL32, to reconfigure UART parameters for
the early or crash console. By default, it is zero, as UART is
already configured i
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
This flag will be used in BL32, to reconfigure UART parameters for
the early or crash console. By default, it is zero, as UART is
already configured in BL2.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b28ff489479ab04a2fade027933524cdd36e959
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| 4b2f23e5 | 15-Mar-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it ove
feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.
To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
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| def661b6 | 22-Sep-2022 |
Michal Simek <michal.simek@amd.com> |
docs(maintainers): update xilinx record to cover docs
Recently new Xilinx Versal NET platform has been merged but documentation
cover only zynqmp. Fix the fragment to cover all Xilinx documentation.
docs(maintainers): update xilinx record to cover docs
Recently new Xilinx Versal NET platform has been merged but documentation
cover only zynqmp. Fix the fragment to cover all Xilinx documentation.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I10f8f865ca8d46518135adb80ba0ba4470534529
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| cdbea240 | 21-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "docs(build): update GCC to 11.3.Rel1 version" into integration |
| 4efdc488 | 31-Aug-2022 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): add documentation for Versal NET SoC
Add description for Versal NET SoC.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
feat(versal-net): add documentation for Versal NET SoC
Add description for Versal NET SoC.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: Idcbb893c6b9e46512308c53ba2a0bee48a022b0a
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| b86cbe10 | 16-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "provencore-spd" into integration
* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL
Merge changes from topic "provencore-spd" into integration
* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL1 SGIs
show more ...
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| eb3d4015 | 04-Jul-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(fwu): update firmware update design
Refactored legacy firmware design and added details about PSA
firmware updates.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9c123
docs(fwu): update firmware update design
Refactored legacy firmware design and added details about PSA
firmware updates.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9c123b3f62580d4271dbaff0a728b6412fae7890
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| b0980e58 | 08-Sep-2021 |
Florian Lugou <florian.lugou@provenrun.com> |
feat(services): add a SPD for ProvenCore
Adds a dispatcher for ProvenCore based on the test secure payload
dispatcher.
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I978afc3
feat(services): add a SPD for ProvenCore
Adds a dispatcher for ProvenCore based on the test secure payload
dispatcher.
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I978afc3af6a6f65791655685a7bc80070673c9f3
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| 158ed580 | 27-Jul-2022 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SY
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| 95925676 | 13-Sep-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(cpus): workaround for Cortex-A710 2216384" into integration |