1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36.. _arm_cpu_macros_errata_workarounds: 37 38CPU Errata Workarounds 39---------------------- 40 41TF-A exports a series of build flags which control the errata workarounds that 42are applied to each CPU by the reset handler. The errata details can be found 43in the CPU specific errata documents published by Arm: 44 45- `Cortex-A53 MPCore Software Developers Errata Notice`_ 46- `Cortex-A57 MPCore Software Developers Errata Notice`_ 47- `Cortex-A72 MPCore Software Developers Errata Notice`_ 48 49The errata workarounds are implemented for a particular revision or a set of 50processor revisions. This is checked by the reset handler at runtime. Each 51errata workaround is identified by its ``ID`` as specified in the processor's 52errata notice document. The format of the define used to enable/disable the 53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 54is for example ``A57`` for the ``Cortex_A57`` CPU. 55 56Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to 57write errata workaround functions. 58 59All workarounds are disabled by default. The platform is responsible for 60enabling these workarounds according to its requirement by defining the 61errata workaround build flags in the platform specific makefile. In case 62these workarounds are enabled for the wrong CPU revision then the errata 63workaround is not applied. In the DEBUG build, this is indicated by 64printing a warning to the crash console. 65 66In the current implementation, a platform which has more than 1 variant 67with different revisions of a processor has no runtime mechanism available 68for it to specify which errata workarounds should be enabled or not. 69 70The value of the build flags is 0 by default, that is, disabled. A value of 1 71will enable it. 72 73For Cortex-A9, the following errata build flags are defined : 74 75- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 76 CPU. This needs to be enabled for all revisions of the CPU. 77 78For Cortex-A15, the following errata build flags are defined : 79 80- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 82 83- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 85 86For Cortex-A17, the following errata build flags are defined : 87 88- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 90 91- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 93 94For Cortex-A35, the following errata build flags are defined : 95 96- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 98 99For Cortex-A53, the following errata build flags are defined : 100 101- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 103 104- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 106 107- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 109 110- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 115 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 116 sections. 117 118- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 120 r0p4 and onwards, this errata is enabled by default in hardware. 121 122- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 123 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 124 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 125 which are 4kB aligned. 126 127- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 128 CPUs. Though the erratum is present in every revision of the CPU, 129 this workaround is only applied to CPUs from r0p3 onwards, which feature 130 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 131 Earlier revisions of the CPU have other errata which require the same 132 workaround in software, so they should be covered anyway. 133 134- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 135 revisions of Cortex-A53 CPU. 136 137For Cortex-A55, the following errata build flags are defined : 138 139- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 140 CPU. This needs to be enabled only for revision r0p0 of the CPU. 141 142- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 143 CPU. This needs to be enabled only for revision r0p0 of the CPU. 144 145- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 146 CPU. This needs to be enabled only for revision r0p0 of the CPU. 147 148- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 149 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 150 151- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 152 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 153 154- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 155 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 156 157- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 158 revisions of Cortex-A55 CPU. 159 160For Cortex-A57, the following errata build flags are defined : 161 162- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 163 CPU. This needs to be enabled only for revision r0p0 of the CPU. 164 165- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 166 CPU. This needs to be enabled only for revision r0p0 of the CPU. 167 168- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 169 CPU. This needs to be enabled only for revision r0p0 of the CPU. 170 171- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 172 CPU. This needs to be enabled only for revision r0p0 of the CPU. 173 174- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 175 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 176 177- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 178 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 179 180- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 181 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 182 183- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 184 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 185 186- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 187 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 188 189- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 190 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 191 192- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 193 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 194 195- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 196 revisions of Cortex-A57 CPU. 197 198For Cortex-A72, the following errata build flags are defined : 199 200- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 201 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 202 203- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 204 revisions of Cortex-A72 CPU. 205 206For Cortex-A73, the following errata build flags are defined : 207 208- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 209 CPU. This needs to be enabled only for revision r0p0 of the CPU. 210 211- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 212 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 213 214For Cortex-A75, the following errata build flags are defined : 215 216- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 217 CPU. This needs to be enabled only for revision r0p0 of the CPU. 218 219- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 220 CPU. This needs to be enabled only for revision r0p0 of the CPU. 221 222For Cortex-A76, the following errata build flags are defined : 223 224- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 225 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 226 227- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 228 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 229 230- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 231 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 232 233- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 234 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 235 236- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 237 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 238 239- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 240 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 241 242- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 243 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 244 245- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 246 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 247 248- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 249 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 250 limitation of errata framework this errata is applied to all revisions 251 of Cortex-A76 CPU. 252 253- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 254 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 255 256- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 257 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 258 259For Cortex-A77, the following errata build flags are defined : 260 261- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 262 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 263 264- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 265 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 266 267- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 268 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 269 270- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 271 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 272 273- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 274 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 275 276For Cortex-A78, the following errata build flags are defined : 277 278- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 279 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 280 281- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 282 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 283 284- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 285 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 286 issue but there is no workaround for that revision. 287 288- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 289 CPU. This needs to be enabled for revisions r0p0 and r1p0. 290 291- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 292 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 293 294- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 295 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It 296 is still open. 297 298- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 299 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 300 is present in r0p0 but there is no workaround. It is still open. 301 302- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 303 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 304 it is still open. 305 306- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 307 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 308 it is still open. 309 310For Cortex-A78 AE, the following errata build flags are defined : 311 312- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 313 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 314 This erratum is still open. 315 316- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 317 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 318 erratum is still open. 319 320- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 321 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 322 erratum is still open. 323 324- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 325 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 326 erratum is still open. 327 328For Cortex-X1 CPU, the following errata build flags are defined: 329 330- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 331 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 332 333- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 334 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 335 336- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 337 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 338 339For Neoverse N1, the following errata build flags are defined : 340 341- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 342 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 343 344- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 345 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 346 347- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 348 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 349 350- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 351 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 352 353- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 354 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 355 356- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 357 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 358 359- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 360 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 361 362- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 363 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 364 365- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 366 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 367 368- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 369 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 370 371- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 372 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 373 374- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 375 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 376 377- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 378 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 379 revisions r0p0, r1p0, and r2p0 there is no workaround. 380 381For Neoverse V1, the following errata build flags are defined : 382 383- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 384 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 385 in r1p1. 386 387- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 388 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 389 in r1p1. 390 391- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 392 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 393 in r1p1. 394 395- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 396 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 397 398- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 399 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 400 CPU. 401 402- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 403 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 404 issue is present in r0p0 as well but there is no workaround for that 405 revision. It is still open. 406 407- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 408 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 409 CPU. It is still open. 410 411- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 412 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 413 It is still open. 414 415- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 416 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 417 issue is present in r0p0 as well but there is no workaround for that 418 revision. It is still open. 419 420- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 421 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 422 It is still open. 423 424For Cortex-A710, the following errata build flags are defined : 425 426- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 427 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 428 r2p0 of the CPU. It is still open. 429 430- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 431 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 432 r2p0 of the CPU. It is still open. 433 434- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 435 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 436 and is still open. 437 438- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 439 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 440 of the CPU and is still open. 441 442- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 443 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 444 is still open. 445 446- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to 447 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 448 of the CPU and is still open. 449 450- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 451 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 452 of the CPU and is fixed in r2p1. 453 454- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 455 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 456 of the CPU and is fixed in r2p1. 457 458- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 459 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 460 of the CPU and is fixed in r2p1. 461 462- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 463 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 464 of the CPU and is fixed in r2p1. 465 466For Neoverse N2, the following errata build flags are defined : 467 468- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 469 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open. 470 471- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 472 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 473 474- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 475 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 476 477- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 478 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 479 480- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 481 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 482 483- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 484 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 485 486- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 487 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 488 489- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 490 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 491 492- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 493 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 494 495- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 496 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 497 498For Cortex-X2, the following errata build flags are defined : 499 500- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 501 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 502 it is still open. 503 504- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 505 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 506 it is still open. 507 508- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 509 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open. 510 511- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to 512 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 513 r2p0 of the CPU, it is fixed in r2p1. 514 515- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to 516 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 517 r2p0 of the CPU, it is fixed in r2p1. 518 519- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to 520 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 521 r2p0 of the CPU, it is fixed in r2p1. 522 523- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to 524 Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU, 525 it is fixed in r2p1. 526 527For Cortex-A510, the following errata build flags are defined : 528 529- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to 530 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is 531 fixed in r0p1. 532 533- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 534 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 535 r0p2, r0p3 and r1p0, it is fixed in r1p1. 536 537- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 538 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 539 r0p2, it is fixed in r0p3. 540 541- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 542 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 543 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 544 workaround for those revisions. 545 546- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 547 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 548 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 549 ENABLE_MPMM=1. 550 551- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 552 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 553 r0p3 and r1p0, it is fixed in r1p1. 554 555- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 556 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 557 r0p3 and r1p0, it is fixed in r1p1. 558 559DSU Errata Workarounds 560---------------------- 561 562Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 563Shared Unit) errata. The DSU errata details can be found in the respective Arm 564documentation: 565 566- `Arm DSU Software Developers Errata Notice`_. 567 568Each erratum is identified by an ``ID``, as defined in the DSU errata notice 569document. Thus, the build flags which enable/disable the errata workarounds 570have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 571of DSU errata workarounds are similar to `CPU errata workarounds`_. 572 573For DSU errata, the following build flags are defined: 574 575- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 576 affected DSU configurations. This errata applies only for those DSUs that 577 revision is r0p0 (on r0p1 it is fixed). However, please note that this 578 workaround results in increased DSU power consumption on idle. 579 580- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 581 affected DSU configurations. This errata applies only for those DSUs that 582 contain the ACP interface **and** the DSU revision is older than r2p0 (on 583 r2p0 it is fixed). However, please note that this workaround results in 584 increased DSU power consumption on idle. 585 586- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 587 affected DSU configurations. This errata applies for those DSUs with 588 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 589 please note that this workaround results in increased DSU power consumption 590 on idle. 591 592CPU Specific optimizations 593-------------------------- 594 595This section describes some of the optimizations allowed by the CPU micro 596architecture that can be enabled by the platform as desired. 597 598- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 599 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 600 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 601 of the L2 by set/way flushes any dirty lines from the L1 as well. This 602 is a known safe deviation from the Cortex-A57 TRM defined power down 603 sequence. Each Cortex-A57 based platform must make its own decision on 604 whether to use the optimization. 605 606- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 607 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 608 in a way most programmers expect, and will most probably result in a 609 significant speed degradation to any code that employs them. The Armv8-A 610 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 611 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 612 flag enforces this behaviour. This needs to be enabled only for revisions 613 <= r0p3 of the CPU and is enabled by default. 614 615- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 616 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 617 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 618 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 619 `Cortex-A57 Software Optimization Guide`_. 620 621- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 622 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 623 this bit only if their memory system meets the requirement that cache 624 line fill requests from the Cortex-A57 processor are atomic. Each 625 Cortex-A57 based platform must make its own decision on whether to use 626 the optimization. This flag is disabled by default. 627 628- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 629 level cache(LLC) is present in the system, and that the DataSource field 630 on the master CHI interface indicates when data is returned from the LLC. 631 This is used to control how the LL_CACHE* PMU events count. 632 Default value is 0 (Disabled). 633 634-------------- 635 636*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.* 637 638.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 639.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 640.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 641.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 642.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 643.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 644.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 645.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 646