rpi3: add RPI3_USE_UEFI_MAP build option

The default Raspberry Pi 3 memory mapping for ATF is geared towards
the use of uboot + Linux. This creates issues when trying to use
ATF with an UEFI payload

rpi3: add RPI3_USE_UEFI_MAP build option

The default Raspberry Pi 3 memory mapping for ATF is geared towards
the use of uboot + Linux. This creates issues when trying to use
ATF with an UEFI payload and Windows on ARM64.

We therefore introduce new build option RPI3_USE_UEFI_MAP, that
enables the build process to use an alternate memory mapping that
is compatible with UEFI + Windows (as well as UEFI + Linux).

Fixes ARM-software/tf-issues#649

Signed-off-by: Pete Batard <pete@akeo.ie>

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rpi3: add RPI3_RUNTIME_UART build option

Some OSes (e.g. Ubuntu 18.04 LTS on Raspberry Pi 3) may disable the
runtime UART in a manner that prevents the system from rebooting if
ATF tries to send run

rpi3: add RPI3_RUNTIME_UART build option

Some OSes (e.g. Ubuntu 18.04 LTS on Raspberry Pi 3) may disable the
runtime UART in a manner that prevents the system from rebooting if
ATF tries to send runtime messages there.

Also, we don't want the firmware to share the UART with normal
world, as this can be a DoS attack vector into the secure world.

This patch fixes these 2 issues by introducing new build option
RPI3_RUNTIME_UART, that disables the runtime UART by default.

Fixes ARM-software/tf-issues#647

Signed-off-by: Pete Batard <pete@akeo.ie>

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arm64: versal: Add support for new Xilinx Versal ACAPs

Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Sc

arm64: versal: Add support for new Xilinx Versal ACAPs

Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.

This patch adds Virtual QEMU platform support for
this SoC "versal_virt".

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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Merge pull request #1649 from Yann-lms/stm32mp1_doc_update

docs: stm32mp1: complete compilation and flashing steps

docs: gxbb: Add documentation

Change-Id: Ie2465c1ccc482bd8eb5e5a71c580543095e4ba94
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

rpi3: Add mem reserve region to DTB if present

When a device tree blob is present at a known address, instead of, for
example, relying on the user modifying the Linux command line to warn
about the

rpi3: Add mem reserve region to DTB if present

When a device tree blob is present at a known address, instead of, for
example, relying on the user modifying the Linux command line to warn
about the memory reserved for the Trusted Firmware, pass it on the DTB.

The current code deletes the memory reserved for the default bootstrap
of the Raspberry Pi and adds the region used by the Trusted Firmware.

This system replaces the previous one consisting on adding
``memmap=16M$256M`` to the Linux command line. It's also meant to be
used by U-Boot and any other bootloader that understands DTB files.

Change-Id: I13ee528475fb043d6e8d9e9f24228e37ac3ac436
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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docs: stm32mp1: complete compilation and flashing steps

Add U-Boot compilation information.
Add a chapter about how to populate SD-card.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

rcar-gen3: initial commit for the rcar-gen3 boards

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author

rcar-gen3: initial commit for the rcar-gen3 boards

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date: Thu Aug 30 21:26:41 2018 +0900
Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
git@github.com:ARMmbed/mbedtls.git [devel]

Merge: 68dbc94 f34a4c1
Author: Simon Butcher <simon.butcher@arm.com>
Date: Thu Aug 30 00:57:28 2018 +0100

* optee_os:
https://github.com/BayLibre/optee_os

Until it gets merged into OP-TEE, the port requires Renesas' Trusted
Environment with a modification to support power management.

Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
Date: Thu Aug 30 16:49:49 2018 +0200
plat-rcar: cpu-suspend: handle the power level
Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
The port has beent tested using mainline uboot.

Author: Fabio Estevam <festevam@gmail.com>
Date: Tue Sep 4 10:23:12 2018 -0300

*linux:
The port has beent tested using mainline kernel.

Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Sep 16 11:52:37 2018 -0700
Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----

* cpuidle
-------
enable kernel's cpuidle arm_idle driver and boot

* system suspend
--------------
$ cat suspend.sh
#!/bin/bash
i2cset -f -y 7 0x30 0x20 0x0F
read -p "Switch off SW23 and press return " foo
echo mem > /sys/power/state

* cpu hotplug:
------------
$ cat offline.sh
#!/bin/bash
nbr=$1
echo 0 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

$ cat online.sh
#!/bin/bash
nbr=$1
echo 1 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

Signed-off-by: ldts <jramirez@baylibre.com>

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zynqmp: Migrate to new interfaces

- Remove references to removed build options.
- Migrate to bl31_early_platform_setup2().

Change-Id: Ibeb8982a0a841f55ce778c4f09f06b72b47b21d8
Tested-by: Siva Durga

zynqmp: Migrate to new interfaces

- Remove references to removed build options.
- Migrate to bl31_early_platform_setup2().

Change-Id: Ibeb8982a0a841f55ce778c4f09f06b72b47b21d8
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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docs: warp7: Add description for the i.MX7 WaRP7 platform

This patch describes the boot-flow and building of the WaRP7 TF-A port.
What it describes is booting and unsigned TF-A.

A very brief sectio

docs: warp7: Add description for the i.MX7 WaRP7 platform

This patch describes the boot-flow and building of the WaRP7 TF-A port.
What it describes is booting and unsigned TF-A.

A very brief section has been added on signing BL2 which is in no-way
comprehensive. For a comprehensive description of the signing process try
the Boundary Devices blog on the matter.

https://boundarydevices.com/high-assurance-boot-hab-dummies/

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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stm32mp1: Add platform documentation

Signed-off-by: Yann Gautier <yann.gautier@st.com>

rpi3: Move NS-DRAM out of the protected region

The Non-secure DRAM region shouldn't be protected in the range specified
in the Linux command line with memmap.

This change also increases the size of

rpi3: Move NS-DRAM out of the protected region

The Non-secure DRAM region shouldn't be protected in the range specified
in the Linux command line with memmap.

This change also increases the size of the Secure DRAM region.

Change-Id: I306e9e443a84b834c99739f54a534a3ca3be2424
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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rpi3: Switch addresses of kernel and DTB

In the memory map of the documentation the kernel only had 16MiB of
allocated space. This leaves very little room for growth, so the
addresses of the DTB and

rpi3: Switch addresses of kernel and DTB

In the memory map of the documentation the kernel only had 16MiB of
allocated space. This leaves very little room for growth, so the
addresses of the DTB and the kernel have been interchanged.

The documentation has been updated to reflect this change.

Change-Id: Ib6eab69f047fa88561fb755397ce3a0b356c8860
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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rpi3: Update documentation

Add information about direct Linux kernel boot for kernels that support
PSCI.

Change-Id: I05f76aa36398edabf411cb25a646437af1862e6e
Signed-off-by: Antonio Nino Diaz <anton

rpi3: Update documentation

Add information about direct Linux kernel boot for kernels that support
PSCI.

Change-Id: I05f76aa36398edabf411cb25a646437af1862e6e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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rpi3: Add support for the stack protector

It uses the hardware RNG in a similar way as Juno (it gets 128 bits of
entropy and does xor on them).

It is disabled by default.

Change-Id: I8b3adb61f5a56

rpi3: Add support for the stack protector

It uses the hardware RNG in a similar way as Juno (it gets 128 bits of
entropy and does xor on them).

It is disabled by default.

Change-Id: I8b3adb61f5a5623716e0e8b6799404c68dd94c60
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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rpi3: Remove broken support of RESET_TO_BL31

There is no way to boot BL31 at the addresses specified in the platform
memory map unless an extra loader is used at address 0x00000000. It is
better to

rpi3: Remove broken support of RESET_TO_BL31

There is no way to boot BL31 at the addresses specified in the platform
memory map unless an extra loader is used at address 0x00000000. It is
better to remove it to prevent confusion. Having it enabled was a bug.

Change-Id: I3229fbc080f5996cff47efce8e799bae94e0d5cb
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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rpi3: Concatenate BL1 and FIP automatically

Add a new default makefile target to concatenate BL1 and the FIP and
generate armstub8.bin. This way it isn't needed to do it manually.

Documentation upd

rpi3: Concatenate BL1 and FIP automatically

Add a new default makefile target to concatenate BL1 and the FIP and
generate armstub8.bin. This way it isn't needed to do it manually.

Documentation updated to reflect the changes.

Change-Id: Id5b5b1b7b9f87767db63fd01180ddfea855a7207
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1476 from grandpaul/paulliu-rpi3-modify-size

rpi3: enlarge SEC_DRAM0_SIZE for optee_test to pass

rpi3: enlarge SEC_DRAM0_SIZE for optee_test to pass

Running optee_test failed because SEC_DRAM0_SIZE is too small. Previous
is 2 MB. We enlarge it to 11 MB for passing the test. Also we reduce
the N

rpi3: enlarge SEC_DRAM0_SIZE for optee_test to pass

Running optee_test failed because SEC_DRAM0_SIZE is too small. Previous
is 2 MB. We enlarge it to 11 MB for passing the test. Also we reduce
the NS_DRAM0_SIZE from 13MB to 4MB so that the whole section is still
fit in 16MB.

This commit also modified the document to reflect the changes we've
made in code.

Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>

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rpi3: Implement simple interrupt routing

Implement minimal interrupt routing functions. All interrupts are
treated as non-secure interrupts to be handled by the non-secure world.

Add note to the do

rpi3: Implement simple interrupt routing

Implement minimal interrupt routing functions. All interrupts are
treated as non-secure interrupts to be handled by the non-secure world.

Add note to the documentation about disabling FIQs qhen using OP-TEE
with Linux.

Change-Id: I937096542d973925e43ae946c5d0b306d0d95a94
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1463 from grandpaul/paulliu-rpi3-tbb0

rpi3: Add support for Trusted Board Boot

docs: rpi3: add description for Trusted Board Boot

Add paragraph for how to enable Trusted Board Boot for rpi3

Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (

docs: rpi3: add description for Trusted Board Boot

Add paragraph for how to enable Trusted Board Boot for rpi3

Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>

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docs: rpi3: fix the size of BL1

For Trusted Board Boot we enlarge the BL1 size from 64k to 128k.

Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul

docs: rpi3: fix the size of BL1

For Trusted Board Boot we enlarge the BL1 size from 64k to 128k.

Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>

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allwinner: Add Allwinner H6 SoC support

The H6 is Allwinner's most recent SoC. It shares most peripherals with the
other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
map.

In

allwinner: Add Allwinner H6 SoC support

The H6 is Allwinner's most recent SoC. It shares most peripherals with the
other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
map.

Introduce a separate platform target, which includes a different header
file to cater for the address differences. Also add the new build target
to the documentation.

The new ATF platform name is "sun50i_h6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: doc: add missing paragraphs

Add two empty lines to denote the paragraphs properly and improve
readability.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara

allwinner: doc: add missing paragraphs

Add two empty lines to denote the paragraphs properly and improve
readability.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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