1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <assert.h> 9 #include <console.h> 10 #include <debug.h> 11 #include <generic_delay_timer.h> 12 #include <gicv2.h> 13 #include <libfdt.h> 14 #include <mmio.h> 15 #include <platform.h> 16 #include <platform_def.h> 17 #include <sunxi_def.h> 18 #include <sunxi_mmap.h> 19 #include <sunxi_private.h> 20 #include <uart_16550.h> 21 22 23 static entry_point_info_t bl32_image_ep_info; 24 static entry_point_info_t bl33_image_ep_info; 25 26 static console_16550_t console; 27 28 static const gicv2_driver_data_t sunxi_gic_data = { 29 .gicd_base = SUNXI_GICD_BASE, 30 .gicc_base = SUNXI_GICC_BASE, 31 }; 32 33 /* 34 * Try to find a DTB loaded in memory by previous stages. 35 * 36 * At the moment we implement a heuristic to find the DTB attached to U-Boot: 37 * U-Boot appends its DTB to the end of the image. Assuming that BL33 is 38 * U-Boot, try to find the size of the U-Boot image to learn the DTB address. 39 * The generic ARMv8 U-Boot image contains the load address and its size 40 * as u64 variables at the beginning of the image. There might be padding 41 * or other headers before that data, so scan the first 2KB after the BL33 42 * entry point to find the load address, which should be followed by the 43 * size. Adding those together gives us the address of the DTB. 44 */ 45 static void *sunxi_find_dtb(void) 46 { 47 uint64_t *u_boot_base; 48 int i; 49 50 u_boot_base = (void *)(SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE); 51 52 for (i = 0; i < 2048 / sizeof(uint64_t); i++) { 53 uint32_t *dtb_base; 54 55 if (u_boot_base[i] != PLAT_SUNXI_NS_IMAGE_OFFSET) 56 continue; 57 58 /* Does the suspected U-Boot size look anyhow reasonable? */ 59 if (u_boot_base[i + 1] >= 256 * 1024 * 1024) 60 continue; 61 62 /* end of the image: base address + size */ 63 dtb_base = (void *)((char *)u_boot_base + u_boot_base[i + 1]); 64 65 if (fdt_check_header(dtb_base) != 0) 66 continue; 67 68 return dtb_base; 69 } 70 71 return NULL; 72 } 73 74 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 75 u_register_t arg2, u_register_t arg3) 76 { 77 /* Initialize the debug console as soon as possible */ 78 console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ, 79 SUNXI_UART0_BAUDRATE, &console); 80 81 #ifdef BL32_BASE 82 /* Populate entry point information for BL32 */ 83 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 84 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 85 bl32_image_ep_info.pc = BL32_BASE; 86 #endif 87 88 /* Populate entry point information for BL33 */ 89 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 90 /* 91 * Tell BL31 where the non-trusted software image 92 * is located and the entry state information 93 */ 94 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 95 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 96 DISABLE_ALL_EXCEPTIONS); 97 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 98 99 /* Turn off all secondary CPUs */ 100 sunxi_disable_secondary_cpus(plat_my_core_pos()); 101 } 102 103 void bl31_plat_arch_setup(void) 104 { 105 sunxi_configure_mmu_el3(0); 106 } 107 108 void bl31_platform_setup(void) 109 { 110 const char *soc_name; 111 uint16_t soc_id = sunxi_read_soc_id(); 112 void *fdt; 113 114 switch (soc_id) { 115 case SUNXI_SOC_A64: 116 soc_name = "A64/H64/R18"; 117 break; 118 case SUNXI_SOC_H5: 119 soc_name = "H5"; 120 break; 121 case SUNXI_SOC_H6: 122 soc_name = "H6"; 123 break; 124 default: 125 soc_name = "unknown"; 126 break; 127 } 128 NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id); 129 130 generic_delay_timer_init(); 131 132 fdt = sunxi_find_dtb(); 133 if (fdt) { 134 const char *model; 135 int length; 136 137 model = fdt_getprop(fdt, 0, "model", &length); 138 NOTICE("BL31: Found U-Boot DTB at %p, model: %s\n", fdt, 139 model ?: "unknown"); 140 } else { 141 NOTICE("BL31: No DTB found.\n"); 142 } 143 144 /* Configure the interrupt controller */ 145 gicv2_driver_init(&sunxi_gic_data); 146 gicv2_distif_init(); 147 gicv2_pcpu_distif_init(); 148 gicv2_cpuif_enable(); 149 150 sunxi_security_setup(); 151 152 /* 153 * On the A64 U-Boot's SPL sets the bus clocks to some conservative 154 * values, to work around FEL mode instabilities with SRAM C accesses. 155 * FEL mode is gone when we reach ATF, so bring the AHB1 bus 156 * (the "main" bus) clock frequency back to the recommended 200MHz, 157 * for improved performance. 158 */ 159 if (soc_id == SUNXI_SOC_A64) 160 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180); 161 162 /* 163 * U-Boot or the kernel don't setup AHB2, which leaves it at the 164 * AHB1 frequency (200 MHz, see above). However Allwinner recommends 165 * 300 MHz, for improved Ethernet and USB performance. Switch the 166 * clock to use "PLL_PERIPH0 / 2". 167 */ 168 if (soc_id == SUNXI_SOC_A64 || soc_id == SUNXI_SOC_H5) 169 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0x1); 170 171 sunxi_pmic_setup(soc_id, fdt); 172 173 INFO("BL31: Platform setup done\n"); 174 } 175 176 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 177 { 178 assert(sec_state_is_valid(type) != 0); 179 180 if (type == NON_SECURE) 181 return &bl33_image_ep_info; 182 183 if ((type == SECURE) && bl32_image_ep_info.pc) 184 return &bl32_image_ep_info; 185 186 return NULL; 187 } 188