Merge changes from topic "deprecate-t210-t186" into integration

* changes:
refactor(tegra): deprecate tegra186 platform
refactor(tegra): deprecate tegra210 platform

Merge changes from topics "xlnx_versal_ipi_build", "xlnx_versalnet_ipi_build" into integration

* changes:
feat(versal-net): add build macro support for IPI_ID_APU
feat(versal): add build macro s

Merge changes from topics "xlnx_versal_ipi_build", "xlnx_versalnet_ipi_build" into integration

* changes:
feat(versal-net): add build macro support for IPI_ID_APU
feat(versal): add build macro support for IPI_ID_APU

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refactor(tegra): deprecate tegra186 platform

The Tegra186 platform has reached EOL. The formal announcement is at
https://forums.developer.nvidia.com/t/upstream-tf-a-mmu-issues-on-tegra186/350096.

refactor(tegra): deprecate tegra186 platform

The Tegra186 platform has reached EOL. The formal announcement is at
https://forums.developer.nvidia.com/t/upstream-tf-a-mmu-issues-on-tegra186/350096.

This patch removes the support for this platform as a
result.

Reported-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iec4668c3bd34000bbc2da685d0be4a4e06cf05d0

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refactor(tegra): deprecate tegra210 platform

The Tegra210 platform has reached EOL. The formal announcement is at
https://forums.developer.nvidia.com/t/upstream-tf-a-fails-to-boot-on-tegra210/350094

refactor(tegra): deprecate tegra210 platform

The Tegra210 platform has reached EOL. The formal announcement is at
https://forums.developer.nvidia.com/t/upstream-tf-a-fails-to-boot-on-tegra210/350094.

This patch removes the support for this platform as a result.

Reported-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Id894f892ade438b5e15a6fcb05509691ef2257d8

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feat(versal-net): add build macro support for IPI_ID_APU

Add build-time macro support for PLAT_IPI_ID_APU to allow
the APU IPI channel to be explicitly selected at build time,
as per the design. Thi

feat(versal-net): add build macro support for IPI_ID_APU

Add build-time macro support for PLAT_IPI_ID_APU to allow
the APU IPI channel to be explicitly selected at build time,
as per the design. This change aligns PLAT_IPI_ID_APU handling
with existing IPI ID macros, enabling platforms to define the
APU IPI ID via a build flag instead of hardcoding it in platform
code. This improves configurability and consistency across
platform.

Change-Id: I9b2be16a73cc1c6dcf273c2531af8aaf01695cd1
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option perfor

feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.

Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.

For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192

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feat(k3low): introduce Cadence LPDDR4 core driver for AM62L

AM62L devices support 16-bit DDR4/LPDDR4 DRAM memory devices. The core
DDR4/LPDDR4 driver was developed by Cadence. This patch introduces

feat(k3low): introduce Cadence LPDDR4 core driver for AM62L

AM62L devices support 16-bit DDR4/LPDDR4 DRAM memory devices. The core
DDR4/LPDDR4 driver was developed by Cadence. This patch introduces the
Cadence IP driver files (lpddr4.c, lpddr4_16bit.c, lpddr4_obj_if.c and
their associated headers) which carry dual copyright (Cadence + TI).

The driver was pruned from ~6800 macros to ~80 with AI-assisted removal
of unused code; the Cadence CTL/PHY/PI API surface remains intact for
review against the User Guides.

These files are intentionally unreferenced in platform.mk pending the
AM62L platform shim in the next patch.

For additional information please check the technical reference
manual at:
https://www.ti.com/lit/pdf/sprujb4

Change-Id: I8b02a6b30e5ea7b1b457cc0a933d8ef232993fa1
Co-developed-by: Claude <noreply@anthropic.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>

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feat(versal): add build macro support for IPI_ID_APU

Add build-time macro support for PLAT_IPI_ID_APU to
allow the APU IPI channel to be explicitly selected
at build time, as per the design. This ch

feat(versal): add build macro support for IPI_ID_APU

Add build-time macro support for PLAT_IPI_ID_APU to
allow the APU IPI channel to be explicitly selected
at build time, as per the design. This change aligns
PLAT_IPI_ID_APU handling with existing IPI ID macros,
enabling platforms to define the APU IPI ID via a build
flag instead of hardcoding it in platform code. This
improves configurability and consistency across platform.

Change-Id: I32a978a1abf8e8d993742cfd1253cfe4a44fd113
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge "fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID" into integration

Merge "docs(morello): update information regarding capability arch support" into integration

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch m

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.

The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.

This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.

Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "qti_lemans_evk" into integration

* changes:
docs(qti): add lemans_evk platform documentation
fix(qti): don't panic() without QTISECLIB
feat(lemans): add support for l

Merge changes from topic "qti_lemans_evk" into integration

* changes:
docs(qti): add lemans_evk platform documentation
fix(qti): don't panic() without QTISECLIB
feat(lemans): add support for lemans EVK platform
feat(qti): add support for Lemans SoC

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docs(qti): add lemans_evk platform documentation

Add documentation for lemans_evk platform listing down step to
build, flash and boot up the platform with TF-A BL2 and BL31
support. Currently the QT

docs(qti): add lemans_evk platform documentation

Add documentation for lemans_evk platform listing down step to
build, flash and boot up the platform with TF-A BL2 and BL31
support. Currently the QTISECLIB port is work under progress,
hence the boot only progresses upto OP-TEE OS.

Change-Id: I9c01286511f7ee5ec4b758efe9068fd43858e5c5
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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docs(morello): update information regarding capability arch support

Update the information as per the lastest upstream code.

Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: I450f7

docs(morello): update information regarding capability arch support

Update the information as per the lastest upstream code.

Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: I450f7a1600b88aacfd44950180c520aa45a19228

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Merge "refactor(nxp): add NXP_TBBR_USE_X509 switch for TBBR flow selection" into integration

refactor(nxp): add NXP_TBBR_USE_X509 switch for TBBR flow selection

Introduce NXP_TBBR_USE_X509 (default 0) to select X.509/mbedTLS
versus CSF header flows, and update fuse_fip and ddr_fip gating
to

refactor(nxp): add NXP_TBBR_USE_X509 switch for TBBR flow selection

Introduce NXP_TBBR_USE_X509 (default 0) to select X.509/mbedTLS
versus CSF header flows, and update fuse_fip and ddr_fip gating
to use this flag instead of MBEDTLS_DIR.

Change-Id: Ifabf6bbb4a05f57b060e9af3c9ae6b29b8864280
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(fvp): update FVP versions used

Update FVP version used to 11.31.28

Change-Id: Ifb2c09f1335b12ff20a32bbc62e0589c49f623bb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge changes Iad777e77,I0eb24083 into integration

* changes:
feat(build): add Mbed TLS submodule
fix(brcm): fix bad Mbed TLS check

Merge "feat(rza): add initial BL2 support for RZ/A platforms" into integration

Merge changes from topic "a80x0_nbx-platform-v1" into integration

* changes:
fix(marvell): work around uutils coreutils truncate -s %SIZE bug
fix(a8k): add XFI params for NBX SFI 10G
fix(a8k):

Merge changes from topic "a80x0_nbx-platform-v1" into integration

* changes:
fix(marvell): work around uutils coreutils truncate -s %SIZE bug
fix(a8k): add XFI params for NBX SFI 10G
fix(a8k): mv_ddr path may not be a git repo
feat(a8k): add a80x0_nbx Free Mobile board
feat(a8k): add user callback for skip_image

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feat(rza): add initial BL2 support for RZ/A platforms

This patch introduces the initial BL2 support for Renesas RZ/A
platforms. It adds platform-specific sources, drivers, build files,
and memory co

feat(rza): add initial BL2 support for RZ/A platforms

This patch introduces the initial BL2 support for Renesas RZ/A
platforms. It adds platform-specific sources, drivers, build files,
and memory configuration needed to boot via BL2.

Key changes include:
- Board-specific makefiles for RZ/A3M board.
- Platform helpers and BL2 setup routines.
- Drivers for DDR, GPIO, and CPG drivers.
- Platform headers, register definitions, and configuration files.
- Scripts and makefiles for image generation.

Change-Id: I6cea17a76633998d746e7c7c429da9a5bd09ef0c
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

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feat(build): add Mbed TLS submodule

This change adds Mbed TLS 3.6.5 as a submodule to the TF-A repository.
It is no longer a requirement to pass `MBEDTLS_DIR` to the build system
when building confi

feat(build): add Mbed TLS submodule

This change adds Mbed TLS 3.6.5 as a submodule to the TF-A repository.
It is no longer a requirement to pass `MBEDTLS_DIR` to the build system
when building configurations which require it, as the build system will
now look inside the `contrib` directory if the parameter is missing.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: Mbed TLS is now included in the TF-A repository, and it
is no longer a requirement to pass `MBEDTLS_DIR` to the build system.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: Iad777e77936d1c373065f17fe5c4aadc45e56b64
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(s32g274ardb): document DDR integration

Document the integration of DDR driver into
the boot process. Document the relocation
of BL31 and BL33 to DDR instead of SRAM.

Additionally, include the

feat(s32g274ardb): document DDR integration

Document the integration of DDR driver into
the boot process. Document the relocation
of BL31 and BL33 to DDR instead of SRAM.

Additionally, include the new build parameter
`DDR_FW_BIN_PATH` which must be provided to
specify the path to the DDR firmware binary.
This firmware is used by the DDR driver to
configure and initialize DDR memory.

Change-Id: Ib9fa850926d3dcd745a93eb4aa44846bbdf3e9d3
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(a8k): add a80x0_nbx Free Mobile board

Add TF-A platform support for the a80x0_nbx board (Free Mobile
Nodebox10G), a network appliance based on the Marvell Armada 8040
SoC with dual CP110 compan

feat(a8k): add a80x0_nbx Free Mobile board

Add TF-A platform support for the a80x0_nbx board (Free Mobile
Nodebox10G), a network appliance based on the Marvell Armada 8040
SoC with dual CP110 companion processors.

Hardware configuration:
- Quad-core ARM Cortex-A72 @ 1.3GHz
- DDR4 memory with ECC support (single channel, 32-bit)
- Dual CP110 companion processors (CP0 and CP1)
- SGMII 1G Ethernet on CP0 lane 5
- I2C buses for peripheral access (CP0: 100kHz, CP1: 400kHz)
- NS16550 UART console at 115200 baud
- eMMC boot via Xenon SDHCI controller

Key features implemented:

1. Ramoops buffer preservation across cold boot (ramoopsies driver)
On ECC-enabled DDR configurations, the memory controller must
scrub all memory during initialization to establish valid parity
bits. This would normally destroy the Linux kernel ramoops buffer
containing crash logs from the previous boot. The ramoopsies
driver intercepts the DDR scrubbing function using the GNU linker
--wrap feature, saving the 32KB ramoops buffer (at 0x3FFF8000) to
SRAM before scrubbing and restoring it afterward. The driver also
handles pending SError exceptions that occur when reading
uninitialized ECC memory by installing a minimal exception vector
that acknowledges and clears them.

2. UART-based skip image recovery mechanism
The platform uses the USER_DEFINED skip image detection callback
to implement software-based boot recovery without requiring a
dedicated GPIO button. Users can trigger recovery mode by holding
the 's' key during early boot, causing the bootloader to load
from the secondary/recovery image instead of the primary firmware.

3. SerDes/ComPhy configuration
PHY porting layer configured with default tuning values for
XFI (10G) and SATA interfaces, following the principle of minimal
bootloader configuration. Advanced SerDes tuning is deferred to
the Linux kernel where it can be more easily adjusted.

The implementation includes comprehensive documentation and a build
verification script to validate proper symbol exports, DDR driver
integration, and flash image format compliance.

Based on original work by Nicolas Schichan <nschichan@freebox.fr>
for the ramoops preservation mechanism and USER_DEFINED skip image
detection concept.

Change-Id: Iaacbb29631f27b47fbf5cc300d8c63aaf1e89e51
Signed-off-by: Vincent Jardin <vjardin@free.fr>

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feat(stm32mp1): make stpmic2 usable for STM32MP1

Update STPMIC2 driver to use it on STM32MP1 especially
STM32MP_STPMIC1L.

Change-Id: I0db727a093a6a85dca7a74be280c0d1af0e54417
Signed-off-by: Pascal

feat(stm32mp1): make stpmic2 usable for STM32MP1

Update STPMIC2 driver to use it on STM32MP1 especially
STM32MP_STPMIC1L.

Change-Id: I0db727a093a6a85dca7a74be280c0d1af0e54417
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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