1 /* 2 * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /* Extracts the CPU part number from MIDR for checking CPU match */ 28 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 29 30 /******************************************************************************* 31 * MPIDR macros 32 ******************************************************************************/ 33 #define MPIDR_MT_MASK (ULL(1) << 24) 34 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 35 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 36 #define MPIDR_AFFINITY_BITS U(8) 37 #define MPIDR_AFFLVL_MASK ULL(0xff) 38 #define MPIDR_AFF0_SHIFT U(0) 39 #define MPIDR_AFF1_SHIFT U(8) 40 #define MPIDR_AFF2_SHIFT U(16) 41 #define MPIDR_AFF3_SHIFT U(32) 42 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 44 #define MPIDR_AFFLVL_SHIFT U(3) 45 #define MPIDR_AFFLVL0 ULL(0x0) 46 #define MPIDR_AFFLVL1 ULL(0x1) 47 #define MPIDR_AFFLVL2 ULL(0x2) 48 #define MPIDR_AFFLVL3 ULL(0x3) 49 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 50 #define MPIDR_AFFLVL0_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL1_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 54 #define MPIDR_AFFLVL2_VAL(mpidr) \ 55 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 56 #define MPIDR_AFFLVL3_VAL(mpidr) \ 57 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 58 /* 59 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 60 * add one while using this macro to define array sizes. 61 * TODO: Support only the first 3 affinity levels for now. 62 */ 63 #define MPIDR_MAX_AFFLVL U(2) 64 65 #define MPID_MASK (MPIDR_MT_MASK | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 67 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 68 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 69 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 70 71 #define MPIDR_AFF_ID(mpid, n) \ 72 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 73 74 /* 75 * An invalid MPID. This value can be used by functions that return an MPID to 76 * indicate an error. 77 */ 78 #define INVALID_MPID U(0xFFFFFFFF) 79 80 /******************************************************************************* 81 * Definitions for Exception vector offsets 82 ******************************************************************************/ 83 #define CURRENT_EL_SP0 0x0 84 #define CURRENT_EL_SPX 0x200 85 #define LOWER_EL_AARCH64 0x400 86 #define LOWER_EL_AARCH32 0x600 87 88 #define SYNC_EXCEPTION 0x0 89 #define IRQ_EXCEPTION 0x80 90 #define FIQ_EXCEPTION 0x100 91 #define SERROR_EXCEPTION 0x180 92 93 /******************************************************************************* 94 * Encodings for GICv5 EL3 system registers 95 ******************************************************************************/ 96 #define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4 97 #define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5 98 #define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6 99 #define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7 100 101 #define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3) 102 #define ICC_PPI_DOMAINR_COUNT (32) 103 104 /******************************************************************************* 105 * Definitions for CPU system register interface to GICv3 106 ******************************************************************************/ 107 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 108 #define ICC_SGI1R S3_0_C12_C11_5 109 #define ICC_ASGI1R S3_0_C12_C11_6 110 #define ICC_SRE_EL1 S3_0_C12_C12_5 111 #define ICC_SRE_EL2 S3_4_C12_C9_5 112 #define ICC_SRE_EL3 S3_6_C12_C12_5 113 #define ICC_CTLR_EL1 S3_0_C12_C12_4 114 #define ICC_CTLR_EL3 S3_6_C12_C12_4 115 #define ICC_PMR_EL1 S3_0_C4_C6_0 116 #define ICC_RPR_EL1 S3_0_C12_C11_3 117 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 118 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 119 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 120 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 121 #define ICC_IAR0_EL1 S3_0_c12_c8_0 122 #define ICC_IAR1_EL1 S3_0_c12_c12_0 123 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 124 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 125 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 126 127 /******************************************************************************* 128 * Definitions for EL2 system registers for save/restore routine 129 ******************************************************************************/ 130 #define CNTPOFF_EL2 S3_4_C14_C0_6 131 #define HDFGRTR2_EL2 S3_4_C3_C1_0 132 #define HDFGWTR2_EL2 S3_4_C3_C1_1 133 #define HFGRTR2_EL2 S3_4_C3_C1_2 134 #define HFGWTR2_EL2 S3_4_C3_C1_3 135 #define HDFGRTR_EL2 S3_4_C3_C1_4 136 #define HDFGWTR_EL2 S3_4_C3_C1_5 137 #define HAFGRTR_EL2 S3_4_C3_C1_6 138 #define HFGITR2_EL2 S3_4_C3_C1_7 139 #define HFGITR_EL2 S3_4_C1_C1_6 140 #define HFGRTR_EL2 S3_4_C1_C1_4 141 #define HFGWTR_EL2 S3_4_C1_C1_5 142 #define ICH_HCR_EL2 S3_4_C12_C11_0 143 #define ICH_VMCR_EL2 S3_4_C12_C11_7 144 #define MPAMVPM0_EL2 S3_4_C10_C6_0 145 #define MPAMVPM1_EL2 S3_4_C10_C6_1 146 #define MPAMVPM2_EL2 S3_4_C10_C6_2 147 #define MPAMVPM3_EL2 S3_4_C10_C6_3 148 #define MPAMVPM4_EL2 S3_4_C10_C6_4 149 #define MPAMVPM5_EL2 S3_4_C10_C6_5 150 #define MPAMVPM6_EL2 S3_4_C10_C6_6 151 #define MPAMVPM7_EL2 S3_4_C10_C6_7 152 #define MPAMVPMV_EL2 S3_4_C10_C4_1 153 #define VNCR_EL2 S3_4_C2_C2_0 154 #define PMSCR_EL2 S3_4_C9_C9_0 155 #define TFSR_EL2 S3_4_C5_C6_0 156 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 157 #define TTBR1_EL2 S3_4_C2_C0_1 158 159 #define HAFGRTR_EL2_INIT_VAL ULL(0) 160 161 /******************************************************************************* 162 * Generic timer memory mapped registers & offsets 163 ******************************************************************************/ 164 #define CNTCR_OFF U(0x000) 165 #define CNTCV_OFF U(0x008) 166 #define CNTFID_OFF U(0x020) 167 168 #define CNTCR_EN (U(1) << 0) 169 #define CNTCR_HDBG (U(1) << 1) 170 #define CNTCR_FCREQ(x) ((x) << 8) 171 172 /******************************************************************************* 173 * System register bit definitions 174 ******************************************************************************/ 175 /* CLIDR definitions */ 176 #define LOUIS_SHIFT U(21) 177 #define LOC_SHIFT U(24) 178 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 179 #define CLIDR_FIELD_WIDTH U(3) 180 181 /* CSSELR definitions */ 182 #define LEVEL_SHIFT U(1) 183 184 /* Data cache set/way op type defines */ 185 #define DCISW U(0x0) 186 #define DCCISW U(0x1) 187 #if ERRATA_A53_827319 188 #define DCCSW DCCISW 189 #else 190 #define DCCSW U(0x2) 191 #endif 192 193 #define ID_REG_FIELD_MASK ULL(0xf) 194 195 /******************************************************************************* 196 * PFR0_EL1 - Definitions for AArch32 Processor Feature Register 0 197 ******************************************************************************/ 198 #define ID_PFR0_EL1 S3_0_C0_C1_0 199 200 /******************************************************************************* 201 * PFR2_EL1 - Definitions for AArch32 Processor Feature Register 2 202 ******************************************************************************/ 203 #define ID_PFR2_EL1 S3_0_C0_C3_4 204 205 /******************************************************************************* 206 * ID_ISAR6_EL1 - Definition for AArch32 Instruction Set Attribute Register 6 207 ******************************************************************************/ 208 #define ID_ISAR6_EL1 S3_0_C0_C2_7 209 210 /******************************************************************************* 211 * ID_DFR1_EL1 - Definition for AArch32 Debug Feature Register 1 212 ******************************************************************************/ 213 #define ID_DFR1_EL1 S3_0_C0_C3_5 214 215 /* ID_AA64PFR0_EL1 definitions */ 216 #define ID_AA64PFR0_EL0_SHIFT U(0) 217 #define ID_AA64PFR0_EL1_SHIFT U(4) 218 #define ID_AA64PFR0_EL2_SHIFT U(8) 219 #define ID_AA64PFR0_EL3_SHIFT U(12) 220 221 #define ID_AA64PFR0_AMU_SHIFT U(44) 222 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 223 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 224 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 225 226 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 227 #define ID_AA64PFR0_EL0_MASK ID_AA64PFR0_ELX_MASK 228 #define ID_AA64PFR0_EL1_MASK ID_AA64PFR0_ELX_MASK 229 #define ID_AA64PFR0_EL2_MASK ID_AA64PFR0_ELX_MASK 230 #define ID_AA64PFR0_EL3_MASK ID_AA64PFR0_ELX_MASK 231 232 #define ID_AA64PFR0_GIC_SHIFT U(24) 233 #define ID_AA64PFR0_GIC_WIDTH U(4) 234 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 235 236 #define ID_AA64PFR0_SVE_SHIFT U(32) 237 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 238 #define ID_AA64PFR0_SVE_LENGTH U(4) 239 #define SVE_IMPLEMENTED ULL(0x1) 240 241 #define ID_AA64PFR0_SEL2_SHIFT U(36) 242 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 243 244 #define ID_AA64PFR0_MPAM_SHIFT U(40) 245 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 246 247 #define ID_AA64PFR0_DIT_SHIFT U(48) 248 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 249 #define ID_AA64PFR0_DIT_LENGTH U(4) 250 #define DIT_IMPLEMENTED ULL(1) 251 252 #define ID_AA64PFR0_CSV2_SHIFT U(56) 253 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 254 #define ID_AA64PFR0_CSV2_LENGTH U(4) 255 #define CSV2_2_IMPLEMENTED ULL(0x2) 256 #define CSV2_3_IMPLEMENTED ULL(0x3) 257 258 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 259 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 260 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 261 #define RME_NOT_IMPLEMENTED ULL(0) 262 #define RME_GPC2_IMPLEMENTED ULL(0x2) 263 264 #define ID_AA64PFR0_RAS_SHIFT U(28) 265 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 266 #define ID_AA64PFR0_RAS_LENGTH U(4) 267 268 /* Exception level handling */ 269 #define EL_IMPL_NONE ULL(0) 270 #define EL_IMPL_A64ONLY ULL(1) 271 #define EL_IMPL_A64_A32 ULL(2) 272 273 /* ID_AA64DFR0_EL1.DebugVer definitions */ 274 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 275 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 276 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 277 278 /* ID_AA64DFR0_EL1.TraceVer definitions */ 279 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 280 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 281 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 282 283 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 284 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 285 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 286 #define TRACEFILT_IMPLEMENTED ULL(1) 287 288 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 289 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 290 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 291 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 292 #define ID_AA64DFR0_PMUVER_PMUV3P9 U(9) 293 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 294 295 /* ID_AA64DFR0_EL1.SEBEP definitions */ 296 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 297 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 298 #define SEBEP_IMPLEMENTED ULL(1) 299 300 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 301 #define ID_AA64DFR0_PMS_SHIFT U(32) 302 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 303 #define SPE_IMPLEMENTED ULL(0x1) 304 #define SPE_NOT_IMPLEMENTED ULL(0x0) 305 306 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 307 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 308 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 309 #define TRACEBUFFER_IMPLEMENTED ULL(1) 310 311 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 312 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 313 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 314 #define MTPMU_IMPLEMENTED ULL(1) 315 #define MTPMU_NOT_IMPLEMENTED ULL(15) 316 317 /* ID_AA64DFR0_EL1.BRBE definitions */ 318 #define ID_AA64DFR0_BRBE_SHIFT U(52) 319 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 320 #define BRBE_IMPLEMENTED ULL(1) 321 322 /* ID_AA64DFR1_EL1 definitions */ 323 #define ID_AA64DFR1_EBEP_SHIFT U(48) 324 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 325 #define EBEP_IMPLEMENTED ULL(1) 326 327 #define ID_AA64DFR1_BRP_SHIFT U(8) 328 #define ID_AA64DFR1_BRP_WIDTH U(8) 329 330 /* ID_AA64DFR2_EL1 definitions */ 331 #define ID_AA64DFR2_STEP_SHIFT U(0) 332 #define ID_AA64DFR2_STEP_MASK ULL(0xf) 333 334 #define ID_AA64ZFR0_EL1 S3_0_C0_C4_4 335 #define ID_AA64FPFR0_EL1 S3_0_C0_C4_7 336 #define ID_AA64DFR2_EL1 S3_0_C0_C5_2 337 #define GMID_EL1 S3_1_C0_C0_4 338 339 /* ID_AA64ISAR0_EL1 definitions */ 340 #define ID_AA64ISAR0_ATOMIC_SHIFT U(20) 341 #define ID_AA64ISAR0_ATOMIC_MASK ULL(0xf) 342 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 343 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 344 345 #define ID_AA64ISAR0_AES_SHIFT U(0x4) 346 #define ID_AA64ISAR0_AES_MASK ULL(0xf) 347 #define ID_AA64ISAR0_SHA1_SHIFT U(0x8) 348 #define ID_AA64ISAR0_SHA1_MASK ULL(0xf) 349 #define ID_AA64ISAR0_SHA2_SHIFT U(0xc) 350 #define ID_AA64ISAR0_SHA2_MASK ULL(0xf) 351 352 /* ID_AA64ISAR1_EL1 definitions */ 353 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 354 355 #define ID_AA64ISAR1_LS64_SHIFT U(60) 356 #define ID_AA64ISAR1_LS64_MASK ULL(0xf) 357 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3) 358 #define LS64_V_IMPLEMENTED ULL(0x2) 359 #define LS64_IMPLEMENTED ULL(0x1) 360 #define LS64_NOT_IMPLEMENTED ULL(0x0) 361 362 #define ID_AA64ISAR1_SB_SHIFT U(36) 363 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 364 #define SB_IMPLEMENTED ULL(0x1) 365 #define SB_NOT_IMPLEMENTED ULL(0x0) 366 367 #define ID_AA64ISAR1_GPI_SHIFT U(28) 368 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 369 #define ID_AA64ISAR1_GPA_SHIFT U(24) 370 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 371 372 #define ID_AA64ISAR1_API_SHIFT U(8) 373 #define ID_AA64ISAR1_API_MASK ULL(0xf) 374 #define ID_AA64ISAR1_APA_SHIFT U(4) 375 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 376 377 /* ID_AA64ISAR2_EL1 definitions */ 378 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 379 #define ID_AA64ISAR2_EL1_MOPS_SHIFT U(16) 380 #define ID_AA64ISAR2_EL1_MOPS_MASK ULL(0xf) 381 382 #define MOPS_IMPLEMENTED ULL(0x1) 383 384 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 385 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 386 387 #define ID_AA64ISAR2_APA3_SHIFT U(12) 388 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 389 390 #define ID_AA64ISAR2_CLRBHB_SHIFT U(28) 391 #define ID_AA64ISAR2_CLRBHB_MASK ULL(0xf) 392 393 #define ID_AA64ISAR2_SYSREG128_SHIFT U(32) 394 #define ID_AA64ISAR2_SYSREG128_MASK ULL(0xf) 395 396 /* ID_AA64ISAR3_EL1 definitions */ 397 #define ID_AA64ISAR3_EL1 S3_0_C0_C6_3 398 #define ID_AA64ISAR3_EL1_CPA_SHIFT U(0) 399 #define ID_AA64ISAR3_EL1_CPA_MASK ULL(0xf) 400 401 #define CPA2_IMPLEMENTED ULL(0x2) 402 403 /* ID_AA64MMFR0_EL1 definitions */ 404 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 405 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 406 407 #define PARANGE_0000 U(32) 408 #define PARANGE_0001 U(36) 409 #define PARANGE_0010 U(40) 410 #define PARANGE_0011 U(42) 411 #define PARANGE_0100 U(44) 412 #define PARANGE_0101 U(48) 413 #define PARANGE_0110 U(52) 414 #define PARANGE_0111 U(56) 415 416 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 417 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 418 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 419 #define ECV_IMPLEMENTED ULL(0x1) 420 421 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 422 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 423 #define FGT2_IMPLEMENTED ULL(0x2) 424 #define FGT_IMPLEMENTED ULL(0x1) 425 #define FGT_NOT_IMPLEMENTED ULL(0x0) 426 427 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 428 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 429 430 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 431 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 432 433 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 434 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 435 #define TGRAN16_IMPLEMENTED ULL(0x1) 436 437 /* ID_AA64MMFR1_EL1 definitions */ 438 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 439 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 440 #define TWED_IMPLEMENTED ULL(0x1) 441 442 #define ID_AA64MMFR1_EL1_HAFDBS_SHIFT U(0) 443 #define ID_AA64MMFR1_EL1_HAFDBS_MASK ULL(0xf) 444 #define HDBSS_IMPLEMENTED ULL(0x4) 445 446 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 447 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 448 #define PAN_IMPLEMENTED ULL(0x1) 449 #define PAN2_IMPLEMENTED ULL(0x2) 450 #define PAN3_IMPLEMENTED ULL(0x3) 451 452 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 453 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 454 455 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 456 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 457 #define HCX_IMPLEMENTED ULL(0x1) 458 459 /* ID_AA64MMFR2_EL1 definitions */ 460 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 461 462 #define ID_AA64MMFR2_EL1_IDS_SHIFT U(36) 463 #define ID_AA64MMFR2_EL1_IDS_MASK ULL(0xf) 464 465 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 466 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 467 468 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 469 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 470 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 471 472 #define ID_AA64MMFR2_EL1_IESB_SHIFT U(12) 473 #define ID_AA64MMFR2_EL1_IESB_MASK ULL(0xf) 474 475 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 476 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 477 478 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 479 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 480 481 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 482 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 483 #define NV2_IMPLEMENTED ULL(0x2) 484 485 /* ID_AA64MMFR3_EL1 definitions */ 486 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 487 488 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32) 489 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf) 490 #define D128_IMPLEMENTED ULL(0x1) 491 492 #define ID_AA64MMFR3_EL1_MEC_SHIFT U(28) 493 #define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf) 494 495 #define ID_AA64MMFR3_EL1_AIE_SHIFT U(24) 496 #define ID_AA64MMFR3_EL1_AIE_MASK ULL(0xf) 497 498 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 499 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 500 501 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 502 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 503 504 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 505 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 506 507 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 508 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 509 510 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4) 511 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf) 512 #define SCTLR2_IMPLEMENTED ULL(1) 513 514 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 515 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 516 517 /* ID_AA64MMFR4_EL1 definitions */ 518 #define ID_AA64MMFR4_EL1 S3_0_C0_C7_4 519 520 #define ID_AA64MMFR4_EL1_HACDBS_SHIFT U(12) 521 #define ID_AA64MMFR4_EL1_HACDBS_MASK ULL(0xf) 522 #define HACDBS_IMPLEMENTED ULL(0x1) 523 524 #define ID_AA64MMFR4_EL1_FGWTE3_SHIFT U(16) 525 #define ID_AA64MMFR4_EL1_FGWTE3_MASK ULL(0xf) 526 #define FGWTE3_IMPLEMENTED ULL(0x1) 527 528 #define ID_AA64MMFR4_EL1_RME_GDI_SHIFT U(28) 529 #define ID_AA64MMFR4_EL1_RME_GDI_MASK ULL(0xf) 530 #define ID_AA64MMFR4_EL1_RME_GDI_LENGTH U(4) 531 #define RME_GDI_IMPLEMENTED ULL(0x1) 532 533 /* ID_AA64PFR1_EL1 definitions */ 534 535 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 536 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 537 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 538 539 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 540 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 541 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 542 543 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 544 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 545 546 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 547 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 548 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 549 550 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 551 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 552 #define NMI_IMPLEMENTED ULL(1) 553 554 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 555 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 556 #define GCS_IMPLEMENTED ULL(1) 557 558 #define ID_AA64PFR1_EL1_THE_SHIFT U(48) 559 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf) 560 #define THE_IMPLEMENTED ULL(1) 561 562 #define ID_AA64PFR1_EL1_PFAR_SHIFT U(60) 563 #define ID_AA64PFR1_EL1_PFAR_MASK ULL(0xf) 564 565 /* ID_AA64PFR1_EL1.CE field: Morello architecture presence (bits [23:20]) */ 566 #define ID_AA64PFR1_EL1_CE_SHIFT U(20) 567 #define ID_AA64PFR1_EL1_CE_MASK ULL(0xf) 568 /* 0b0000 means Morello arch is not present, 0b0001 means it is present */ 569 #define MORELLO_EXTENSION_IMPLEMENTED ULL(0x1) 570 #define CSCR_EL3_SETTAG ULL(0x1) 571 572 /* ID_AA64PFR2_EL1 definitions */ 573 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 574 575 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 576 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 577 578 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 579 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 580 581 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 582 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 583 584 #define ID_AA64PFR2_EL1_UINJ_SHIFT U(16) 585 #define ID_AA64PFR2_EL1_UINJ_MASK ULL(0xf) 586 #define UINJ_IMPLEMENTED ULL(0x1) 587 588 #define ID_AA64PFR2_EL1_FPMR_SHIFT U(32) 589 #define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf) 590 591 #define FPMR_IMPLEMENTED ULL(0x1) 592 593 #define VDISR_EL2 S3_4_C12_C1_1 594 #define VSESR_EL2 S3_4_C5_C2_3 595 596 /* Memory Tagging Extension is not implemented */ 597 #define MTE_UNIMPLEMENTED U(0) 598 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 599 #define MTE_IMPLEMENTED_EL0 U(1) 600 /* FEAT_MTE2: Full MTE is implemented */ 601 #define MTE_IMPLEMENTED_ELX U(2) 602 /* 603 * FEAT_MTE3: MTE is implemented with support for 604 * asymmetric Tag Check Fault handling 605 */ 606 #define MTE_IMPLEMENTED_ASY U(3) 607 608 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 609 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 610 611 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 612 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 613 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 614 #define SME_IMPLEMENTED ULL(0x1) 615 #define SME2_IMPLEMENTED ULL(0x2) 616 #define SME_NOT_IMPLEMENTED ULL(0x0) 617 618 /* ID_AA64PFR2_EL1 definitions */ 619 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 620 #define ID_AA64PFR2_EL1_GCIE_SHIFT 12 621 #define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf) 622 623 /* ID_PFR1_EL1 definitions */ 624 #define ID_PFR1_VIRTEXT_SHIFT U(12) 625 #define ID_PFR1_VIRTEXT_MASK U(0xf) 626 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 627 & ID_PFR1_VIRTEXT_MASK) 628 629 /* SCTLR definitions */ 630 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 631 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 632 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 633 634 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 635 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 636 637 #define SCTLR_AARCH32_EL1_RES1 \ 638 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 639 (U(1) << 4) | (U(1) << 3)) 640 641 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 642 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 643 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 644 645 #define SCTLR_M_BIT (ULL(1) << 0) 646 #define SCTLR_A_BIT (ULL(1) << 1) 647 #define SCTLR_C_BIT (ULL(1) << 2) 648 #define SCTLR_SA_BIT (ULL(1) << 3) 649 #define SCTLR_SA0_BIT (ULL(1) << 4) 650 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 651 #define SCTLR_nAA_BIT (ULL(1) << 6) 652 #define SCTLR_ITD_BIT (ULL(1) << 7) 653 #define SCTLR_SED_BIT (ULL(1) << 8) 654 #define SCTLR_UMA_BIT (ULL(1) << 9) 655 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 656 #define SCTLR_EOS_BIT (ULL(1) << 11) 657 #define SCTLR_I_BIT (ULL(1) << 12) 658 #define SCTLR_EnDB_BIT (ULL(1) << 13) 659 #define SCTLR_DZE_BIT (ULL(1) << 14) 660 #define SCTLR_UCT_BIT (ULL(1) << 15) 661 #define SCTLR_NTWI_BIT (ULL(1) << 16) 662 #define SCTLR_NTWE_BIT (ULL(1) << 18) 663 #define SCTLR_WXN_BIT (ULL(1) << 19) 664 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 665 #define SCTLR_IESB_BIT (ULL(1) << 21) 666 #define SCTLR_EIS_BIT (ULL(1) << 22) 667 #define SCTLR_SPAN_BIT (ULL(1) << 23) 668 #define SCTLR_E0E_BIT (ULL(1) << 24) 669 #define SCTLR_EE_BIT (ULL(1) << 25) 670 #define SCTLR_UCI_BIT (ULL(1) << 26) 671 #define SCTLR_EnDA_BIT (ULL(1) << 27) 672 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 673 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 674 #define SCTLR_EnIB_BIT (ULL(1) << 30) 675 #define SCTLR_EnIA_BIT (ULL(1) << 31) 676 #define SCTLR_BT0_BIT (ULL(1) << 35) 677 #define SCTLR_BT1_BIT (ULL(1) << 36) 678 #define SCTLR_BT_BIT (ULL(1) << 36) 679 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 680 #define SCTLR_TCF0_SHIFT U(38) 681 #define SCTLR_TCF0_MASK ULL(3) 682 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 683 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 684 685 /* Tag Check Faults in EL0 have no effect on the PE */ 686 #define SCTLR_TCF0_NO_EFFECT U(0) 687 /* Tag Check Faults in EL0 cause a synchronous exception */ 688 #define SCTLR_TCF0_SYNC U(1) 689 /* Tag Check Faults in EL0 are asynchronously accumulated */ 690 #define SCTLR_TCF0_ASYNC U(2) 691 /* 692 * Tag Check Faults in EL0 cause a synchronous exception on reads, 693 * and are asynchronously accumulated on writes 694 */ 695 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 696 697 #define SCTLR_TCF_SHIFT U(40) 698 #define SCTLR_TCF_MASK ULL(3) 699 700 /* Tag Check Faults in EL1 have no effect on the PE */ 701 #define SCTLR_TCF_NO_EFFECT U(0) 702 /* Tag Check Faults in EL1 cause a synchronous exception */ 703 #define SCTLR_TCF_SYNC U(1) 704 /* Tag Check Faults in EL1 are asynchronously accumulated */ 705 #define SCTLR_TCF_ASYNC U(2) 706 /* 707 * Tag Check Faults in EL1 cause a synchronous exception on reads, 708 * and are asynchronously accumulated on writes 709 */ 710 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 711 712 #define SCTLR_ATA0_BIT (ULL(1) << 42) 713 #define SCTLR_ATA_BIT (ULL(1) << 43) 714 #define SCTLR_DSSBS_SHIFT U(44) 715 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 716 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 717 #define SCTLR_TWEDEL_SHIFT U(46) 718 #define SCTLR_TWEDEL_MASK ULL(0xf) 719 #define SCTLR_EnASR_BIT (ULL(1) << 54) 720 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 721 #define SCTLR_EnALS_BIT (ULL(1) << 56) 722 #define SCTLR_EPAN_BIT (ULL(1) << 57) 723 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 724 725 #define SCTLR2_EnPACM_BIT (ULL(1) << 7) 726 #define SCTLR2_CPTA_BIT (ULL(1) << 9) 727 #define SCTLR2_CPTM_BIT (ULL(1) << 11) 728 729 /* SCTLR2 currently has no RES1 fields so reset to 0 */ 730 #define SCTLR2_RESET_VAL ULL(0) 731 732 /* CPACR_EL1 definitions */ 733 #define CPACR_EL1_FPEN(x) ((x) << 20) 734 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 735 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 736 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 737 #define CPACR_EL1_SMEN_SHIFT U(24) 738 #define CPACR_EL1_SMEN_MASK ULL(0x3) 739 740 /* SCR definitions */ 741 #if ENABLE_FEAT_GCIE 742 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT) 743 #else 744 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 745 #endif 746 #define SCR_NSE_SHIFT U(62) 747 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 748 #define SCR_HACDBSEn_BIT (UL(1) << 61) 749 #define SCR_HDBSSEn_BIT (UL(1) << 60) 750 #define SCR_FGTEN2_BIT (UL(1) << 59) 751 #define SCR_PFAREn_BIT (UL(1) << 53) 752 #define SCR_EnFPM_BIT (ULL(1) << 50) 753 #define SCR_MECEn_BIT (UL(1) << 49) 754 #define SCR_GPF_BIT (UL(1) << 48) 755 #define SCR_D128En_BIT (UL(1) << 47) 756 #define SCR_AIEn_BIT (UL(1) << 46) 757 #define SCR_TWEDEL_SHIFT U(30) 758 #define SCR_TWEDEL_MASK ULL(0xf) 759 #define SCR_PIEN_BIT (UL(1) << 45) 760 #define SCR_SCTLR2En_BIT (UL(1) << 44) 761 #define SCR_TCR2EN_BIT (UL(1) << 43) 762 #define SCR_RCWMASKEn_BIT (UL(1) << 42) 763 #define SCR_ENTP2_SHIFT U(41) 764 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 765 #define SCR_TRNDR_BIT (UL(1) << 40) 766 #define SCR_GCSEn_BIT (UL(1) << 39) 767 #define SCR_HXEn_BIT (UL(1) << 38) 768 #define SCR_ADEn_BIT (UL(1) << 37) 769 #define SCR_EnAS0_BIT (UL(1) << 36) 770 #define SCR_AMVOFFEN_SHIFT U(35) 771 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 772 #define SCR_TWEDEn_BIT (UL(1) << 29) 773 #define SCR_ECVEN_BIT (UL(1) << 28) 774 #define SCR_FGTEN_BIT (UL(1) << 27) 775 #define SCR_ATA_BIT (UL(1) << 26) 776 #define SCR_EnSCXT_BIT (UL(1) << 25) 777 #define SCR_TID5_BIT (UL(1) << 23) 778 #define SCR_TID3_BIT (UL(1) << 22) 779 #define SCR_FIEN_BIT (UL(1) << 21) 780 #define SCR_EEL2_SHIFT U(18) 781 #define SCR_EEL2_BIT (UL(1) << SCR_EEL2_SHIFT) 782 #define SCR_API_BIT (UL(1) << 17) 783 #define SCR_APK_BIT (UL(1) << 16) 784 #define SCR_TERR_BIT (UL(1) << 15) 785 #define SCR_TWE_BIT (UL(1) << 13) 786 #define SCR_TWI_BIT (UL(1) << 12) 787 #define SCR_ST_BIT (UL(1) << 11) 788 #define SCR_RW_BIT (UL(1) << 10) 789 #define SCR_SIF_BIT (UL(1) << 9) 790 #define SCR_HCE_BIT (UL(1) << 8) 791 #define SCR_SMD_BIT (UL(1) << 7) 792 #define SCR_EA_BIT (UL(1) << 3) 793 #define SCR_FIQ_BIT (UL(1) << 2) 794 #define SCR_IRQ_BIT (UL(1) << 1) 795 #define SCR_NS_BIT (UL(1) << 0) 796 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 797 #define SCR_RESET_VAL SCR_RES1_BITS 798 799 /* MDCR_EL3 definitions */ 800 #define MDCR_EnSTEPOP_BIT (ULL(1) << 50) 801 #define MDCR_EBWE_BIT (ULL(1) << 43) 802 #define MDCR_EnPMS3_BIT (ULL(1) << 42) 803 #define MDCR_PMEE(x) ((x) << 40) 804 #define MDCR_PMEE_CTRL_EL2 ULL(0x1) 805 #define MDCR_E3BREC_BIT (ULL(1) << 38) 806 #define MDCR_E3BREW_BIT (ULL(1) << 37) 807 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 808 #define MDCR_MPMX_BIT (ULL(1) << 35) 809 #define MDCR_MCCD_BIT (ULL(1) << 34) 810 #define MDCR_SBRBE_SHIFT U(32) 811 #define MDCR_SBRBE(x) ((x) << MDCR_SBRBE_SHIFT) 812 #define MDCR_SBRBE_ALL ULL(0x3) 813 #define MDCR_SBRBE_NS ULL(0x1) 814 #define MDCR_NSTB_EN_BIT (ULL(1) << 24) 815 #define MDCR_NSTB_SS_BIT (ULL(1) << 25) 816 #define MDCR_NSTBE_BIT (ULL(1) << 26) 817 #define MDCR_MTPME_BIT (ULL(1) << 28) 818 #define MDCR_TDCC_BIT (ULL(1) << 27) 819 #define MDCR_SCCD_BIT (ULL(1) << 23) 820 #define MDCR_EPMAD_BIT (ULL(1) << 21) 821 #define MDCR_EDAD_BIT (ULL(1) << 20) 822 #define MDCR_TTRF_BIT (ULL(1) << 19) 823 #define MDCR_STE_BIT (ULL(1) << 18) 824 #define MDCR_SPME_BIT (ULL(1) << 17) 825 #define MDCR_SDD_BIT (ULL(1) << 16) 826 #define MDCR_SPD32(x) ((x) << 14) 827 #define MDCR_SPD32_LEGACY ULL(0x0) 828 #define MDCR_SPD32_DISABLE ULL(0x2) 829 #define MDCR_SPD32_ENABLE ULL(0x3) 830 #define MDCR_NSPB_SS_BIT (ULL(1) << 13) 831 #define MDCR_NSPB_EN_BIT (ULL(1) << 12) 832 #define MDCR_NSPBE_BIT (ULL(1) << 11) 833 #define MDCR_TDOSA_BIT (ULL(1) << 10) 834 #define MDCR_TDA_BIT (ULL(1) << 9) 835 #define MDCR_EnPM2_BIT (ULL(1) << 7) 836 #define MDCR_TPM_BIT (ULL(1) << 6) 837 #define MDCR_RLTE_BIT (ULL(1) << 0) 838 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 839 840 /* MDCR_EL2 definitions */ 841 #define MDCR_EL2_MTPME (ULL(1) << 28) 842 #define MDCR_EL2_HLP_BIT (ULL(1) << 26) 843 #define MDCR_EL2_E2TB(x) ULL((x) << 24) 844 #define MDCR_EL2_E2TB_EL1 ULL(0x3) 845 #define MDCR_EL2_HCCD_BIT (ULL(1) << 23) 846 #define MDCR_EL2_TTRF (ULL(1) << 19) 847 #define MDCR_EL2_HPMD_BIT (ULL(1) << 17) 848 #define MDCR_EL2_TPMS (ULL(1) << 14) 849 #define MDCR_EL2_E2PB(x) ULL((x) << 12) 850 #define MDCR_EL2_E2PB_EL1 ULL(0x3) 851 #define MDCR_EL2_TDRA_BIT (ULL(1) << 11) 852 #define MDCR_EL2_TDOSA_BIT (ULL(1) << 10) 853 #define MDCR_EL2_TDA_BIT (ULL(1) << 9) 854 #define MDCR_EL2_TDE_BIT (ULL(1) << 8) 855 #define MDCR_EL2_HPME_BIT (ULL(1) << 7) 856 #define MDCR_EL2_TPM_BIT (ULL(1) << 6) 857 #define MDCR_EL2_TPMCR_BIT (ULL(1) << 5) 858 #define MDCR_EL2_HPMN_MASK ULL(0x1f) 859 #define MDCR_EL2_RESET_VAL ULL(0x0) 860 861 /* HSTR_EL2 definitions */ 862 #define HSTR_EL2_RESET_VAL U(0x0) 863 #define HSTR_EL2_T_MASK U(0xff) 864 865 /* CNTHP_CTL_EL2 definitions */ 866 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 867 #define CNTHP_CTL_RESET_VAL U(0x0) 868 869 /* VTTBR_EL2 definitions */ 870 #define VTTBR_RESET_VAL ULL(0x0) 871 #define VTTBR_VMID_MASK ULL(0xff) 872 #define VTTBR_VMID_SHIFT U(48) 873 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 874 #define VTTBR_BADDR_SHIFT U(0) 875 876 /* HCR definitions */ 877 #define HCR_RESET_VAL ULL(0x0) 878 #define HCR_AMVOFFEN_SHIFT U(51) 879 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 880 #define HCR_TEA_BIT (ULL(1) << 47) 881 #define HCR_API_BIT (ULL(1) << 41) 882 #define HCR_APK_BIT (ULL(1) << 40) 883 #define HCR_E2H_BIT (ULL(1) << 34) 884 #define HCR_HCD_BIT (ULL(1) << 29) 885 #define HCR_TGE_BIT (ULL(1) << 27) 886 #define HCR_RW_SHIFT U(31) 887 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 888 #define HCR_TWE_BIT (ULL(1) << 14) 889 #define HCR_TWI_BIT (ULL(1) << 13) 890 #define HCR_AMO_BIT (ULL(1) << 5) 891 #define HCR_IMO_BIT (ULL(1) << 4) 892 #define HCR_FMO_BIT (ULL(1) << 3) 893 894 /* ISR definitions */ 895 #define ISR_A_SHIFT U(8) 896 #define ISR_I_SHIFT U(7) 897 #define ISR_F_SHIFT U(6) 898 899 /* CNTHCTL_EL2 definitions */ 900 #define CNTHCTL_RESET_VAL U(0x0) 901 #define EVNTEN_BIT (U(1) << 2) 902 #define EL1PCEN_BIT (U(1) << 1) 903 #define EL1PCTEN_BIT (U(1) << 0) 904 905 /* CNTKCTL_EL1 definitions */ 906 #define EL0PTEN_BIT (U(1) << 9) 907 #define EL0VTEN_BIT (U(1) << 8) 908 #define EL0PCTEN_BIT (U(1) << 0) 909 #define EL0VCTEN_BIT (U(1) << 1) 910 #define EVNTEN_BIT (U(1) << 2) 911 #define EVNTDIR_BIT (U(1) << 3) 912 #define EVNTI_SHIFT U(4) 913 #define EVNTI_MASK U(0xf) 914 915 /* CPTR_EL3 definitions */ 916 #define TCPAC_BIT (U(1) << 31) 917 #define TAM_SHIFT U(30) 918 #define TAM_BIT (U(1) << TAM_SHIFT) 919 #define TTA_BIT (U(1) << 20) 920 #define ESM_BIT (U(1) << 12) 921 #define TFP_BIT (U(1) << 10) 922 #define CPTR_EZ_BIT (U(1) << 8) 923 924 #if ENABLE_FEAT_MORELLO 925 #define EC_BIT (U(1) << 9) 926 /* 927 * Even though the morello spec doesnot have TAM_BIT defined it is included 928 * to keep the definition as close to other hardware as possible. Since bit 30 929 * is reserved in Morello it should not have any effect anyways. 930 */ 931 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT | EC_BIT) & \ 932 ~(CPTR_EZ_BIT | ESM_BIT | TCPAC_BIT)) 933 #else 934 /* TCPAC is always set by default as the register is always present */ 935 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT) & \ 936 ~(CPTR_EZ_BIT | ESM_BIT | TCPAC_BIT)) 937 #endif 938 939 /* CPTR_EL2 definitions */ 940 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 941 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 942 #define CPTR_EL2_TAM_SHIFT U(30) 943 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 944 #define CPTR_EL2_SMEN_MASK ULL(0x3) 945 #define CPTR_EL2_SMEN_SHIFT U(24) 946 #define CPTR_EL2_TTA_BIT (U(1) << 20) 947 #define CPTR_EL2_ZEN_MASK ULL(0x3) 948 #define CPTR_EL2_ZEN_SHIFT U(16) 949 #define CPTR_EL2_TSM_BIT (U(1) << 12) 950 #define CPTR_EL2_TFP_BIT (ULL(1) << 10) 951 #define CPTR_EL2_TZ_BIT (ULL(1) << 8) 952 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 953 954 /* VTCR_EL2 definitions */ 955 #define VTCR_RESET_VAL U(0x0) 956 #define VTCR_EL2_MSA (U(1) << 31) 957 958 /* CPSR/SPSR definitions */ 959 #define DAIF_FIQ_BIT (U(1) << 0) 960 #define DAIF_IRQ_BIT (U(1) << 1) 961 #define DAIF_ABT_BIT (U(1) << 2) 962 #define DAIF_DBG_BIT (U(1) << 3) 963 #define SPSR_V_BIT (U(1) << 28) 964 #define SPSR_C_BIT (U(1) << 29) 965 #define SPSR_Z_BIT (U(1) << 30) 966 #define SPSR_N_BIT (U(1) << 31) 967 #define SPSR_DAIF_SHIFT U(6) 968 #define SPSR_DAIF_MASK U(0xf) 969 970 #define SPSR_AIF_SHIFT U(6) 971 #define SPSR_AIF_MASK U(0x7) 972 973 #define SPSR_E_SHIFT U(9) 974 #define SPSR_E_MASK U(0x1) 975 #define SPSR_E_LITTLE U(0x0) 976 #define SPSR_E_BIG U(0x1) 977 978 #define SPSR_T_SHIFT U(5) 979 #define SPSR_T_MASK U(0x1) 980 #define SPSR_T_ARM U(0x0) 981 #define SPSR_T_THUMB U(0x1) 982 983 #define SPSR_M_SHIFT U(4) 984 #define SPSR_M_MASK U(0x1) 985 #define SPSR_M_WIDTH U(1) 986 #define SPSR_M_AARCH64 U(0x0) 987 #define SPSR_M_AARCH32 U(0x1) 988 #define SPSR_M_EL1H U(0x5) 989 #define SPSR_M_EL2H U(0x9) 990 991 #define SPSR_EL_SHIFT U(2) 992 #define SPSR_EL_WIDTH U(2) 993 994 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 995 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 996 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 997 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 998 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 999 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 1000 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 1001 #define SPSR_IL_BIT BIT_64(20) 1002 #define SPSR_SS_BIT BIT_64(21) 1003 #define SPSR_PAN_BIT BIT_64(22) 1004 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 1005 #define SPSR_DIT_BIT BIT(24) 1006 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 1007 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 1008 #define SPSR_PPEND_BIT BIT(33) 1009 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 1010 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 1011 #define SPSR_PACM_BIT_AARCH64 BIT_64(35) 1012 #define SPSR_UINJ_BIT BIT_64(36) 1013 1014 /* 1015 * SPSR_EL2 1016 * M=0x9 (0b1001 EL2h) 1017 * M[4]=0 1018 * DAIF=0xF Exceptions masked on entry. 1019 * BTYPE=0 BTI not yet supported. 1020 * SSBS=0 Not yet supported. 1021 * IL=0 Not an illegal exception return. 1022 * SS=0 Not single stepping. 1023 * PAN=1 RMM shouldn't access Unprivileged memory when running in VHE mode. 1024 * UAO=0 1025 * DIT=0 1026 * TCO=0 1027 * NZCV=0 1028 */ 1029 #define SPSR_EL2_REALM (SPSR_M_EL2H | (0xF << SPSR_DAIF_SHIFT) | \ 1030 SPSR_PAN_BIT) 1031 1032 #define DISABLE_ALL_EXCEPTIONS \ 1033 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 1034 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 1035 1036 /* 1037 * RMR_EL3 definitions 1038 */ 1039 #define RMR_EL3_RR_BIT (U(1) << 1) 1040 #define RMR_EL3_AA64_BIT (U(1) << 0) 1041 1042 /* 1043 * HI-VECTOR address for AArch32 state 1044 */ 1045 #define HI_VECTOR_BASE U(0xFFFF0000) 1046 1047 /* 1048 * TCR definitions 1049 */ 1050 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 1051 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 1052 #define TCR_EL1_IPS_SHIFT U(32) 1053 #define TCR_EL2_PS_SHIFT U(16) 1054 #define TCR_EL3_PS_SHIFT U(16) 1055 1056 #define TCR_TxSZ_MIN ULL(16) 1057 #define TCR_TxSZ_MAX ULL(39) 1058 #define TCR_TxSZ_MAX_TTST ULL(48) 1059 1060 #define TCR_T0SZ_SHIFT U(0) 1061 #define TCR_T1SZ_SHIFT U(16) 1062 1063 /* (internal) physical address size bits in EL3/EL1 */ 1064 #define TCR_PS_BITS_4GB ULL(0x0) 1065 #define TCR_PS_BITS_64GB ULL(0x1) 1066 #define TCR_PS_BITS_1TB ULL(0x2) 1067 #define TCR_PS_BITS_4TB ULL(0x3) 1068 #define TCR_PS_BITS_16TB ULL(0x4) 1069 #define TCR_PS_BITS_256TB ULL(0x5) 1070 1071 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 1072 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 1073 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 1074 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 1075 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 1076 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 1077 1078 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 1079 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 1080 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 1081 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 1082 1083 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 1084 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 1085 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 1086 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 1087 1088 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 1089 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 1090 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 1091 1092 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 1093 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 1094 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 1095 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 1096 1097 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 1098 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 1099 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 1100 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 1101 1102 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 1103 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 1104 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 1105 1106 #define TCR_TG0_SHIFT U(14) 1107 #define TCR_TG0_MASK ULL(3) 1108 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 1109 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 1110 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 1111 1112 #define TCR_HPD_BIT (ULL(1) << 24) 1113 #define TCR_HWU59_BIT (ULL(1) << 25) 1114 #define TCR_HWU60_BIT (ULL(1) << 26) 1115 #define TCR_HWU61_BIT (ULL(1) << 27) 1116 #define TCR_HWU62_BIT (ULL(1) << 28) 1117 1118 #define TCR_TG1_SHIFT U(30) 1119 #define TCR_TG1_MASK ULL(3) 1120 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 1121 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 1122 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 1123 1124 #define TCR_EPD0_BIT (ULL(1) << 7) 1125 #define TCR_EPD1_BIT (ULL(1) << 23) 1126 1127 #define MODE_SP_SHIFT U(0x0) 1128 #define MODE_SP_MASK U(0x1) 1129 #define MODE_SP_EL0 U(0x0) 1130 #define MODE_SP_ELX U(0x1) 1131 1132 #define MODE_RW_SHIFT U(0x4) 1133 #define MODE_RW_MASK U(0x1) 1134 #define MODE_RW_64 U(0x0) 1135 #define MODE_RW_32 U(0x1) 1136 1137 #define MODE_EL_SHIFT U(0x2) 1138 #define MODE_EL_MASK U(0x3) 1139 #define MODE_EL_WIDTH U(0x2) 1140 #define MODE_EL3 U(0x3) 1141 #define MODE_EL2 U(0x2) 1142 #define MODE_EL1 U(0x1) 1143 #define MODE_EL0 U(0x0) 1144 1145 #define MODE32_SHIFT U(0) 1146 #define MODE32_MASK U(0xf) 1147 #define MODE32_usr U(0x0) 1148 #define MODE32_fiq U(0x1) 1149 #define MODE32_irq U(0x2) 1150 #define MODE32_svc U(0x3) 1151 #define MODE32_mon U(0x6) 1152 #define MODE32_abt U(0x7) 1153 #define MODE32_hyp U(0xa) 1154 #define MODE32_und U(0xb) 1155 #define MODE32_sys U(0xf) 1156 1157 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 1158 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 1159 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 1160 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 1161 1162 #define SPSR_64(el, sp, daif) \ 1163 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 1164 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 1165 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 1166 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 1167 (~(SPSR_SSBS_BIT_AARCH64))) 1168 1169 #define SPSR_MODE32(mode, isa, endian, aif) \ 1170 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 1171 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 1172 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 1173 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 1174 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 1175 (~(SPSR_SSBS_BIT_AARCH32))) 1176 1177 /* 1178 * TTBR Definitions 1179 */ 1180 #define TTBR_CNP_BIT ULL(0x1) 1181 1182 /* 1183 * CTR_EL0 definitions 1184 */ 1185 #define CTR_CWG_SHIFT U(24) 1186 #define CTR_CWG_MASK U(0xf) 1187 #define CTR_ERG_SHIFT U(20) 1188 #define CTR_ERG_MASK U(0xf) 1189 #define CTR_DMINLINE_SHIFT U(16) 1190 #define CTR_DMINLINE_MASK U(0xf) 1191 #define CTR_L1IP_SHIFT U(14) 1192 #define CTR_L1IP_MASK U(0x3) 1193 #define CTR_IMINLINE_SHIFT U(0) 1194 #define CTR_IMINLINE_MASK U(0xf) 1195 1196 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 1197 1198 /* Physical timer control register bit fields shifts and masks */ 1199 #define CNTP_CTL_ENABLE_SHIFT U(0) 1200 #define CNTP_CTL_IMASK_SHIFT U(1) 1201 #define CNTP_CTL_ISTATUS_SHIFT U(2) 1202 1203 #define CNTP_CTL_ENABLE_MASK U(1) 1204 #define CNTP_CTL_IMASK_MASK U(1) 1205 #define CNTP_CTL_ISTATUS_MASK U(1) 1206 1207 /* Physical timer control macros */ 1208 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 1209 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 1210 1211 /* Exception Syndrome register bits and bobs */ 1212 #define ESR_EC_SHIFT U(26) 1213 #define ESR_EC_MASK U(0x3f) 1214 #define ESR_EC_LENGTH U(6) 1215 #define ESR_EC_WIDTH U(6) 1216 #define ESR_ISS_SHIFT U(0) 1217 #define ESR_ISS_WIDTH U(25) 1218 #define ESR_IL_BIT (U(1) << 25) 1219 #define EC_UNKNOWN U(0x0) 1220 #define EC_WFE_WFI U(0x1) 1221 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 1222 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 1223 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 1224 #define EC_AARCH32_CP14_LDC_STC U(0x6) 1225 #define EC_FP_SIMD U(0x7) 1226 #define EC_AARCH32_CP10_MRC U(0x8) 1227 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1228 #define EC_ILLEGAL U(0xe) 1229 #define EC_AARCH32_SVC U(0x11) 1230 #define EC_AARCH32_HVC U(0x12) 1231 #define EC_AARCH32_SMC U(0x13) 1232 #define EC_AARCH64_SVC U(0x15) 1233 #define EC_AARCH64_HVC U(0x16) 1234 #define EC_AARCH64_SMC U(0x17) 1235 #define EC_AARCH64_SYS U(0x18) 1236 #define EC_IMP_DEF_EL3 U(0x1f) 1237 #define EC_IABORT_LOWER_EL U(0x20) 1238 #define EC_IABORT_CUR_EL U(0x21) 1239 #define EC_PC_ALIGN U(0x22) 1240 #define EC_DABORT_LOWER_EL U(0x24) 1241 #define EC_DABORT_CUR_EL U(0x25) 1242 #define EC_SP_ALIGN U(0x26) 1243 #define EC_AARCH32_FP U(0x28) 1244 #define EC_AARCH64_FP U(0x2c) 1245 #define EC_SERROR U(0x2f) 1246 #define EC_BRK U(0x3c) 1247 1248 /* ISS layout for trapped AArch64 system-register access (ESR_EL3.ISS) 1249 * 1250 * [21:20] Op0 1251 * [19:17] Op2 1252 * [16:14] Op1 1253 * [13:10] CRn 1254 * [9:5] Rt 1255 * [4:1] CRm 1256 * [0] DIR 1257 */ 1258 #define ISS_SYS64_OP0_SHIFT U(20) 1259 #define ISS_SYS64_OP0_WIDTH U(2) 1260 #define ISS_SYS64_OP2_SHIFT U(17) 1261 #define ISS_SYS64_OP2_WIDTH U(3) 1262 #define ISS_SYS64_OP1_SHIFT U(14) 1263 #define ISS_SYS64_OP1_WIDTH U(3) 1264 #define ISS_SYS64_CRN_SHIFT U(10) 1265 #define ISS_SYS64_CRN_WIDTH U(4) 1266 #define ISS_SYS64_RT_SHIFT U(5) 1267 #define ISS_SYS64_RT_WIDTH U(5) 1268 #define ISS_SYS64_CRM_SHIFT U(1) 1269 #define ISS_SYS64_CRM_WIDTH U(4) 1270 #define ISS_SYS64_DIR_SHIFT U(0) 1271 #define ISS_SYS64_DIR_WIDTH U(1) 1272 1273 /* The RT field encodes general purpose registers in sequence and xzr as #31 */ 1274 #define ISS_SYSREG_RT_XZR 31 1275 1276 #define SYSREG_ESR(op0, op1, crn, crm, op2) \ 1277 (((op0) << ISS_SYS64_OP0_SHIFT) | \ 1278 ((op1) << ISS_SYS64_OP1_SHIFT) | \ 1279 ((crn) << ISS_SYS64_CRN_SHIFT) | \ 1280 ((crm) << ISS_SYS64_CRM_SHIFT) | \ 1281 ((op2) << ISS_SYS64_OP2_SHIFT)) 1282 1283 #define ISS_SYSREG_OPCODE_RNDR SYSREG_ESR(3, 3, 2, 4, 0) 1284 #define ISS_SYSREG_OPCODE_RNDRRS SYSREG_ESR(3, 3, 2, 4, 1) 1285 1286 /* Group 3 ID Registers. Are all continous, some are not yet allocated */ 1287 #define ISS_SYSREG_OPCODE_ID_PFR0_EL1 SYSREG_ESR(3, 0, 0, 1, 0) 1288 #define ISS_SYSREG_OPCODE_ID_PFR1_EL1 SYSREG_ESR(3, 0, 0, 1, 1) 1289 #define ISS_SYSREG_OPCODE_ID_DFR0_EL1 SYSREG_ESR(3, 0, 0, 1, 2) 1290 #define ISS_SYSREG_OPCODE_ID_AFR0_EL1 SYSREG_ESR(3, 0, 0, 1, 3) 1291 #define ISS_SYSREG_OPCODE_ID_MMFR0_EL1 SYSREG_ESR(3, 0, 0, 1, 4) 1292 #define ISS_SYSREG_OPCODE_ID_MMFR1_EL1 SYSREG_ESR(3, 0, 0, 1, 5) 1293 #define ISS_SYSREG_OPCODE_ID_MMFR2_EL1 SYSREG_ESR(3, 0, 0, 1, 6) 1294 #define ISS_SYSREG_OPCODE_ID_MMFR3_EL1 SYSREG_ESR(3, 0, 0, 1, 7) 1295 1296 #define ISS_SYSREG_OPCODE_ID_ISAR0_EL1 SYSREG_ESR(3, 0, 0, 2, 0) 1297 #define ISS_SYSREG_OPCODE_ID_ISAR1_EL1 SYSREG_ESR(3, 0, 0, 2, 1) 1298 #define ISS_SYSREG_OPCODE_ID_ISAR2_EL1 SYSREG_ESR(3, 0, 0, 2, 2) 1299 #define ISS_SYSREG_OPCODE_ID_ISAR3_EL1 SYSREG_ESR(3, 0, 0, 2, 3) 1300 #define ISS_SYSREG_OPCODE_ID_ISAR4_EL1 SYSREG_ESR(3, 0, 0, 2, 4) 1301 #define ISS_SYSREG_OPCODE_ID_ISAR5_EL1 SYSREG_ESR(3, 0, 0, 2, 5) 1302 #define ISS_SYSREG_OPCODE_ID_MMFR4_EL1 SYSREG_ESR(3, 0, 0, 2, 6) 1303 #define ISS_SYSREG_OPCODE_ID_ISAR6_EL1 SYSREG_ESR(3, 0, 0, 2, 7) 1304 1305 #define ISS_SYSREG_OPCODE_MVFR0_EL1 SYSREG_ESR(3, 0, 0, 3, 0) 1306 #define ISS_SYSREG_OPCODE_MVFR1_EL1 SYSREG_ESR(3, 0, 0, 3, 1) 1307 #define ISS_SYSREG_OPCODE_MVFR2_EL1 SYSREG_ESR(3, 0, 0, 3, 2) 1308 #define ISS_SYSREG_OPCODE_ID_PFR2_EL1 SYSREG_ESR(3, 0, 0, 3, 4) 1309 #define ISS_SYSREG_OPCODE_ID_DFR1_EL1 SYSREG_ESR(3, 0, 0, 3, 5) 1310 #define ISS_SYSREG_OPCODE_ID_MMFR5_EL1 SYSREG_ESR(3, 0, 0, 3, 6) 1311 1312 #define ISS_SYSREG_OPCODE_ID_AA64PFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 0) 1313 #define ISS_SYSREG_OPCODE_ID_AA64PFR1_EL1 SYSREG_ESR(3, 0, 0, 4, 1) 1314 #define ISS_SYSREG_OPCODE_ID_AA64PFR2_EL1 SYSREG_ESR(3, 0, 0, 4, 2) 1315 #define ISS_SYSREG_OPCODE_ID_AA64ZFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 4) 1316 #define ISS_SYSREG_OPCODE_ID_AA64SMFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 5) 1317 #define ISS_SYSREG_OPCODE_ID_AA64FPFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 7) 1318 1319 #define ISS_SYSREG_OPCODE_ID_AA64DFR0_EL1 SYSREG_ESR(3, 0, 0, 5, 0) 1320 #define ISS_SYSREG_OPCODE_ID_AA64DFR1_EL1 SYSREG_ESR(3, 0, 0, 5, 1) 1321 #define ISS_SYSREG_OPCODE_ID_AA64DFR2_EL1 SYSREG_ESR(3, 0, 0, 5, 2) 1322 #define ISS_SYSREG_OPCODE_ID_AA64AFR0_EL1 SYSREG_ESR(3, 0, 0, 5, 4) 1323 #define ISS_SYSREG_OPCODE_ID_AA64AFR1_EL1 SYSREG_ESR(3, 0, 0, 5, 5) 1324 1325 #define ISS_SYSREG_OPCODE_ID_AA64ISAR0_EL1 SYSREG_ESR(3, 0, 0, 6, 0) 1326 #define ISS_SYSREG_OPCODE_ID_AA64ISAR1_EL1 SYSREG_ESR(3, 0, 0, 6, 1) 1327 #define ISS_SYSREG_OPCODE_ID_AA64ISAR2_EL1 SYSREG_ESR(3, 0, 0, 6, 2) 1328 #define ISS_SYSREG_OPCODE_ID_AA64ISAR3_EL1 SYSREG_ESR(3, 0, 0, 6, 3) 1329 #define ISS_SYSREG_OPCODE_ID_AA64MMFR0_EL1 SYSREG_ESR(3, 0, 0, 7, 0) 1330 1331 #define ISS_SYSREG_OPCODE_ID_AA64MMFR1_EL1 SYSREG_ESR(3, 0, 0, 7, 1) 1332 #define ISS_SYSREG_OPCODE_ID_AA64MMFR2_EL1 SYSREG_ESR(3, 0, 0, 7, 2) 1333 #define ISS_SYSREG_OPCODE_ID_AA64MMFR3_EL1 SYSREG_ESR(3, 0, 0, 7, 3) 1334 #define ISS_SYSREG_OPCODE_ID_AA64MMFR4_EL1 SYSREG_ESR(3, 0, 0, 7, 4) 1335 1336 #define ISS_SYSREG_OPCODE_IDREG_MIN ISS_SYSREG_OPCODE_ID_PFR0_EL1 1337 #define ISS_SYSREG_OPCODE_IDREG_MAX SYSREG_ESR(3, 0, 0, 7, 7) 1338 1339 /* Group 5 ID Register. Currently a single one. */ 1340 #define ISS_SYSREG_OPCODE_GMID_EL1 SYSREG_ESR(3, 1, 0, 0, 4) 1341 1342 /* Bits that must be set to end up in the IMPDEF registers space 1343 * (D23.3.2 of the Arm ARM) */ 1344 #define ISS_SYSREG_OPCODE_IMPDEF_MASK SYSREG_ESR(3, 0, 11, 0, 0) 1345 1346 /* 1347 * External Abort bit in Instruction and Data Aborts synchronous exception 1348 * syndromes. 1349 */ 1350 #define ESR_ISS_EABORT_EA_BIT U(9) 1351 1352 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1353 1354 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1355 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1356 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1357 1358 /******************************************************************************* 1359 * Definitions of register offsets, fields and macros for CPU system 1360 * instructions. 1361 ******************************************************************************/ 1362 1363 #define TLBI_ADDR_SHIFT U(12) 1364 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1365 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1366 1367 /******************************************************************************* 1368 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1369 * system level implementation of the Generic Timer. 1370 ******************************************************************************/ 1371 #define CNTCTLBASE_CNTFRQ U(0x0) 1372 #define CNTNSAR U(0x4) 1373 #define CNTNSAR_NS_SHIFT(x) (x) 1374 1375 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1376 #define CNTACR_RPCT_SHIFT U(0x0) 1377 #define CNTACR_RVCT_SHIFT U(0x1) 1378 #define CNTACR_RFRQ_SHIFT U(0x2) 1379 #define CNTACR_RVOFF_SHIFT U(0x3) 1380 #define CNTACR_RWVT_SHIFT U(0x4) 1381 #define CNTACR_RWPT_SHIFT U(0x5) 1382 1383 /******************************************************************************* 1384 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1385 * system level implementation of the Generic Timer. 1386 ******************************************************************************/ 1387 /* Physical Count register. */ 1388 #define CNTPCT_LO U(0x0) 1389 /* Counter Frequency register. */ 1390 #define CNTBASEN_CNTFRQ U(0x10) 1391 /* Physical Timer CompareValue register. */ 1392 #define CNTP_CVAL_LO U(0x20) 1393 /* Physical Timer Control register. */ 1394 #define CNTP_CTL U(0x2c) 1395 1396 /* PMCR_EL0 definitions */ 1397 #define PMCR_EL0_RESET_VAL U(0x0) 1398 #define PMCR_EL0_N_SHIFT U(11) 1399 #define PMCR_EL0_N_MASK U(0x1f) 1400 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1401 #define PMCR_EL0_LP_BIT (U(1) << 7) 1402 #define PMCR_EL0_LC_BIT (U(1) << 6) 1403 #define PMCR_EL0_DP_BIT (U(1) << 5) 1404 #define PMCR_EL0_X_BIT (U(1) << 4) 1405 #define PMCR_EL0_D_BIT (U(1) << 3) 1406 #define PMCR_EL0_C_BIT (U(1) << 2) 1407 #define PMCR_EL0_P_BIT (U(1) << 1) 1408 #define PMCR_EL0_E_BIT (U(1) << 0) 1409 1410 /******************************************************************************* 1411 * Definitions for system register interface to SVE 1412 ******************************************************************************/ 1413 #define ZCR_EL3 S3_6_C1_C2_0 1414 #define ZCR_EL2 S3_4_C1_C2_0 1415 1416 /* ZCR_EL3 definitions */ 1417 #define ZCR_EL3_LEN_MASK UL(0xf) 1418 1419 /******************************************************************************* 1420 * Definitions for system register interface to SME as needed in EL3 1421 ******************************************************************************/ 1422 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1423 #define SMCR_EL3 S3_6_C1_C2_6 1424 #define SVCR S3_3_C4_C2_2 1425 1426 /* ID_AA64SMFR0_EL1 definitions */ 1427 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1428 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1429 #define SME_FA64_IMPLEMENTED U(0x1) 1430 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1431 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1432 #define SME_INST_IMPLEMENTED ULL(0x0) 1433 #define SME2_INST_IMPLEMENTED ULL(0x1) 1434 1435 /* SMCR_ELx definitions */ 1436 #define SMCR_ELX_LEN_SHIFT U(0) 1437 #define SMCR_ELX_LEN_MAX U(0x1ff) 1438 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1439 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1440 1441 /******************************************************************************* 1442 * Definitions of MAIR encodings for device and normal memory 1443 ******************************************************************************/ 1444 /* 1445 * MAIR encodings for device memory attributes. 1446 */ 1447 #define MAIR_DEV_nGnRnE ULL(0x0) 1448 #define MAIR_DEV_nGnRE ULL(0x4) 1449 #define MAIR_DEV_nGRE ULL(0x8) 1450 #define MAIR_DEV_GRE ULL(0xc) 1451 1452 /* 1453 * MAIR encodings for normal memory attributes. 1454 * 1455 * Cache Policy 1456 * WT: Write Through 1457 * WB: Write Back 1458 * NC: Non-Cacheable 1459 * 1460 * Transient Hint 1461 * NTR: Non-Transient 1462 * TR: Transient 1463 * 1464 * Allocation Policy 1465 * RA: Read Allocate 1466 * WA: Write Allocate 1467 * RWA: Read and Write Allocate 1468 * NA: No Allocation 1469 */ 1470 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1471 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1472 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1473 #define MAIR_NORM_NC ULL(0x4) 1474 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1475 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1476 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1477 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1478 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1479 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1480 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1481 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1482 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1483 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1484 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1485 1486 #define MAIR_NORM_OUTER_SHIFT U(4) 1487 1488 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1489 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1490 1491 /* PAR_EL1 fields */ 1492 #define PAR_F_SHIFT U(0) 1493 #define PAR_F_MASK ULL(0x1) 1494 1495 #define PAR_D128_ADDR_MASK GENMASK(55, 12) /* 44-bits-wide page address */ 1496 #define PAR_ADDR_MASK GENMASK(51, 12) /* 40-bits-wide page address */ 1497 1498 /******************************************************************************* 1499 * Definitions for system register interface to SPE 1500 ******************************************************************************/ 1501 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1502 1503 /******************************************************************************* 1504 * Definitions for system register interface, shifts and masks for MPAM 1505 ******************************************************************************/ 1506 #define MPAMIDR_EL1 S3_0_C10_C4_4 1507 #define MPAM2_EL2 S3_4_C10_C5_0 1508 #define MPAMHCR_EL2 S3_4_C10_C4_0 1509 #define MPAM3_EL3 S3_6_C10_C5_0 1510 1511 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1512 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1513 /******************************************************************************* 1514 * Definitions for system register interface to AMU for FEAT_AMUv1 1515 ******************************************************************************/ 1516 #define AMCR_EL0 S3_3_C13_C2_0 1517 #define AMCFGR_EL0 S3_3_C13_C2_1 1518 #define AMCGCR_EL0 S3_3_C13_C2_2 1519 #define AMUSERENR_EL0 S3_3_C13_C2_3 1520 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1521 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1522 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1523 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1524 1525 /* Activity Monitor Group 0 Event Counter Registers */ 1526 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1527 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1528 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1529 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1530 1531 /* Activity Monitor Group 0 Event Type Registers */ 1532 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1533 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1534 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1535 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1536 1537 /* Activity Monitor Group 1 Event Counter Registers */ 1538 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1539 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1540 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1541 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1542 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1543 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1544 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1545 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1546 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1547 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1548 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1549 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1550 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1551 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1552 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1553 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1554 1555 /* Activity Monitor Group 1 Event Type Registers */ 1556 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1557 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1558 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1559 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1560 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1561 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1562 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1563 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1564 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1565 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1566 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1567 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1568 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1569 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1570 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1571 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1572 1573 /* AMCNTENSET0_EL0 definitions */ 1574 #define AMCNTENSET0_EL0_Pn_ALWAYS_ON ULL(0x3) 1575 #define AMCNTENSET0_EL0_Pn_CONTEXTED ULL(0xc) 1576 #define AMCNTENSET0_EL0_Pn_ALL ULL(0xf) 1577 1578 /* AMCNTENSET1_EL0 definitions */ 1579 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1580 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1581 1582 /* AMCNTENCLR0_EL0 definitions */ 1583 #define AMCNTENCLR0_EL0_Pn_ALWAYS_ON ULL(0x3) 1584 #define AMCNTENCLR0_EL0_Pn_CONTEXTED ULL(0xc) 1585 #define AMCNTENCLR0_EL0_Pn_ALL ULL(0xf) 1586 1587 /* AMCNTENCLR1_EL0 definitions */ 1588 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1589 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1590 1591 /* AMCFGR_EL0 definitions */ 1592 #define AMCFGR_EL0_NCG_SHIFT U(28) 1593 #define AMCFGR_EL0_NCG_MASK U(0xf) 1594 #define AMCFGR_EL0_N_SHIFT U(0) 1595 #define AMCFGR_EL0_N_MASK U(0xff) 1596 1597 /* AMCGCR_EL0 definitions */ 1598 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1599 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1600 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1601 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1602 1603 /* MPAM register definitions */ 1604 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1605 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1606 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1607 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1608 1609 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1610 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1611 1612 #define MPAMIDR_HAS_BW_CTRL_BIT (ULL(1) << 56) 1613 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1614 1615 /* MPAM_PE_BW_CTRL register definitions */ 1616 #define MPAMBW2_EL2 S3_4_C10_C5_4 1617 #define MPAMBW2_EL2_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1618 #define MPAMBW2_EL2_ENABLED_BIT (ULL(1) << 62) 1619 #define MPAMBW2_EL2_HARDLIM_BIT (ULL(1) << 61) 1620 #define MPAMBW2_EL2_NTRAP_MPAMBWIDR_EL1_BIT (ULL(1) << 52) 1621 #define MPAMBW2_EL2_NTRAP_MPAMBW0_EL1_BIT (ULL(1) << 51) 1622 #define MPAMBW2_EL2_NTRAP_MPAMBW1_EL1_BIT (ULL(1) << 50) 1623 #define MPAMBW2_EL2_NTRAP_MPAMBWSM_EL1_BIT (ULL(1) << 49) 1624 1625 #define MPAMBW3_EL3 S3_6_C10_C5_4 1626 #define MPAMBW3_EL3_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1627 #define MPAMBW3_EL3_ENABLED_BIT (ULL(1) << 62) 1628 #define MPAMBW3_EL3_HARDLIM_BIT (ULL(1) << 61) 1629 #define MPAMBW3_EL3_NTRAPLOWER_BIT (ULL(1) << 49) 1630 1631 /******************************************************************************* 1632 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1633 ******************************************************************************/ 1634 1635 /* Definition for register defining which virtual offsets are implemented. */ 1636 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1637 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1638 #define AMCG1IDR_CTR_SHIFT U(0) 1639 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1640 #define AMCG1IDR_VOFF_SHIFT U(16) 1641 1642 /* New bit added to AMCR_EL0 */ 1643 #define AMCR_CG1RZ_SHIFT U(17) 1644 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1645 1646 /* 1647 * Definitions for virtual offset registers for architected activity monitor 1648 * event counters. 1649 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1650 */ 1651 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1652 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1653 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1654 1655 /* 1656 * Definitions for virtual offset registers for auxiliary activity monitor event 1657 * counters. 1658 */ 1659 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1660 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1661 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1662 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1663 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1664 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1665 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1666 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1667 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1668 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1669 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1670 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1671 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1672 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1673 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1674 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1675 1676 /******************************************************************************* 1677 * Realm management extension register definitions 1678 ******************************************************************************/ 1679 #define GPCCR_EL3 S3_6_C2_C1_6 1680 #define GPTBR_EL3 S3_6_C2_C1_4 1681 1682 #define SCXTNUM_EL2 S3_4_C13_C0_7 1683 #define SCXTNUM_EL1 S3_0_C13_C0_7 1684 #define SCXTNUM_EL0 S3_3_C13_C0_7 1685 1686 /******************************************************************************* 1687 * RAS system registers 1688 ******************************************************************************/ 1689 #define DISR_EL1 S3_0_C12_C1_1 1690 #define DISR_A_BIT U(31) 1691 1692 #define ERRIDR_EL1 S3_0_C5_C3_0 1693 #define ERRIDR_MASK U(0xffff) 1694 1695 #define ERRSELR_EL1 S3_0_C5_C3_1 1696 1697 /* System register access to Standard Error Record registers */ 1698 #define ERXFR_EL1 S3_0_C5_C4_0 1699 #define ERXCTLR_EL1 S3_0_C5_C4_1 1700 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1701 #define ERXADDR_EL1 S3_0_C5_C4_3 1702 #define ERXPFGF_EL1 S3_0_C5_C4_4 1703 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1704 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1705 #define ERXMISC0_EL1 S3_0_C5_C5_0 1706 #define ERXMISC1_EL1 S3_0_C5_C5_1 1707 1708 #define ERXCTLR_ED_SHIFT U(0) 1709 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1710 #define ERXCTLR_UE_BIT (U(1) << 4) 1711 1712 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1713 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1714 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1715 1716 /******************************************************************************* 1717 * Armv8.3 Pointer Authentication Registers 1718 ******************************************************************************/ 1719 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1720 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1721 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1722 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1723 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1724 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1725 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1726 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1727 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1728 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1729 1730 /******************************************************************************* 1731 * Armv8.4 Data Independent Timing Registers 1732 ******************************************************************************/ 1733 #define DIT S3_3_C4_C2_5 1734 #define DIT_BIT BIT(24) 1735 1736 /******************************************************************************* 1737 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1738 ******************************************************************************/ 1739 #define SSBS S3_3_C4_C2_6 1740 1741 /******************************************************************************* 1742 * Armv8.5 - Memory Tagging Extension Registers 1743 ******************************************************************************/ 1744 #define TFSRE0_EL1 S3_0_C5_C6_1 1745 #define TFSR_EL1 S3_0_C5_C6_0 1746 #define RGSR_EL1 S3_0_C1_C0_5 1747 #define GCR_EL1 S3_0_C1_C0_6 1748 1749 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1750 1751 /******************************************************************************* 1752 * Armv8.5 - Random Number Generator Registers 1753 ******************************************************************************/ 1754 #define RNDR S3_3_C2_C4_0 1755 #define RNDRRS S3_3_C2_C4_1 1756 1757 /******************************************************************************* 1758 * FEAT_HCX - Extended Hypervisor Configuration Register 1759 ******************************************************************************/ 1760 #define HCRX_EL2 S3_4_C1_C2_2 1761 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1762 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1763 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1764 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1765 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1766 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1767 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1768 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1769 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1770 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1771 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1772 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1773 #define HCRX_EL2_INIT_VAL ULL(0x0) 1774 1775 /******************************************************************************* 1776 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1777 ******************************************************************************/ 1778 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1779 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1780 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1781 1782 /******************************************************************************* 1783 * FEAT_TCR2 - Extended Translation Control Registers 1784 ******************************************************************************/ 1785 #define TCR2_EL1 S3_0_C2_C0_3 1786 #define TCR2_EL2 S3_4_C2_C0_3 1787 1788 #define TCR2_EL2_INIT_VAL ULL(0) 1789 1790 /******************************************************************************* 1791 * Permission indirection and overlay Registers 1792 ******************************************************************************/ 1793 1794 #define PIRE0_EL1 S3_0_C10_C2_2 1795 #define PIRE0_EL2 S3_4_C10_C2_2 1796 #define PIR_EL1 S3_0_C10_C2_3 1797 #define PIR_EL2 S3_4_C10_C2_3 1798 #define POR_EL1 S3_0_C10_C2_4 1799 #define POR_EL2 S3_4_C10_C2_4 1800 #define S2PIR_EL2 S3_4_C10_C2_5 1801 #define S2POR_EL1 S3_0_C10_C2_5 1802 1803 /******************************************************************************* 1804 * FEAT_GCS - Guarded Control Stack Registers 1805 ******************************************************************************/ 1806 #define GCSCR_EL2 S3_4_C2_C5_0 1807 #define GCSPR_EL2 S3_4_C2_C5_1 1808 #define GCSCR_EL1 S3_0_C2_C5_0 1809 #define GCSCRE0_EL1 S3_0_C2_C5_2 1810 #define GCSPR_EL1 S3_0_C2_C5_1 1811 #define GCSPR_EL0 S3_3_C2_C5_1 1812 1813 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1814 1815 /******************************************************************************* 1816 * FEAT_TRF - Trace Filter Control Registers 1817 ******************************************************************************/ 1818 #define TRFCR_EL2 S3_4_C1_C2_1 1819 #define TRFCR_EL1 S3_0_C1_C2_1 1820 1821 /******************************************************************************* 1822 * FEAT_STEP2 - Step2 registers 1823 ******************************************************************************/ 1824 #define MDSTEPOP_EL1 S2_0_C0_C5_2 1825 1826 /******************************************************************************* 1827 * FEAT_THE - Translation Hardening Extension Registers 1828 ******************************************************************************/ 1829 #define RCWMASK_EL1 S3_0_C13_C0_6 1830 #define RCWSMASK_EL1 S3_0_C13_C0_3 1831 1832 /******************************************************************************* 1833 * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers 1834 ******************************************************************************/ 1835 #define SCTLR2_EL3 S3_6_C1_C0_3 1836 #define SCTLR2_EL2 S3_4_C1_C0_3 1837 #define SCTLR2_EL1 S3_0_C1_C0_3 1838 1839 /******************************************************************************* 1840 * FEAT_BRBE - Branch Record Buffer Extension Registers 1841 ******************************************************************************/ 1842 #define BRBCR_EL2 S2_4_C9_C0_0 1843 1844 /******************************************************************************* 1845 * FEAT_LS64_ACCDATA - LoadStore64B with status data 1846 ******************************************************************************/ 1847 #define ACCDATA_EL1 S3_0_C13_C0_5 1848 1849 /******************************************************************************* 1850 * Definitions for DynamicIQ Shared Unit registers 1851 ******************************************************************************/ 1852 #define CLUSTERPWRDN_EL1 S3_0_C15_C3_6 1853 1854 /******************************************************************************* 1855 * FEAT_FPMR - Floating point Mode Register 1856 ******************************************************************************/ 1857 #define FPMR S3_3_C4_C4_2 1858 1859 /* CLUSTERPWRDN_EL1 register definitions */ 1860 #define DSU_CLUSTER_PWR_OFF 0 1861 #define DSU_CLUSTER_PWR_ON 1 1862 #define DSU_CLUSTER_PWR_MASK U(1) 1863 #define DSU_CLUSTER_MEM_RET BIT(1) 1864 1865 /* CLUSTERPMMDCR register definitions */ 1866 #define CLUSTERPMMDCR_SPME U(1) 1867 1868 /******************************************************************************* 1869 * Definitions for CPU Power/Performance Management registers 1870 ******************************************************************************/ 1871 1872 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1873 #define CPUPPMCR_EL3_MPMMPINCTL_BIT BIT(0) 1874 1875 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1876 #define CPUMPMMCR_EL3_MPMM_EN_BIT BIT(0) 1877 1878 /* alternative system register encoding for the "sb" speculation barrier */ 1879 #define SYSREG_SB S0_3_C3_C0_7 1880 1881 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1882 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1883 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1884 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1885 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1886 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1887 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1888 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1889 #define CLUSTERPMMDCR_EL3 S3_6_C15_C6_3 1890 1891 #define CLUSTERPMCR_E_BIT BIT(0) 1892 #define CLUSTERPMCR_N_SHIFT U(11) 1893 #define CLUSTERPMCR_N_MASK U(0x1f) 1894 1895 /******************************************************************************* 1896 * FEAT_MEC - Memory Encryption Contexts 1897 ******************************************************************************/ 1898 #define MECIDR_EL2 S3_4_C10_C8_7 1899 #define MECIDR_EL2_MECIDWidthm1_MASK U(0xf) 1900 #define MECIDR_EL2_MECIDWidthm1_SHIFT U(0) 1901 1902 /****************************************************************************** 1903 * FEAT_FGWTE3 - Fine Grained Write Trap 1904 ******************************************************************************/ 1905 #define FGWTE3_EL3 S3_6_C1_C1_5 1906 1907 /* FGWTE3_EL3 Defintions */ 1908 #define FGWTE3_EL3_GPCBW_EL3_BIT (U(1) << 22) 1909 #define FGWTE3_EL3_VBAR_EL3_BIT (U(1) << 21) 1910 #define FGWTE3_EL3_TTBR0_EL3_BIT (U(1) << 20) 1911 #define FGWTE3_EL3_TPIDR_EL3_BIT (U(1) << 19) 1912 #define FGWTE3_EL3_TCR_EL3_BIT (U(1) << 18) 1913 #define FGWTE3_EL3_SPMROOTCR_EL3_BIT (U(1) << 17) 1914 #define FGWTE3_EL3_SCTLR2_EL3_BIT (U(1) << 16) 1915 #define FGWTE3_EL3_SCTLR_EL3_BIT (U(1) << 15) 1916 #define FGWTE3_EL3_PIR_EL3_BIT (U(1) << 14) 1917 #define FGWTE3_EL3_MECID_RL_A_EL3_BIT (U(1) << 12) 1918 #define FGWTE3_EL3_MAIR2_EL3_BIT (U(1) << 10) 1919 #define FGWTE3_EL3_MAIR_EL3_BIT (U(1) << 9) 1920 #define FGWTE3_EL3_GPTBR_EL3_BIT (U(1) << 8) 1921 #define FGWTE3_EL3_GPCCR_EL3_BIT (U(1) << 7) 1922 #define FGWTE3_EL3_GCSPR_EL3_BIT (U(1) << 6) 1923 #define FGWTE3_EL3_GCSCR_EL3_BIT (U(1) << 5) 1924 #define FGWTE3_EL3_AMAIR2_EL3_BIT (U(1) << 4) 1925 #define FGWTE3_EL3_AMAIR_EL3_BIT (U(1) << 3) 1926 #define FGWTE3_EL3_AFSR1_EL3_BIT (U(1) << 2) 1927 #define FGWTE3_EL3_AFSR0_EL3_BIT (U(1) << 1) 1928 #define FGWTE3_EL3_ACTLR_EL3_BIT (U(1) << 0) 1929 1930 #define FGWTE3_EL3_EARLY_INIT_VAL ( \ 1931 FGWTE3_EL3_GPCBW_EL3_BIT | \ 1932 FGWTE3_EL3_VBAR_EL3_BIT | \ 1933 FGWTE3_EL3_TTBR0_EL3_BIT | \ 1934 FGWTE3_EL3_SPMROOTCR_EL3_BIT | \ 1935 FGWTE3_EL3_SCTLR2_EL3_BIT | \ 1936 FGWTE3_EL3_PIR_EL3_BIT | \ 1937 FGWTE3_EL3_MECID_RL_A_EL3_BIT | \ 1938 FGWTE3_EL3_MAIR2_EL3_BIT | \ 1939 FGWTE3_EL3_MAIR_EL3_BIT | \ 1940 FGWTE3_EL3_GCSPR_EL3_BIT | \ 1941 FGWTE3_EL3_GCSCR_EL3_BIT | \ 1942 FGWTE3_EL3_AMAIR2_EL3_BIT | \ 1943 FGWTE3_EL3_AMAIR_EL3_BIT | \ 1944 FGWTE3_EL3_AFSR1_EL3_BIT | \ 1945 FGWTE3_EL3_AFSR0_EL3_BIT) 1946 1947 #if HW_ASSISTED_COHERENCY 1948 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT FGWTE3_EL3_SCTLR_EL3_BIT 1949 #else 1950 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT 0 1951 #endif 1952 1953 #if !(CRASH_REPORTING) 1954 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT FGWTE3_EL3_TPIDR_EL3_BIT 1955 #else 1956 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT 0 1957 #endif 1958 1959 #define FGWTE3_EL3_LATE_INIT_VAL ( \ 1960 FGWTE3_EL3_EARLY_INIT_VAL | \ 1961 FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT | \ 1962 FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT | \ 1963 FGWTE3_EL3_TCR_EL3_BIT | \ 1964 FGWTE3_EL3_GPTBR_EL3_BIT | \ 1965 FGWTE3_EL3_GPCCR_EL3_BIT | \ 1966 FGWTE3_EL3_ACTLR_EL3_BIT) 1967 1968 #endif /* ARCH_H */ 1969