1/* 2 * Copyright (c) 2019-2026, Arm Limited. All rights reserved. 3 * Copyright (c) 2021-2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8#include <arch.h> 9#include <asm_macros.S> 10#include <common/bl_common.h> 11#include <cortex_a78_ae.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21#if WORKAROUND_CVE_2022_23960 22 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae 23#endif /* WORKAROUND_CVE_2022_23960 */ 24 25cpu_reset_prologue cortex_a78_ae 26 27workaround_reset_start cortex_a78_ae, ERRATUM(1827431), ERRATA_A78_AE_1827431 28 sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(53) 29workaround_reset_end cortex_a78_ae, ERRATUM(1827431) 30 31check_erratum_ls cortex_a78_ae, ERRATUM(1827431), CPU_REV(0, 0) 32 33workaround_reset_start cortex_a78_ae, ERRATUM(1827433), ERRATA_A78_AE_1827433 34 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, BIT(2) 35workaround_reset_end cortex_a78_ae, ERRATUM(1827433) 36 37check_erratum_ls cortex_a78_ae, ERRATUM(1827433), CPU_REV(0, 0) 38 39workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500 40 sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 41workaround_reset_end cortex_a78_ae, ERRATUM(1941500) 42 43check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1) 44 45workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502 46 msr S3_6_c15_c8_0, xzr 47 ldr x0, =0x10E3900002 48 msr S3_6_c15_c8_2, x0 49 ldr x0, =0x10FFF00083 50 msr S3_6_c15_c8_3, x0 51 ldr x0, =0x2001003FF 52 msr S3_6_c15_c8_1, x0 53 54 mov x0, #1 55 msr S3_6_c15_c8_0, x0 56 ldr x0, =0x10E3800082 57 msr S3_6_c15_c8_2, x0 58 ldr x0, =0x10FFF00083 59 msr S3_6_c15_c8_3, x0 60 ldr x0, =0x2001003FF 61 msr S3_6_c15_c8_1, x0 62 63 mov x0, #2 64 msr S3_6_c15_c8_0, x0 65 ldr x0, =0x10E3800200 66 msr S3_6_c15_c8_2, x0 67 ldr x0, =0x10FFF003E0 68 msr S3_6_c15_c8_3, x0 69 ldr x0, =0x2001003FF 70 msr S3_6_c15_c8_1, x0 71workaround_reset_end cortex_a78_ae, ERRATUM(1951502) 72 73check_erratum_ls cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 1) 74 75workaround_reset_start cortex_a78_ae, ERRATUM(2242639), ERRATA_A78_AE_2242639 76 ldr x0,=0x5 77 msr s3_6_c15_c8_0,x0 78 ldr x0,=0x10f600e000 79 msr s3_6_c15_c8_2,x0 80 ldr x0,=0x10ff80e000 81 msr s3_6_c15_c8_3,x0 82 ldr x0,=0x80000000003ff 83 msr s3_6_c15_c8_1,x0 84 isb 85workaround_reset_end cortex_a78_ae, ERRATUM(2242639) 86 87check_erratum_range cortex_a78_ae, ERRATUM(2242639), CPU_REV(0, 1), CPU_REV(0, 1) 88 89workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748 90 /* ------------------------------------------------------- 91 * Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to 92 * behave like PLD/PRFM LD and not cause invalidations to 93 * other PE caches. There might be a small performance 94 * degradation to this workaround for certain workloads 95 * that share data. 96 * ------------------------------------------------------- 97 */ 98 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0 99workaround_reset_end cortex_a78_ae, ERRATUM(2376748) 100 101check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 2) 102 103workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408 104 /* -------------------------------------------------------- 105 * Disable folding of demand requests into older prefetches 106 * with L2 miss requests outstanding by setting the 107 * CPUACTLR2_EL1[40] to 1. 108 * -------------------------------------------------------- 109 */ 110 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40 111workaround_reset_end cortex_a78_ae, ERRATUM(2395408) 112 113check_erratum_ls cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 1) 114 115workaround_reset_start cortex_a78_ae, ERRATUM(2466780), ERRATA_A78_AE_2466780 116 ldr x0,=0x3 117 msr s3_6_c15_c8_0,x0 118 ldr x0,=0xee010f10 119 msr s3_6_c15_c8_2,x0 120 ldr x0,=0xff1f0ffe 121 msr s3_6_c15_c8_3,x0 122 ldr x0,=0x100000004003ff 123 msr s3_6_c15_c8_1,x0 124 isb 125workaround_reset_end cortex_a78_ae, ERRATUM(2466780) 126 127check_erratum_ls cortex_a78_ae, ERRATUM(2466780), CPU_REV(0, 1) 128 129workaround_reset_start cortex_a78_ae, ERRATUM(2743229), ERRATA_A78_AE_2743229 130 sysreg_bitfield_insert CORTEX_A78_AE_CPUACTLR5_EL1, 1, 55, 2 131workaround_reset_end cortex_a78_ae, ERRATUM(2743229) 132 133check_erratum_ls cortex_a78_ae, ERRATUM(2743229), CPU_REV(0, 2) 134 135workaround_reset_start cortex_a78_ae, ERRATUM(2779481), ERRATA_A78_AE_2779481 136 sysreg_bit_set CORTEX_A78_AE_CPUACTLR3_EL1, BIT(47) 137workaround_reset_end cortex_a78_ae, ERRATUM(2779481) 138 139check_erratum_ls cortex_a78_ae, ERRATUM(2779481), CPU_REV(0, 2) 140 141workaround_reset_start cortex_a78_ae, ERRATUM(3888018), ERRATA_A78_AE_3888018 142 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, BIT(22) 143workaround_reset_end cortex_a78_ae, ERRATUM(3888018) 144 145check_erratum_chosen cortex_a78_ae, ERRATUM(3888018), ERRATA_A78_AE_3888018 146 147workaround_reset_start cortex_a78_ae, ERRATUM(4302973), ERRATA_A78_AE_4302973 148 sysreg_bit_set CORTEX_A78_AE_CPUACTLR5_EL1, BIT(50) 149workaround_reset_end cortex_a78_ae, ERRATUM(4302973) 150 151check_erratum_chosen cortex_a78_ae, ERRATUM(4302973), ERRATA_A78_AE_4302973 152 153workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 154#if IMAGE_BL31 155 /* 156 * The Cortex-A78AE generic vectors are overridden to apply errata 157 * mitigation on exception entry from lower ELs. 158 */ 159 override_vector_table wa_cve_vbar_cortex_a78_ae 160#endif /* IMAGE_BL31 */ 161workaround_reset_end cortex_a78_ae, CVE(2022, 23960) 162 163check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 164 165/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 166workaround_reset_start cortex_a78_ae, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 167 sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46) 168workaround_reset_end cortex_a78_ae, CVE(2024, 5660) 169 170check_erratum_ls cortex_a78_ae, CVE(2024, 5660), CPU_REV(0, 3) 171 172cpu_reset_func_start cortex_a78_ae 173#if ENABLE_FEAT_AMU 174 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 175 sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT 176 177 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 178 sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT 179 180 /* Enable group0 counters */ 181 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 182 msr CPUAMCNTENSET0_EL0, x0 183 184 /* Enable group1 counters */ 185 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 186 msr CPUAMCNTENSET1_EL0, x0 187#endif 188cpu_reset_func_end cortex_a78_ae 189 190 /* ------------------------------------------------------- 191 * HW will do the cache maintenance while powering down 192 * ------------------------------------------------------- 193 */ 194func cortex_a78_ae_core_pwr_dwn 195 /* ------------------------------------------------------- 196 * Enable CPU power down bit in power control register 197 * ------------------------------------------------------- 198 */ 199 sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 200 isb 201 ret 202endfunc cortex_a78_ae_core_pwr_dwn 203 204 /* ------------------------------------------------------- 205 * This function provides cortex_a78_ae specific 206 * register information for crash reporting. 207 * It needs to return with x6 pointing to 208 * a list of register names in ascii and 209 * x8 - x15 having values of registers to be 210 * reported. 211 * ------------------------------------------------------- 212 */ 213.section .rodata.cortex_a78_ae_regs, "aS" 214cortex_a78_ae_regs: /* The ascii list of register names to be reported */ 215 .asciz "cpuectlr_el1", "" 216 217func cortex_a78_ae_cpu_reg_dump 218 adr x6, cortex_a78_ae_regs 219 mrs x8, CORTEX_A78_CPUECTLR_EL1 220 ret 221endfunc cortex_a78_ae_cpu_reg_dump 222 223declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ 224 cortex_a78_ae_reset_func, \ 225 cortex_a78_ae_core_pwr_dwn 226