Update CHANGELOG for 3.18.0

Update CHANGELOG for 3.18.0 and collect Tested-by tags.

Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io> (Poplar)
Tested-by: Jerome Forissier <jerome.forissier@linaro

Update CHANGELOG for 3.18.0

Update CHANGELOG for 3.18.0 and collect Tested-by tags.

Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io> (Poplar)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_virt, GP, PKCS#11)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Base RevC)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Foundation model)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a, GP, PKCS#11)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (hikey-hikey960, GP, PKCS#11)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (hikey-hikey, GP, PKCS#11)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sxsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8dxlevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8ulpevk)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1, gp, pkcs11, stmm)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1012A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1028A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1088A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS2088A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1046A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1043A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-QDS)
Tested-by: Ricardo Salveti <ricardo@foundries.io> (ZynqMP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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ci: azure: add STM32MP135F-DK platform support

Adds ci build for the STM32MP135F-DK from STMicroelectronics

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Car

ci: azure: add STM32MP135F-DK platform support

Adds ci build for the STM32MP135F-DK from STMicroelectronics

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1)

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drivers: stm32_gpio: temporary GPIO configuration for STM32MP13

This temporary change set all configured GPIOs to non-secure state
on STM32MP13 platform. This change is needed while we align all
com

drivers: stm32_gpio: temporary GPIO configuration for STM32MP13

This temporary change set all configured GPIOs to non-secure state
on STM32MP13 platform. This change is needed while we align all
components.

Changes I2C driver to assign I2C pins to secure world for STM32MP13.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: temporary ETZPC configuration

As device-tree configuration for the ETZPC is not yet handled,
add a temporary configuration in the platform main.

Signed-off-by: Gatien Chevallier <gat

plat-stm32mp1: temporary ETZPC configuration

As device-tree configuration for the ETZPC is not yet handled,
add a temporary configuration in the platform main.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: add APB6 memory mapping

This patch adds the secure memory mapping for APB6.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.ca

plat-stm32mp1: add APB6 memory mapping

This patch adds the secure memory mapping for APB6.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: define specific STM32MP13 peripheral addresses

Some peripheral addresses differ from STM32MP15 to STM32MP13.
This change adds support for those differences.

Signed-off-by: Gatien Che

plat-stm32mp1: define specific STM32MP13 peripheral addresses

Some peripheral addresses differ from STM32MP15 to STM32MP13.
This change adds support for those differences.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: tzc400: support STM32MP13

On STM32MP13 platforms, there is only one TZC filter unit.
Therefore, differentiate the TZC_FILTERS_MASK from the STM32MP15,
which has two.

Signed-off-by: G

plat-stm32mp1: tzc400: support STM32MP13

On STM32MP13 platforms, there is only one TZC filter unit.
Therefore, differentiate the TZC_FILTERS_MASK from the STM32MP15,
which has two.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: clk: clk-stm32mp13: add ck_mlahb to critical clocks

This clock must remain enabled as long as the platform is running.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Sign

drivers: clk: clk-stm32mp13: add ck_mlahb to critical clocks

This clock must remain enabled as long as the platform is running.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: conf: introduce STM32MP13 configuration

This change introduces STM32MP13 minimal configuration and
differentiates STM32MP15 platform from the STM32MP13 one by enabling
or disabling sp

plat-stm32mp1: conf: introduce STM32MP13 configuration

This change introduces STM32MP13 minimal configuration and
differentiates STM32MP15 platform from the STM32MP13 one by enabling
or disabling specific switches.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: CFG_TZSRAM_START may not be defined

STM32MP13 SoCs do not use internal RAM to run OP-TEE hence do not
define CFG_TZSRAM_START/SIZE for that platform.

Signed-off-by: Gatien Chevallier

plat-stm32mp1: CFG_TZSRAM_START may not be defined

STM32MP13 SoCs do not use internal RAM to run OP-TEE hence do not
define CFG_TZSRAM_START/SIZE for that platform.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: conf: set variant config before common default configs

Moves definition of variant config (MP15/MP13) to conf.mk file top,
before common switches default initialization. This is more

plat-stm32mp1: conf: set variant config before common default configs

Moves definition of variant config (MP15/MP13) to conf.mk file top,
before common switches default initialization. This is more flexible
to define target specific configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: conf: implement switch list for CFG_STM32MP15|13

CFG_STM32MP15 and CFG_STM32MP13 are part of a configuration choice list,
one and one only of the items shall be enabled.

Highlight th

plat-stm32mp1: conf: implement switch list for CFG_STM32MP15|13

CFG_STM32MP15 and CFG_STM32MP13 are part of a configuration choice list,
one and one only of the items shall be enabled.

Highlight that with an inline comment and some logic. The default target
is CFG_STM32MP15 for backward compatibility.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: conf: introduce STM32MP1 flavorlists

Add flavorlist-MP13 to list boards currently supported for the
STM32MP13 SoC.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Re

plat-stm32mp1: conf: introduce STM32MP1 flavorlists

Add flavorlist-MP13 to list boards currently supported for the
STM32MP13 SoC.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: support STM32MP13 gpio bank resources

STM32MP13 platform does not support the same amount of GPIO bank.

Always define the util functions. Support STM32MP13 and STM32MP15.

Signed-off

plat-stm32mp1: support STM32MP13 gpio bank resources

STM32MP13 platform does not support the same amount of GPIO bank.

Always define the util functions. Support STM32MP13 and STM32MP15.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: scmi_server update for STM32MP13

Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.

This change also remove the '0' index to the SCMI domains

plat-stm32mp1: scmi_server update for STM32MP13

Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.

This change also remove the '0' index to the SCMI domains in order to
align with Linux kernel.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dt-bindings: add STM32MP13 regulator bindings

These bindings will be used for the SCMI voltage domain.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien

dt-bindings: add STM32MP13 regulator bindings

These bindings will be used for the SCMI voltage domain.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add initial support of STM32MP135F-DK board

Add support of STM32MP135F discovery board (part number:
STM32MP135F-DK) that integrates a STM32MP135F SoC with 512 MB of DDR3.

The board pro

dts: stm32: add initial support of STM32MP135F-DK board

Add support of STM32MP135F discovery board (part number:
STM32MP135F-DK) that integrates a STM32MP135F SoC with 512 MB of DDR3.

The board provides SDcard and USB mass storage as persistent storage
device interfaces.

Co-developed-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
- STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-st

dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
- STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-storage: 3*SDMCC, 1*QSPI, FMC
-com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART
-audio: 2*SAI
-network: 1*ETH(GMAC)
-STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-STM32MP135: STM32MP133 + DCMIPP, LTDC

Co-developed-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Disable SA2UL RNG driver on unsupported flavors

Only enable the SA2UL TRNG on platform flavors that are currently
supported. This can be relaxed for platforms as support is verifie

plat-k3: drivers: Disable SA2UL RNG driver on unsupported flavors

Only enable the SA2UL TRNG on platform flavors that are currently
supported. This can be relaxed for platforms as support is verified.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: kernel: fix rpc shm free when prealloc is disable

Fixes commit [1] that changed implementation of the standard invocation
SMC command to introduce invocation with RPC shared memory refere

core: arm: kernel: fix rpc shm free when prealloc is disable

Fixes commit [1] that changed implementation of the standard invocation
SMC command to introduce invocation with RPC shared memory reference.
A wrong logic was implemented to free RPC buffer on standard invocation
completion. This change fixes that by freeing the cached shared memory
when pre-allocation is disable by config switch or runtime service.

Fixes: feb290a51087 ("core: add OPTEE_SMC_CALL_WITH_RPC_ARG")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: plat-ls: correct expression CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE

There was no parenthesis around CFG_TEE_CORE_NB_CORE
when assigning it to CFG_NUM_THREADS, so corrected it.

Signed-off-by:

core: plat-ls: correct expression CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE

There was no parenthesis around CFG_TEE_CORE_NB_CORE
when assigning it to CFG_NUM_THREADS, so corrected it.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: plat-ls: remove OP-TEE support for LS1012A-FRWY platform

LS1012A-FRWY does not support OP-TEE anymore, removing its
support.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: J

core: plat-ls: remove OP-TEE support for LS1012A-FRWY platform

LS1012A-FRWY does not support OP-TEE anymore, removing its
support.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-ls: set CFG_NUM_THREADS ?= 2 for LS1012ARDB

xtest regression_1009.3 fails on LS1012ARDB because the test needs
at least two threads but the default configuration for the platform
enables

core: plat-ls: set CFG_NUM_THREADS ?= 2 for LS1012ARDB

xtest regression_1009.3 fails on LS1012ARDB because the test needs
at least two threads but the default configuration for the platform
enables only one. Set CFG_NUM_THREADS ?= 2 to fix the issue.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: increase the minimum entropy delay the imx6sx

The i.MX6SX requires to start the RNG instantiation at a higher
entropy delay to provide a stable RNG generation and avoid RNG
hardware e

drivers: caam: increase the minimum entropy delay the imx6sx

The i.MX6SX requires to start the RNG instantiation at a higher
entropy delay to provide a stable RNG generation and avoid RNG
hardware errors.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: fix get_linear_map_end()

With paging enabled there is an unpaged portion of OP-TEE which ends at
the address returned by get_linear_map_end(). Without ASLR enabled this
is both a virtua

core: pager: fix get_linear_map_end()

With paging enabled there is an unpaged portion of OP-TEE which ends at
the address returned by get_linear_map_end(). Without ASLR enabled this
is both a virtual and physical address. However, with ASLR enabled it's
important to keep these addresses apart so add get_linear_map_end_va()
and get_linear_map_end_pa() and use the right function in
phys_to_virt_tee_ram() and is_unpaged().

This fixes occasional errors like:
E/TC:0 0 Panic 'can't find mmu tables' at core/arch/arm/mm/tee_pager.c:549 <tee_pager_early_init>
E/TC:0 0 TEE load address @ 0x50b9000
E/TC:0 0 Call stack:
E/TC:0 0 0x050bf144

with paging and ASLR enabled.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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