1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2022, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32_iwdg.h> 13 #include <drivers/stm32_tamp.h> 14 #include <drivers/stm32_uart.h> 15 #include <drivers/stm32mp1_etzpc.h> 16 #include <drivers/stm32mp_dt_bindings.h> 17 #include <kernel/boot.h> 18 #include <kernel/dt.h> 19 #include <kernel/interrupt.h> 20 #include <kernel/misc.h> 21 #include <kernel/panic.h> 22 #include <kernel/spinlock.h> 23 #include <mm/core_memprot.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stm32_util.h> 27 #include <trace.h> 28 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE); 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE); 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE); 36 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB3_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB4_BASE, APB4_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB5_BASE, APB5_SIZE); 40 #ifdef CFG_STM32MP13 41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB6_BASE, APB6_SIZE); 42 #endif 43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 46 47 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 48 49 #define _ID2STR(id) (#id) 50 #define ID2STR(id) _ID2STR(id) 51 52 static TEE_Result platform_banner(void) 53 { 54 #ifdef CFG_EMBED_DTB 55 IMSG("Platform stm32mp1: flavor %s - DT %s", 56 ID2STR(PLATFORM_FLAVOR), 57 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 58 #else 59 IMSG("Platform stm32mp1: flavor %s - no device tree", 60 ID2STR(PLATFORM_FLAVOR)); 61 #endif 62 63 return TEE_SUCCESS; 64 } 65 service_init(platform_banner); 66 67 /* 68 * Console 69 * 70 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 71 * trace console. Value 0 disables the early console. 72 * 73 * We cannot use the generic serial_console support since probing 74 * the console requires the platform clock driver to be already 75 * up and ready which is done only once service_init are completed. 76 */ 77 static struct stm32_uart_pdata console_data; 78 79 void console_init(void) 80 { 81 /* Early console initialization before MMU setup */ 82 struct uart { 83 paddr_t pa; 84 bool secure; 85 } uarts[] = { 86 [0] = { .pa = 0 }, 87 [1] = { .pa = USART1_BASE, .secure = true, }, 88 [2] = { .pa = USART2_BASE, .secure = false, }, 89 [3] = { .pa = USART3_BASE, .secure = false, }, 90 [4] = { .pa = UART4_BASE, .secure = false, }, 91 [5] = { .pa = UART5_BASE, .secure = false, }, 92 [6] = { .pa = USART6_BASE, .secure = false, }, 93 [7] = { .pa = UART7_BASE, .secure = false, }, 94 [8] = { .pa = UART8_BASE, .secure = false, }, 95 }; 96 97 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 98 99 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 100 return; 101 102 /* No clock yet bound to the UART console */ 103 console_data.clock = NULL; 104 105 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 106 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 107 108 register_serial_console(&console_data.chip); 109 110 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 111 } 112 113 #ifdef CFG_EMBED_DTB 114 static TEE_Result init_console_from_dt(void) 115 { 116 struct stm32_uart_pdata *pd = NULL; 117 void *fdt = NULL; 118 int node = 0; 119 TEE_Result res = TEE_ERROR_GENERIC; 120 121 fdt = get_embedded_dt(); 122 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 123 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 124 fdt = get_external_dt(); 125 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 126 if (res == TEE_ERROR_ITEM_NOT_FOUND) 127 return TEE_SUCCESS; 128 if (res != TEE_SUCCESS) 129 return res; 130 } 131 132 pd = stm32_uart_init_from_dt_node(fdt, node); 133 if (!pd) { 134 IMSG("DTB disables console"); 135 register_serial_console(NULL); 136 return TEE_SUCCESS; 137 } 138 139 /* Replace early console with the new one */ 140 console_flush(); 141 console_data = *pd; 142 free(pd); 143 register_serial_console(&console_data.chip); 144 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 145 146 return TEE_SUCCESS; 147 } 148 149 /* Probe console from DT once clock inits (service init level) are completed */ 150 service_init_late(init_console_from_dt); 151 #endif 152 153 /* 154 * GIC init, used also for primary/secondary boot core wake completion 155 */ 156 static struct gic_data gic_data; 157 158 void itr_core_handler(void) 159 { 160 gic_it_handle(&gic_data); 161 } 162 163 void main_init_gic(void) 164 { 165 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 166 itr_init(&gic_data.chip); 167 168 stm32mp_register_online_cpu(); 169 } 170 171 void main_secondary_init_gic(void) 172 { 173 gic_cpu_init(&gic_data); 174 175 stm32mp_register_online_cpu(); 176 } 177 178 static TEE_Result init_stm32mp1_drivers(void) 179 { 180 /* Without secure DTB support, some drivers must be inited */ 181 if (!IS_ENABLED(CFG_EMBED_DTB)) 182 stm32_etzpc_init(ETZPC_BASE); 183 184 /* Secure internal memories for the platform, once ETZPC is ready */ 185 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 186 etzpc_lock_tzma(0); 187 188 #ifdef CFG_TZSRAM_START 189 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 190 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 191 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 192 #endif /* CFG_TZSRAM_START */ 193 194 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 195 etzpc_lock_tzma(1); 196 197 return TEE_SUCCESS; 198 } 199 200 service_init_late(init_stm32mp1_drivers); 201 202 static TEE_Result init_late_stm32mp1_drivers(void) 203 { 204 TEE_Result res = TEE_ERROR_GENERIC; 205 206 /* Set access permission to TAM backup registers */ 207 if (IS_ENABLED(CFG_STM32_TAMP)) { 208 struct stm32_bkpregs_conf conf = { 209 .nb_zone1_regs = TAMP_BKP_REGISTER_ZONE1_COUNT, 210 .nb_zone2_regs = TAMP_BKP_REGISTER_ZONE2_COUNT, 211 }; 212 213 res = stm32_tamp_set_secure_bkpregs(&conf); 214 if (res == TEE_ERROR_DEFER_DRIVER_INIT) { 215 /* TAMP driver was not probed if disabled in the DT */ 216 res = TEE_SUCCESS; 217 } 218 if (res) 219 panic(); 220 } 221 222 return TEE_SUCCESS; 223 } 224 225 driver_init_late(init_late_stm32mp1_drivers); 226 227 vaddr_t stm32_rcc_base(void) 228 { 229 static struct io_pa_va base = { .pa = RCC_BASE }; 230 231 return io_pa_or_va_secure(&base, 1); 232 } 233 234 vaddr_t get_gicd_base(void) 235 { 236 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 237 238 return io_pa_or_va_secure(&base, 1); 239 } 240 241 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 242 { 243 cfg->base = BSEC_BASE; 244 cfg->upper_start = STM32MP1_UPPER_OTP_START; 245 cfg->max_id = STM32MP1_OTP_MAX_ID; 246 } 247 248 bool stm32mp_is_closed_device(void) 249 { 250 uint32_t otp = 0; 251 TEE_Result result = TEE_ERROR_GENERIC; 252 253 /* Non closed_device platform expects fuse well programmed to 0 */ 254 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 255 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 256 return false; 257 258 return true; 259 } 260 261 bool __weak stm32mp_with_pmic(void) 262 { 263 return false; 264 } 265 266 uint32_t may_spin_lock(unsigned int *lock) 267 { 268 if (!lock || !cpu_mmu_enabled()) 269 return 0; 270 271 return cpu_spin_lock_xsave(lock); 272 } 273 274 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 275 { 276 if (!lock || !cpu_mmu_enabled()) 277 return; 278 279 cpu_spin_unlock_xrestore(lock, exceptions); 280 } 281 282 static vaddr_t stm32_tamp_base(void) 283 { 284 static struct io_pa_va base = { .pa = TAMP_BASE }; 285 286 return io_pa_or_va_secure(&base, 1); 287 } 288 289 static vaddr_t bkpreg_base(void) 290 { 291 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 292 } 293 294 vaddr_t stm32mp_bkpreg(unsigned int idx) 295 { 296 return bkpreg_base() + (idx * sizeof(uint32_t)); 297 } 298 299 static bool __maybe_unused bank_is_valid(unsigned int bank) 300 { 301 if (IS_ENABLED(CFG_STM32MP15)) 302 return bank == GPIO_BANK_Z || bank <= GPIO_BANK_K; 303 304 if (IS_ENABLED(CFG_STM32MP13)) 305 return bank <= GPIO_BANK_I; 306 307 panic(); 308 } 309 310 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 311 { 312 static struct io_pa_va base = { .pa = GPIOA_BASE }; 313 314 static_assert(GPIO_BANK_A == 0); 315 assert(bank_is_valid(bank)); 316 317 if (IS_ENABLED(CFG_STM32MP15)) { 318 static struct io_pa_va zbase = { .pa = GPIOZ_BASE }; 319 320 /* Get secure mapping address for GPIOZ */ 321 if (bank == GPIO_BANK_Z) 322 return io_pa_or_va_secure(&zbase, GPIO_BANK_OFFSET); 323 324 /* Other are mapped non-secure */ 325 return io_pa_or_va_nsec(&base, (bank + 1) * GPIO_BANK_OFFSET) + 326 (bank * GPIO_BANK_OFFSET); 327 } 328 329 if (IS_ENABLED(CFG_STM32MP13)) 330 return io_pa_or_va_secure(&base, 331 (bank + 1) * GPIO_BANK_OFFSET) + 332 (bank * GPIO_BANK_OFFSET); 333 334 panic(); 335 } 336 337 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 338 { 339 assert(bank_is_valid(bank)); 340 341 if (bank == GPIO_BANK_Z) 342 return 0; 343 344 return bank * GPIO_BANK_OFFSET; 345 } 346 347 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 348 { 349 assert(bank_is_valid(bank)); 350 351 #ifdef CFG_STM32MP15 352 if (bank == GPIO_BANK_Z) 353 return GPIOZ; 354 #endif 355 356 return GPIOA + bank; 357 } 358 359 struct clk *stm32_get_gpio_bank_clk(unsigned int bank) 360 { 361 assert(bank_is_valid(bank)); 362 363 if (!IS_ENABLED(CFG_DRIVERS_CLK)) 364 return NULL; 365 366 return stm32mp_rcc_clock_id_to_clk(stm32_get_gpio_bank_clock(bank)); 367 } 368 369 #ifdef CFG_STM32_IWDG 370 TEE_Result stm32_get_iwdg_otp_config(paddr_t pbase, 371 struct stm32_iwdg_otp_data *otp_data) 372 { 373 unsigned int idx = 0; 374 uint32_t otp_value = 0; 375 376 switch (pbase) { 377 case IWDG1_BASE: 378 idx = 0; 379 break; 380 case IWDG2_BASE: 381 idx = 1; 382 break; 383 default: 384 panic(); 385 } 386 387 if (stm32_bsec_read_otp(&otp_value, HW2_OTP)) 388 panic(); 389 390 otp_data->hw_enabled = otp_value & 391 BIT(idx + HW2_OTP_IWDG_HW_ENABLE_SHIFT); 392 otp_data->disable_on_stop = otp_value & 393 BIT(idx + HW2_OTP_IWDG_FZ_STOP_SHIFT); 394 otp_data->disable_on_standby = otp_value & 395 BIT(idx + HW2_OTP_IWDG_FZ_STANDBY_SHIFT); 396 397 return TEE_SUCCESS; 398 } 399 #endif /*CFG_STM32_IWDG*/ 400