1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 3flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 4flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 5flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 6 7flavor_dts_file-135F_DK = stm32mp135f-dk.dts 8 9flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 10 $(flavor_dts_file-135F_DK) 11 12flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 13 14flavorlist-cryp-1G = $(flavor_dts_file-157C_ED1) \ 15 $(flavor_dts_file-157C_EV1) 16 17flavorlist-no_cryp = $(flavorlist-no_cryp-512M) 18 19flavorlist-512M = $(flavorlist-cryp-512M) \ 20 $(flavorlist-no_cryp-512M) 21 22flavorlist-1G = $(flavorlist-cryp-1G) 23 24flavorlist-MP15 = $(flavor_dts_file-157A_DK1) \ 25 $(flavor_dts_file-157C_DK2) \ 26 $(flavor_dts_file-157C_ED1) \ 27 $(flavor_dts_file-157C_EV1) 28 29flavorlist-MP13 = $(flavor_dts_file-135F_DK) 30 31ifneq ($(PLATFORM_FLAVOR),) 32ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 33$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 34endif 35CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 36endif 37 38ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 39$(call force,CFG_STM32_CRYP,n) 40endif 41 42ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 43$(call force,CFG_STM32MP13,y) 44endif 45 46ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 47$(call force,CFG_STM32MP15,y) 48endif 49 50# CFG_STM32MP1x switches are exclusive. 51# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 52# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 53ifeq ($(CFG_STM32MP13),y) 54$(call force,CFG_STM32MP15,n) 55else 56$(call force,CFG_STM32MP15,y) 57$(call force,CFG_STM32MP13,n) 58endif 59ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 60$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 61endif 62ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 63$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 64endif 65 66include core/arch/arm/cpu/cortex-a7.mk 67 68$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 69$(call force,CFG_DRIVERS_CLK,y) 70$(call force,CFG_DRIVERS_CLK_FIXED,n) 71$(call force,CFG_GIC,y) 72$(call force,CFG_INIT_CNTVOFF,y) 73$(call force,CFG_PSCI_ARM32,y) 74$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 75$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 76$(call force,CFG_SM_PLATFORM_HANDLER,y) 77$(call force,CFG_STM32_SHARED_IO,y) 78 79ifeq ($(CFG_STM32MP13),y) 80$(call force,CFG_CORE_RESERVED_SHM,n) 81$(call force,CFG_STM32MP_CLK_CORE,y) 82$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 83$(call force,CFG_STM32MP13_CLK,y) 84$(call force,CFG_STM32MP15_CLK,n) 85CFG_STM32MP_OPP_COUNT ?= 2 86else # Default to STM32MP15 87$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 88$(call force,CFG_STM32MP15_CLK,y) 89CFG_CORE_RESERVED_SHM ?= y 90endif 91 92CFG_TEE_CORE_NB_CORE ?= 2 93CFG_WITH_PAGER ?= y 94CFG_WITH_LPAE ?= y 95CFG_WITH_SOFTWARE_PRNG ?= y 96CFG_MMAP_REGIONS ?= 23 97CFG_DTB_MAX_SIZE ?= (256 * 1024) 98CFG_CORE_ASLR ?= n 99 100ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),) 101# Some drivers mandate DT support 102$(call force,CFG_DRIVERS_CLK_DT,n) 103$(call force,CFG_STM32_CRYP,n) 104$(call force,CFG_STM32_GPIO,n) 105$(call force,CFG_STM32_I2C,n) 106$(call force,CFG_STM32_IWDG,n) 107$(call force,CFG_STM32_TAMP,n) 108$(call force,CFG_STPMIC1,n) 109$(call force,CFG_STM32MP1_SCMI_SIP,n) 110$(call force,CFG_SCMI_PTA,n) 111else 112$(call force,CFG_DRIVERS_CLK_DT,y) 113endif 114 115ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 116CFG_TZDRAM_START ?= 0xde000000 117CFG_DRAM_SIZE ?= 0x20000000 118endif 119 120CFG_DRAM_BASE ?= 0xc0000000 121CFG_DRAM_SIZE ?= 0x40000000 122CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 123CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 124ifeq ($(CFG_STM32MP15),y) 125CFG_TZDRAM_START ?= 0xfe000000 126CFG_TZDRAM_SIZE ?= 0x01e00000 127CFG_TZSRAM_START ?= 0x2ffc0000 128CFG_TZSRAM_SIZE ?= 0x0003f000 129ifeq ($(CFG_CORE_RESERVED_SHM),y) 130CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 131CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 132endif 133else 134CFG_TZDRAM_SIZE ?= 0x02000000 135CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 136endif #CFG_STM32MP15 137 138CFG_STM32_BSEC ?= y 139CFG_STM32_CRYP ?= y 140CFG_STM32_ETZPC ?= y 141CFG_STM32_GPIO ?= y 142CFG_STM32_I2C ?= y 143CFG_STM32_IWDG ?= y 144CFG_STM32_RNG ?= y 145CFG_STM32_RSTCTRL ?= y 146CFG_STM32_TAMP ?= y 147CFG_STM32_UART ?= y 148CFG_STPMIC1 ?= y 149CFG_TZC400 ?= y 150 151ifeq ($(CFG_STPMIC1),y) 152$(call force,CFG_STM32_I2C,y) 153$(call force,CFG_STM32_GPIO,y) 154endif 155 156# if any crypto driver is enabled, enable the crypto-framework layer 157ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 158$(call force,CFG_STM32_CRYPTO_DRIVER,y) 159endif 160 161CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 162$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 163 164CFG_WDT ?= $(CFG_STM32_IWDG) 165 166# Platform specific configuration 167CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 168 169# SiP/OEM service for non-secure world 170CFG_STM32_BSEC_SIP ?= y 171CFG_STM32MP1_SCMI_SIP ?= n 172ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 173$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 174$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 175$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 176endif 177 178# Default enable SCMI PTA support 179CFG_SCMI_PTA ?= y 180ifeq ($(CFG_SCMI_PTA),y) 181$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 182$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 183CFG_SCMI_MSG_SHM_MSG ?= y 184CFG_SCMI_MSG_SMT ?= y 185endif 186 187CFG_SCMI_MSG_DRIVERS ?= n 188ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 189$(call force,CFG_SCMI_MSG_CLOCK,y) 190$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 191CFG_SCMI_MSG_SHM_MSG ?= y 192CFG_SCMI_MSG_SMT ?= y 193CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 194$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 195endif 196 197ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 198CFG_HWRNG_PTA ?= y 199endif 200ifeq ($(CFG_HWRNG_PTA),y) 201$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 202$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 203$(call force,CFG_HWRNG_QUALITY,1024) 204endif 205 206# Provision enough threads to pass xtest 207ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 208ifeq ($(CFG_WITH_PAGER),y) 209CFG_NUM_THREADS ?= 3 210else 211CFG_NUM_THREADS ?= 10 212endif 213endif 214 215# Default enable some test facitilites 216CFG_ENABLE_EMBEDDED_TESTS ?= y 217CFG_WITH_STATS ?= y 218 219# Enable to allow debug 220CFG_STM32_BSEC_WRITE ?= $(CFG_TEE_CORE_DEBUG) 221 222# Default disable some support for pager memory size constraint 223ifeq ($(CFG_WITH_PAGER),y) 224CFG_TEE_CORE_DEBUG ?= n 225CFG_UNWIND ?= n 226CFG_LOCKDEP ?= n 227CFG_TA_BGET_TEST ?= n 228# Default disable early TA compression to support a smaller HEAP size 229CFG_EARLY_TA_COMPRESS ?= n 230CFG_CORE_HEAP_SIZE ?= 49152 231endif 232 233# Non-secure UART and GPIO/pinctrl for the output console 234CFG_WITH_NSEC_GPIOS ?= y 235CFG_WITH_NSEC_UARTS ?= y 236# UART instance used for early console (0 disables early console) 237CFG_STM32_EARLY_CONSOLE_UART ?= 4 238